Accumulation

𝛘 VG
𝑞𝜙! Ev
Ev
EG Ef EG Ei
EG
Ei Ef
EG
EC EC

𝑞𝜙! Ev
EG
qV EG
Ei 𝑞𝜙! Ev
EG
EC qV EG Ei
Ef
EC
 Depletion and Inversion
Ev
qV VG EG
EG Ei
EG Ev Ef
EG Ei qV EC
Ef
EC

Ev
EG
EG Ei
qV Ef
EG Ev EC
qV
EG Ei
Ef
EC

Inversion Inversion
Strong Inversion

Onset of inversion when

𝐸# % − 𝐸( = 𝐸( − 𝐸# %
$%&' )%*+,-.

EG !" #!$
qV At this stage, the concentration of holes 𝑝 = 𝑛# 𝑒 %&

𝑞𝜙" Ev
Is same as the concentration of electrons in the bulk of the n-type
EG 𝑞𝜙
Ei " semiconductor
Ef
EC The surface is inverted!
Any further increase in potential, will not cause increase in the
Inversion depletion width, but further accumulation of holes in the surface.
 We are still considering the situation, where the
workfunction of metal and semiconductor are the
same – Flat band assumption

P-Type substrate

How to find the potential Δψ distribution in the material ?

Poisson’s equation
V Potentials are fixed at the end
𝑑/ Δ𝜓 𝑑ℇ 𝜌
=− =−
𝑑𝑥 / 𝑑𝑥 𝜖

𝜌 𝑥 = 𝑞 𝑝 𝑥 − 𝑛 𝑥 + 𝑁01 𝑥 − 𝑁23 𝑥

There are basically two kinds of charge in the semiconductor:

1. Depletion charge
2. Mobile carrier charge
The spatial variation of the potential gives an idea about the charge configuration

Let us take the potential at the surface to be 𝜓4 = Δ𝜓(0) and the potential at end of bulk to be zero
𝜓 𝑥 →∞ =0
Remember, there are no charges in the insulator.
𝜌56 = 0 → ℇ56 = 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡 → 𝜓56 = 𝐶𝑥

Thus the bands in the oxide vary linearly. If the semiconductor surface potential is taken to be 𝜓4

Then 𝑉,77& = ℇ56 𝑥 + 𝜓)

Remember, bands are energy levels, and the potential at the point E/q
Ev
The potential (Δ𝜓(𝑥)) at any point is the extent of bending in the bands

EG Ei
For a p-type material, the hole density is given by
𝑝 = 𝑛# 𝑒 (9" 39$)/<= Δ𝜓(𝑥)
Ef
Let 𝑞𝜙7 = 𝐸# − 𝐸( at the bulk
>?'
𝑁2 = 𝑛# 𝑒 <= EC

At any point in x, 𝐸# 𝑥 = 𝐸# − qΔ𝜓 𝑥

Thus, the hole density at any point is given by

>@' A@ BA@
3 <= 3 <=
𝑝 𝑥 = 𝑛# 𝑒 <= 𝑒 = 𝑁2 𝑒

However, remember the law of mass action holds

everywhere 𝑛 𝑥 𝑝 𝑥 = 𝑛#/

""( *+,
Therefore, the electron density 𝑛 𝑥 = 𝑒 %&
C)

𝑞 3
>A@ >A@
𝜌 𝑥 = − 𝑁2 𝑒 <= − 1 − 𝑁0 𝑒 <= − 1
𝜖

Let 𝑄) be the space charge density ∫ 𝜌) 𝑑𝑥 over a very

small region near the surface.

𝑄) = −𝜖ℇ)
Accumulation :

When a negative potential is applied to the metal, the bands bend in the opposite direction.

Δ𝜓 is negative.

*+,
3 (%&
𝑝 𝑥 goes exponentially with Δ𝜓 and the surface charge density goes as 𝑄) 𝛼 𝑒 (2KT comes due to
integration over space

The charge density is due to mobile holes, the charges pile up near the interface due to the field on the
oxide. Typical accumulation thickness is about ~20 nm from the surface .

The exponential ensures that the band bending Δ𝜓 is small, almost pinned to zero for most practical
potentials.
Depletion:
When a small positive potential is applied: Δ𝜓 is positive.

The hole concentration is now lower than the bulk hole concentration. The electron concentration is also not large.

This causes depletion at the surface .

/D@-
The width of depletion region goes as square root of potential 𝑊0 =
>C)

Ev
EG
EG Ei
The square root dependence on the surface potential can be noted on Qs. Ef
qV EC
Strong Inversion:
Onset of strong inversion is when electron density is same as the bulk hole density

𝑛#/ >A@
𝑛) = 𝑛 0 = 𝑁2 = 𝑒 <=
𝑁2

This means, the Ei at the surface is as far away from the Fermi level as the bulk material is, but in opposite direction

Δ𝜓 = 2𝜙7

At the onset of inversion, the semiconductor no longer gets depleted. So, a maximum in depletion width is obtained.
1
0) (
D- <=&"
/D- @- "./ .(
"
Maximum depletion width 𝑊! = =𝑞
>C) > ( C)
Charges in the material
Ev
EG
EG Ei
Ev
EG Ef
EG Ei
EC
Ef qV
EC

Inversion

0 0 w
w
 1
The total charge in the depletion width 𝑄E = −𝑞𝑁2 𝑊! = −2 𝑞𝜖) 𝑁2 𝜓7 (

Just before the strong inversion, the surface potential is 𝜓) = 2𝜓7

F2
The potential drop across the oxide 𝜓56 = −
G34

H2
Therefore, the bias voltage required on the metal to achieve strong inversion 𝑉= = − + 2𝜓7
G34

This is an important quality of a Metal-Oxide-Semiconductor interfaces and MOS transistor.

 Non-idealities

Work function difference between metal and semiconductor: 𝜙!) ! = 0

𝑞𝜙) 𝛘
𝑞𝜙)
Ev Ef
𝛘 𝑞𝜙!
𝑞𝜙! EG
Ev EG Ei
EG Ef
EG EC
Ei

EC
𝑞𝜙)

𝛘
𝑞𝜙!
Ev
EG
EG Ef
Ei

EC
Condition to achieve flat band

𝑞𝜙)

𝑞𝜙) 𝛘 𝛘
𝑞𝜙!
Ev Ef Ev
𝑞𝜙! EG
EG EG Ef
EG Ei Ei

EC EC

𝜙!) is positive. Bands bend up to deplete the electrons at the surface.

To achieve flat band, the metal Fermi level should be shifted down, with respect to semiconductor Fermi level.

This is achieved by applying a positive potential. 𝑉(I = 𝜙!)

Thus the semiconductor is already depleted to begin with.

Infact, when the 𝜙!) is sufficiently high, an inversion layer can exist even without application of external bias!
What happens on the other side:

𝑞𝜙) 𝛘
𝑞𝜙) 𝛘 Ev
𝑞𝜙! 𝑞𝜙! EG
Ev Ei
EG EG
EG Ef Ef
Ei
EC
EC

When 𝜙!) is negative ?

It is clear, the Fermi level of the metal needs to be pushed up,
To obtain flat band. A negative potential on the metal will push it up

So 𝑉 = 𝐹(I = 𝜙!) is required to achieve flat band!

Effect of oxide charge density

Formation of junctions: Example Metal – Insulator – Semiconductor Junction

Thermal oxidation: “The main reason for dominance of Si is the existence of a stable oxide and good Si-SiO2 interface.”

Most common technique to form oxides – Thermal oxidation.

1. Batch of wafer are placed in Quartz boats inside a quartz tube.

2. Tube heated to about 800 – 1000 °C in a furnace.
3. Oxide is grown on top of Si using two techniques (dry O2 gas or steam)

𝑆𝑖 + 𝑂/ → 𝑆𝑖𝑂/
𝑆𝑖 + 2𝐻/ 𝑂 → 𝑆𝑖𝑂/ + 2𝐻/
4. In both cases, Si at the surface is consumed and oxide layer is formed.
5. For every μm of SiO2 grown, 0.44 μm Si is consumed. 2.2 times the volume of Si consumed is obtained as SiO2 layer.
 Bulk oxide charge densities
Most common contaminant in furnaces – Alkali metals

They tend to introduce positive charge densities in the bulk of oxides .

Qf
Na+
The effect of the ion charges depends on the position and the density.
Na+ Qf

The alkali ions are very small and mobile. They are influenced by the gate field
+ + +
as well as by the other drain-source potentials

Interfacial charge densities

Si
An ideal interface is formed when all the Si atoms at the surface is coordinated
right

However, it does not happen and some Si atoms at the interface remain as Si,

Leading to positive interface charge densities. [Remember the way SiO2 is

grown]
 All the bulk and interface charge densities are typically positive.

Generally, all the oxide charges are taken into a single term 𝑄56 = 𝑄+ + 𝑄#J

The effect of this positive charge density is to introduce field in the oxide, which attracts electrons in the semiconductor.

This will make the bands in the semiconductor to bend down.

To make these bands flat, a negative voltage is typically required to make a flat band.

-negative sign of Qox is 𝑞𝜙) 𝛘

because the charges are Ev
𝑞𝜙! + EG Thus the total potential
taken to be positive and a required for flatband
Ei
negative potential is EG
required to remove the Ef H
excess electrons EC 𝑉(I = 𝜙!) − G34
34
accumulating at the
interface
 The threshold voltage:

𝑄$
𝑉! = 𝑉"# − + 2𝜙'
𝐶%&

The potential at the gate should first offset

1. non-ideality [Flat band potential]

2. Deplete the carriers at the interface
3. Invert the surface
4. Generate enough carriers to match the bulk majority carrier density
Let us take an example problem:

What potential is required to invert a P-type Silicon surface with doping density 5 x 1015 cm15
with an interface trap charge density 4 x 1010 /cm2. Assume oxide is 10 nm thick.

We should first assume metal and semiconductor work functions are the same.

D5" ( KL#17
Oxide capacitance 𝐶56 = = 3.9 ∗ 8.85 ∗ = 3.45 ∗ 103M 𝐹/𝑐𝑚/
KL#6 -!( KL#6

H N∗KL18∗K.Q∗KL#19
The flat band potential 𝑉(I = 𝜙!) − G34 = − R.NS ∗KL#:
= 0.019 𝑉
34

The Fermi level is below the Intrinsic level is given by

𝑘𝑇 𝑁2 5 ∗ 10KS
𝜙7 = ln = 0.026 ∗ ln = 0.329 𝑒𝑉
𝑞 𝑛# 1.5 ∗ 10KL
Maximum width of the depletion before strong inversion
𝜖𝜙7
𝑊! = 2 = 0.415 𝜇𝑚
𝑞𝑁2
The total charge in the depletion

𝑄0 = −𝑞𝑁2 𝑊! = −1.6 ∗ 103KT ∗ 5 ∗ 10KS ∗ 4.15 ∗ 103S = −3.32 ∗ 103U 𝐶/𝑐𝑚/

The total threshold potential

𝑄0
𝑉= = 𝑉(I − + 2𝜙7
𝐶56

103U
𝑉= = −0.010 + 0.658 + 3.32 ∗ = +0.74 𝑉
3.45 ∗ 103M

Variation of threshold voltage for different doping density

- Onset of strong inversion.

1. Negative threshold voltage for p-type means, you need to apply

the potential to invert
2. Negative threshold voltage for n-type means, even in the
absence of gate potential, the surface is inverted.
3. This means, the channel is normally conducting! We will soon
see such situations are bad for device applications
Capacitance measurements
 Equivalent circuit

MOS Capacitor Cit

There are different charge distribution in the semiconductor: Ci
1. Mobile charges localized at the interface
2. Fixed charge density in the insulator Cd
3. Depletion charge near the interface

The total potential is distributed across the oxide and the semiconductor

𝑉 = 𝑉56 + 𝜓)
Realistic case: MOS – CV measurement:
For a Ptype substrate:

1. A negative potential will cause accumulation.

Cox
1. If you assume flat band condition, for small positive
potentials, there is a small depletion near the
interface due to charge screening. The length of Cfb
depletion is related to the screening length/Debye
length (distance by which charge inhomogeneities are
screened. We have weak accumulation
1 1 %&
𝐶! = +
𝐶"# 𝐶$
1. Further increase in negative potentials will lead to VFB
0
large hole concentration at the surface that cannot be VG
screened. The only capacitance that is left is now the
oxide capacitance. We have strong accumulation
2. If the non idealisties are considered, the bands can
bend even further, leading to lower total capacitance
 Weak
Weak
Accumulation
inversion
The insulator capacitance
𝜖56 Cox
𝐶56 =
𝑑56
Is the maximum capacitance in the structure. Cfb
At positive gate biases, the surface gets depleted.
Cmin
The minimum capacitance is obtained at the maximum depletion width

𝜖)# Strong inversion

𝐶0!#" =
𝑊0!,6
G34 G;
The total capacitance 𝐶= = will be strongly determined by CD VFB VT
G34 1G; 0
Remember, Threshold voltage is when the surface is inverted: charge VG
density at surface is same as the bulk charge density.

Therefore, VT is not obtained when capacitance is minimum,

rather, VT is obtained when the Cox is in series with 2CD
Effect of measurement frequency
Weak
Weak
Accumulation
inversion
Cox Low frequency

Cfb

CLF Cmin
Vac
High Frequency
CHF Strong inversion

VFB VT
0
VG
Two observations at difference between the frequencies:

1. The minimum capacitance is lower in HF

2. Absence of strong inversion at high frequency
Lower Cmin at high frequency:
Interface trap sites can be segregated into fast and slow responding traps sites.

Since each trap site captures charges and screens the potential, there is no need
to deplete the semiconductor further.

Thus, fast traps allow for lower depletion width in the semiconductor and hence
higher over all capacitance.

However, there are always slower traps sites, whose density increases with
increasing measurement frequency. Thus, under such measurements, the
depletion width is higher and hence a overall lower capacitance Cmin is measured.

The measure of fast trap charge density

1 𝐶56 𝐶V( 𝐶56 𝐶W(

𝐷#J = − 𝑐𝑚3/ 𝑉 3K
𝑞 𝐶56 − 𝐶V( 𝐶56 − 𝐶W(
Lack of strong Inversion

Actual measure of capacitance is 𝐶 = 𝑑𝑄,- /𝑑𝑉,-

This measurement is conducted at different DC bias potentials.

When close to strong inversion, for a small dVac the questions is do we accumulate minority carriers
at the interface, or deplete the channel further.

The minority carrier accumulation at the oxide interface requires thermal generation of electrons,
deep depletion of holes at the interface is required to increase the electron density at the interface.

These things require time and depends on the the carrier lifetime and mobility.

Thus, even at frequencies like 1kHz, the mos-CV does not follow the ideal curve.
C – V measurements bottomline:

1. Frequency of measurement determines the ability to invert the channel

2. Presence of fixed oxide charges leads to shift in the spectra (Flat band potential)
3. Nonzero ɸms leads to shift in flat band potential
4. Interface trap-charge density leads to lower minimum capacitance.
Can we keep inverting ?
𝑞𝜙)

𝛘
𝑞𝜙) 𝛘 Ev
Ev 𝑞𝜙! EG
𝑞𝜙! EG Ei
Ei EG
EG Ef
Ef EC
EC

Various tunneling across the interface:

1. Thermal emission
2. Fowler-Nordheim tunneling
Tunneling across the insulator is a major reliability
3. Frenkel-Poole emission concern in modern day devices with shrinking oxide
thickness!
Need for a switch:

Diodes
• Devices which current blocking characteristics used in rectifiers
• Varactors used in microwave devices and filters

Switches
• Three terminal devices useful in logic calculations
• Derived from vacuum tube devices used in computation
 Electronic switch family
Switches

Field Effect Transistor Potential Effect Transistor

contact contact
MESFET JFET IG-FET
(Insulated gate) Channel
(Schottky gate) (p-n junction fet)

MOSFET H-FET

MODFET HiGFET
(doped high-Eg) (undoped high-Eg)
Advantages of FET

• The gate (insulated terminal) is formed either by oxide (MOSFET)/depletion width

(JFET/MESFET)
• High input impedance
• Input matched with microwave circuits
• Can integrate multiple devices to same feed line
• Negative temperature coefficient, prevents thermal runaway
• No minority storage time/recovery
• Steep turn-on and turn off
Structure of MOS-FET
Equilibrium band structure

Equilibrium structure has band bending and depletion at junctions to prevent change carrier exchange
Channel Inversion

The P-type substrate is

inverted to have a n-
channel by applying a
positive gate voltage
 Under Drain and Gate Bias – Source grounded

Drain potential tend to off-set the

gate potential, reduce electron
population near the drain.
 Effect of inversion under appropriate gate bias
Potential at the semiconductor-oxide surface 𝜓) = 2𝜙7 = 2𝜙$

The source potential changes the surface potential:

let the change in the potential be 𝜓# 𝑦

The total potential at the surface is now 𝜓) 𝑦 = 2𝜙$ + 𝜓# 𝑦

X< 3@-
The electric field in the oxide ℰ56 =
J34

/>C)@-
The electric field in the semiconductor ℰ) = D-

H
Gauss Law: Electric flux Φ =
D
Flux emanating from a volume enclosed by a surface 𝜎
Thermal Equilibrium

Metal
Depletion
Gate oxide

P-Type
Source and Drain diffusions

Metal
Depletion Gate oxide

N-Type N-Type

P-Type
MOSFET with Gate Bias VG

Metal
Depletion Gate oxide

N-Type N-Type

P-Type
MOSFET with Gate Bias VG

Metal
Depletion Gate oxide

N-Type N-Type

P-Type
 y

Let us imagine a surface 𝜎

Surface density (Q) oxide
The electric flux Φ = ∯ 𝐸. 𝑑𝐴
Semi
Assume things do not change in the x direction

Then the charge density varies along the y direction as

𝑉Y − 𝜓) 2𝑞𝑁2 𝜓)
𝑄" 𝑦 = 𝜖56 − 𝜖)
𝑡56 𝜖)

D34
If we define the oxide capacitance as 𝐶56 =
Z=>

𝑄" 𝑦 = 𝐶56 𝑉Y − 𝜓) − 2𝑞𝜖4 𝑁2 𝜓)

Ideal Current – voltage relationship

A few assumptions:
1. There are no interface traps sites and we start at flat band approximation
2. Current is mostly drift (what ever is the variation in charge in y, is not that significant for diffusion)
3. Channel doping is uniform and there is negligible reverse current
4. The gate field is much larger than the source-drain field (Gradual channel approximation)

Current at any point y is given by 𝐼 𝑦 = 𝑒𝑊𝑄 𝑦 𝑣

Where W is the width of the channel and v is the velocity

Constant mobility approximation: 𝑣 = 𝜇ℰ

[ V
Length normalized current is given by 𝐼 = 𝑒𝜇 ∫L 𝑄 𝑦 ℰ 𝑦 𝑑𝑦
V
 [ V
Length normalized current is given by 𝐼 = 𝑒𝜇 ∫L 𝑄 𝑦 ℰ 𝑦 𝑑𝑦
V

Field is gradient of potential

𝑒𝜇𝑊 V 𝑑𝜓# 𝑦
𝐼= g 𝑄" 𝑑𝑦
𝐿 L 𝑑𝑦

Changing the limits of integration: The potential varies from 0 at source to VD at the drain

𝑒𝜇𝑊 X;
𝐼= g 𝑄" (𝜓# ) 𝑑𝜓#
𝐿 L

𝑄" 𝑦 = 𝐶56 𝑉Y − 𝜓) − 2𝑞𝜖4 𝑁2 𝜓) 𝜓) 𝑦 = 2𝜙$ + 𝜓# 𝑦

𝑄" 𝑦 = 𝐶56 𝑉Y − 2𝜙$ − 𝜓# 𝑦 − 2𝑞𝜖4 𝑁2 (2𝜙$ + 𝜓# 𝑦 )

𝑊 𝑉0 2 2𝜖) 𝑞𝑁2 R R
𝐼 = 𝜇𝐶56 𝑉Y − 2𝜙$ − 𝑉0 − 𝑉0 + 2𝜙$ / − 2𝜙$ /
𝐿 2 3 𝐶56
 In the presence of non-ideal situations, add the flat band condition 𝑉Y = 𝑉Y − 𝑉(I

𝑊 𝑉0 2 2𝜖) 𝑞𝑁2 R R
𝐼 = 𝜇𝐶56 𝑉Y − 𝑉(I − 2𝜙$ − 𝑉 − 𝑉0 + 2𝜙$ / − 2𝜙$ /
𝐿 2 0 3 𝐶56

Situation: 1 Small VD

𝑊 𝑉0 2 2𝜖) 𝑞𝑁2 𝜙$
𝐼= 𝜇𝐶56 𝑉Y − 𝑉(I − 2𝜙$ − 𝑉0 − 3 𝑉
𝐿 2 3 𝐶56 2 0

2𝜖) 𝑞𝑁2 (2𝜙$ )

𝑉= = 𝑉(I + 2𝜙$ +
𝐶56

𝑊 𝑉0
𝐼0 = 𝜇" 𝐶56 𝑉Y − 𝑉= − 𝑉
𝐿 2 0

The current increases linearly with VD for some extent and then decreases For the condition that 𝑉0 ≪ (𝑉Y − 𝑉= )
according to the equation
Oh, it pinches

As the drain potential is raised, the current according to the approximation reaches a maximum and then decreases.

However, the decrease is unphysical due to the approximations taken

The increase in current with the potential decreases because, the channel is pinched.

The charge density near the drain is reduced due to the drain potential becoming as significant as the gate

The drain depletion width increases.

Pinch-off is a condition when 𝑄 𝑦 = 𝐿 = 0 – That is the edge of the channel first gets depleted.

𝑄" 𝑦 = 𝐶56 𝑉Y − 2𝜙$ − 𝜓# 𝑦 − 2𝑞𝜖4 𝑁2 (2𝜙$ + 𝜓# 𝑦 )

The equation can be solved and the equation for saturation potential is given by

2 𝑉Y − 𝑉(I D>C)
𝑉0),J = Δ𝜓# 𝐿 = 𝑉Y − 𝑉(I − 2𝜙$ + 𝐾 / 1 − 1 + Where 𝐾 =
𝐾/ G34
 Now as before

𝑊 V
𝐼0 = g 𝑄" 𝑦 𝑣 𝑦 𝑑𝑦
𝐿 L

Substitute the pinched off charge density

<
𝑊 /
Where 𝑀 = 1 +
𝐼0 = 𝜇 𝐶 𝑉 − 𝑉= / ??
2𝑀𝐿 " 56 Y

X< 3X&
A more convenient expression for the saturation potential is 𝑉0),J =
\

E];
At any point one can define the conductance 𝜎 =
EX;

In the linear region, there is constant conductance and the conductance drops significantly in the saturation as 𝛿𝜎 → 0
Finally in the nonlinear region, the current can be described by

𝑊 𝑀𝑉0
𝐼0 = 𝜇" 𝐶56 𝑉Y − 𝑉= − 𝑉0
𝐿 2
Threshold and Sub-Threshold

As in the moscap, in the presence of nonzero 𝜙!) and fixed oxide charges 𝑄+

H@ ND>C)??
The threshold voltage 𝑉= = 𝜙!) − G + 2𝜙$ + G34
34

The current in the mosfet is linear for small

drain voltages.

In a real-world mosfet, the linear region of

ID-VG can be employed to identify the
threshold voltage.

The extrapolated voltage (intercept to the

x axis)

1
𝑉6 = 𝑉= + 𝑉0
2
Below the threshold voltage,

In the sub-threshold, there is absence of

inversion region .

So, the current cannot be carried by drift.

𝑁 𝑦
𝐽0 𝑦 = 𝑞𝐷" 𝑑
𝑑𝑦

Remember, y direction is along the S-D axis.

The overall current density can be approximated by

𝑁 𝑆 −𝑁 𝐷
𝐼0 = 𝑊𝑞𝐷"
𝐿
 [; L
Carrier density at the source: 𝑁 𝑆 = ∫L 𝑛 𝑥 𝑑𝑥 = 𝑛7L ∫@ 𝑒 ^?? 𝑑𝜙$
-

Since the potential in the depletion width is known the above expression can be simplified as

1 𝜖
𝑁 𝑠 = 𝑛7L 𝑒 ^@-
𝛽 2𝑞𝜓) 𝑁2

The carrier density at the drain end is lowered exponentially by the drain potential

𝑁 𝐷 = 𝑁 𝑆 𝑒 3^X;

Substituting we get

𝑊 𝜇" ^@
𝐼0 = /
𝑒 - 1 − 𝑒 3^X;
𝐿 𝛽