LAB MANUAL

18EC1L01 DIGITAL ELECTRONIC CIRCUITS

Department of
Electronics and Instrumentation
Engineering

Silicon Institute of Technology

Bhubaneswar
18EC1L01 DIGITAL ELECTRONIC
CIRCUITS LAB
 Type Code L-T-P Credits Marks
Digital Electronic Circuits Lab
PC 18EC1L01 0-0-2 1 100

Objectives The objective of the course is to hands-on exposure on logic gates,

implementation using Boolean algebra, designing digital circuits like
counters, registers and apply the knowledge to formulate digital systems
using HDL.
Pre-Requisites Knowledge of Basic Electronics is required.
Teaching Scheme Regular laboratory experiments to be conducted under supervision of the
faculty with use of ICT as and when required, sessions are planned to be
interactive with focus on implementation in hardware / software tools.

Evaluation Scheme
Daily Lab Test/
Attendance Record Viva-voce Total
Performance Mini Project
10 30 15 30 15 100

Detailed Syllabus
Experiment # Assignment / Experiment
1 Digital Logic Gates: Investigate logic behaviour of AND, OR, NAND, NOR,
EXOR,EX-NOR, Invert and Buffer gates, use of Universal NAND Gate.
2 Combinational Circuit Design: Design, assemble and test: adders and subtractors.
3 Combinational Circuit Design: Code Converters, Gray code to Binary and 7
Segment Display.
4 Universal Gates: Design, implement and test a given design example with (i)
NAND Gates only (ii) NOR Gates only and (iii) using minimum number of
Gates.
5 Multiplexer and De-multiplexer: Design with multiplexers and de-multiplexers.
6 Flip-Flop: Assemble, test and investigate operation of SR, D & J-K flip-flops.
7 Shift Registers: Design and investigate the operation of all types of shift registers.
8 Counters: Design, assemble and test various ripple and synchronous counters -
decimal counter, Binary counter with parallel load.
9 Parallel Adder and Accumulator: Design, implement and test.
10 Binary Multiplier: design and implement a circuit that multiplies 4-bit unsigned
numbers to produce an 8-bit product.
11 Memory Unit: Investigate the behaviour of RAM unit and its storage capacity –
16×4 RAM: testing, simulating and memory expansion.
12 Clock-pulse generator: Design, implement and test.
13 Verilog/VHDL Simulation and implementation of Experiments 2 to 12.

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Text Books:
T1. M. M. Mano and M. D. Ciletti, Digital Design: With an Introduction to Verilog HDL, 5th
Edition, Pearson Education, 2013.
Reference Books:
R1. A. M. Michel´en, Digital Electronics Laboratory Manual, Pearson Education, 2000.
R2. J. W. Stewart & C. -Y. Wang, Digital Electronics Laboratory Experiments: Using the
XilinxXC95108 CPLD with Xilinx Foundation : Design and Simulation Software, 2nd Edition,
Pearson,2004.
Online Resources:
1.
https://www2.mvcc.edu/users/faculty/jfiore/Resources/DigitalElectronics1Laboratory
Manual.pdf
2. https://www.elprocus.com/top-digital-electronic-projects-for-electronicsengineering students/
3. https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-111-
introductory-digital-systems-laboratory-spring-2006/
Course Outcomes: At the end of this course, the students will be able to:
CO1 Analyze the function of logic gates and implementation of Boolean functions.
CO2 Realize Universal gates and Implementation of minimized Boolean Expressions.
CO3 Design and analyze different combinational circuits.
CO4 Design various asynchronous and Synchronous Sequential Circuits.
CO5 Acquire knowledge about internal circuitry and logic behind any digital system.
CO6 Simulate various digital circuits using VHDL in industry standard tool such as Xilinx.

Program Outcomes Relevant to the Course:

Engineering Knowledge: Apply the knowledge of mathematics, science, engineering
PO1 fundamentals, and an engineering specialization to the solution of complex engineering
problems.
Problem Analysis: Identify, formulate, review research literature, and analyse complex
PO2 engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
Design and Development of solution: Design solutions for complex engineering
problems and design system components or processes that meet the specified needs
PO3
with appropriate consideration for the public health and safety, and the cultural and
societal, and environmental considerations.

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 Conduct investigations of complex problems: Use research-based knowledge and
PO4 research methods including design of experiments, analysis and interpretation of data,
and synthesis of the information to provide valid conclusions.
Modern Tool Usage: Create, select, and apply appropriate techniques, resources, and
PO5 modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.
The Engineer and Society: Apply reasoning informed by the contextual knowledge to
PO6 assess societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.

Mapping of COs to POs: (1: Low, 2: Medium, 3: High)

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 3 1 3 3 1
CO2 3 3 1 3 3 1
CO3 3 3 1 3 3 1
CO4 3 1 1 3 3 1
CO5 3 1 1 1 3 1

DO’S AND DONT’S OF THE LABORATORY:

DO’S:
• To be responsible for your own safety and keep the laboratory in a good order, you
must comply with the rules below.
• Solid footwear must be worn by all students inside the laboratory. Staffs are required
by the university to ensure that everyone in the laboratory is wearing solid footwear.
Students with bare feet, thongs, sandals, or other forms of open footwear will not be
allowed into the laboratory.
• Always have your experiment set up checked by a demonstrator before switching on,
and always switch the power off immediately after taking measurements.
• Act sensibly and tidy up after yourself.
• There is a safety switch on each bench which switches power to (and protects) the
GPO's (general purpose outlets/power points).
• Under no circumstances should you attempt to remove any of the panels on the bench.
There is a 230-volt supply behind them which could be lethal.
DON’TS:
• You should not take equipment from another bench. If something is faulty (or missing)
ask the lab staff for assistance.
• No smoking, drinking, or eating is permitted in the laboratory (this includes chewing
gum and confectionaries).
• Do not see directly into the energized waveguide.
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 • Do not touch the Klystron tube as it carries high voltage & heats up too.
• In antenna experiment, it is recommended to not to have any metallic reflectors
near to the setup.
PREFACE:
The aim of this manual is to make the students familiar with designing of Digital Circuits. Digital
Electronics is the branch of Electronics, which deals with digital format of data and codes. (Here
only two conditions are possible, 0 known as low logic and 1 known as high logic).

Digital circuits form the backbone of communication systems, recording devices and many more
systems. Digital Electronics may also refer to the portion of an electronic circuitry responsible for
digital signal conversion. Some devices in this field include multiplexers, gates and decoders. Digital
Electronics is that it is the foundation of modern computers and digital communications. It is
complex digital logic circuits with millions of gates can be built onto a single integrated circuit known
as a microprocessor and these circuits can perform millions of operations per second.

Digital electronics is a fast-expanding field with scope for significant development. This manual
discusses the basics of designing circuits and the functioning of intricate components of a digital
circuit. It presents the fundamental concepts and serves as an excellent guide for an introductory
course on digital electronics. Digital electronic circuits are main thing in digital electronics which
is usually made from large assemblies of logic gates. The system which process discrete values is
known as digital system. The significance of digital electronics is that are inherently more reliable
than analog, in terms of information processing.

LABORATORY ORIENTATION:
OVERALL PURPOSE:
The laboratory portion of this course is designed
• To provide hand-on experience in Circuit design in hardware and using software.
• To provide hands on experience in assembly and Testing of electronics circuit.
• Each laboratory station is equipped with a Power supply, Universal trainer kit.
• Students work in groups, but maintain individual laboratory notebooks and submit
individual reports.
GENERAL COMMENTS:
Every week before the lab, each student should read and prepare for the experiment to be
performed. He/She should work out on the various calculations that are outlined. The student
should refer to the text as prescribed in the course description for the fundamental theory.
The student’s grade will be given on how well he/she has prepared for the lab. Well-
maintenance of laboratory equipment is also the responsibility of students. A constant effort to

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keep the equipment in excellent condition and the working environment well-organized will
result in a productive and safe laboratory. Above all, keep in mind that safety is first!

LABORATORY NOTE BOOK:

Each student should maintain a laboratory notebook according to the following guidelines:
• Obtain a printed material whose pages are consecutively numbered.
• Write name, registration number, course name, section, lab location, semester, and
faculty’s name on the cover page of the experiment.
• Record data by pen, not pencil. Do not use eraser.
• Write the date of experiment and date of submission at the given place.
• Sign at the last page of the experiment.
• Record the instruments settings, and methods used to acquire data.
• Label the axes of a graph with variable names, units, origin, and scales.
• Demonstrate to the lab staff your understanding and achievement of the lab
objectives.
• Have the lab staff’s sign after completing each laboratory session. It is the
responsibility of both the staff and the student to make sure that the data is within
expectation before the student leaves each lab session.
LABORATORY POLICIES AND REPORT FORMAT:
• Reports are due at the beginning of the lab period. The reports are intended to be a
complete documentation of the work done in preparation for and during the lab.
• Lab reports should be submitted on A4 paper.
• Your report is a professional presentation of your work in the lab.
• Neatness, organization, and completeness will be rewarded.
• Points will be deducted for any part that is not clear.
• Copying any post lab will result in a grade of low.
• The incident will be formally reported to the University and the students should follow
the dress code in the Lab session.
• Attendance at your regularly scheduled lab period is required. An unexpected absence
will result in loss of credit for your lab. If for valid reason a student misses a lab, or
makes a reasonable request in advance of the class meeting, it is permissible for the
student to do the lab in a different section later in the week if approved by the faculty
in-charge of both the sections.
• Habitually late students (i.e., students late more than 15 minutes more than once) will
receive 10-point reductions in their grades for each occurrence following the first.
Student attendance less than 75% is detention
• Final grade in this course will be based on laboratory assignments.

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 All labs have an equal weight in the final grade. Grading will be based on laboratory
reports, post-lab and in-lab performance (i.e., completing lab, answering laboratory
related questions, etc.,).The faculty In-charge will ask pertinent questions to individual
members of a team at random.

CONTENTS
Exp. No. LIST OF EXPERIMENTs Page
1 Digital Logic Gates: Investigate logic behavior of AND, OR, NAND, NOR, EX-OR, 1-9
EX-NOR, Invert and Buffer gates, use of Universal (NAND & NOR) Gates.
2 Gate-level minimization: Two level and multi-level implementation of Boolean 10-13
functions.
3 Design, implement and test a given design example with (i) NAND Gates only 14-21
(ii)NOR Gates only and (iii) using minimum number of Gates.
4 Combinational Circuits: design, assemble and test: adders and subtractors. 22-29
5 Design, assemble and test code converters: binary code to gray code, gray code 30-34
to binary and 7 segment displays.
6 Study of Multiplexer, Demultiplexer. Design with multiplexers & de-multiplexer. 35-41
7 Design of Binary to Octal decoder and Implementation of Boolean function 42-46
using decoder
8 Flip-Flop: assemble, test and investigate operation of SR, D, J-K & T flip-flops. 47-55
9 Shift Registers: Design and investigate the operation of all types of shift 56-64
registers with parallel load.
10 Counters: Design, assemble and test various ripple and synchronous counters 65-71
11 Design, assemble and test decimal counter, Binary counter with parallel load. 72-76
12 Memory Unit: Investigate the behavior of RAM unit and its storage capacity – 77-81
16 X4 RAM: testing, simulating and memory expansion.
13 Clock-pulse generator: design, implement and test. 82-86
14 Parallel adder and accumulator: design, implement and test. 87-89
15 Binary Multiplier: design and implement a circuit that multiplies 4-bit unsigned 90-93
numbers to produce a 8-bitproduct.
16 Design, implement and test two-bit magnitude comparator. 94-97
17 Design of special type of counters (four-bit ring counter & Johnson counter) 98-103
using JK flip-flops.
18 Verilog/VHDL simulation and implementation of logic gates. 104-115
19 Verilog/VHDL simulation and implementation of different combinational 116-126
circuits in dataflow and behavioral modeling.

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 20 Verilog/VHDL simulation and implementation of full adder,8-bit adder in 127-133
structural modeling.
21 Verilog/VHDL simulation and implementation of SR-FF,D-FF,JK-FF,T-FF in 134-140
behavioral modeling.

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 EXPERIMENT-1

AIM OF THE EXPERIMENT

Digital Logic Gates: Investigate logic behavior of AND, OR, NAND, NOR, EX-OR, EX-NOR,
Invert and Buffer gates, use of Universal (NAND & NOR) Gates.
OBJECTIVE
• To be familiar with the truth tables of logic gates.
• Identify the 74 Series Integrated circuits (ICs) belong to logic gates and their pin
configurations.
• Test logic behavior (truth tables) of Basic Gates (AND, OR, INVERT) and Derived
Gates (NAND, NOR, EX-OR, EX-NOR) ICs.
• Use of Universal Gates (NAND & NOR) to realize other gates, justify through truth
tables.
COMPONENTS REQUIRED
• IC 7408,IC 7432,IC 7404,IC7400,IC7402,IC7486,IC74266.
• Digital Trainer Kit
• Connecting wires
• Twizer
APPLICATIONS
• Logic gates are the building blocks of combinational logic circuits. You can buy ICs of
logic gates from electronic hobby places. These gates are primarily for hobbyists.
Each chip usually has about 4 logic gates.
• Real computers don't use these kinds of gates, because they take far too much space.
With VLSI technology, you can cram millions of gates onto a wafer no bigger than
that your thumbnail.
THEORY
7400 SERIES ICS LABELLING

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7400 SERIES ICS LABELLING EXAMPLE

7400 SERIES ICS

Part Number Units Description
7400 4 Quad 2 input NAND gate
7402 4 Quad 2 input NOR gate
7404 6 Hex Inverter
7408 4 Quad 2 input AND gate
7432 4 Quad 2 input OR gate
7486 4 Quad 2 input XOR gate
74266 4 Quad 2 input XNOR gate
2-INPUT AND GATE
The AND gate is a digital logic gate with ‘n’ I/Ps (n≥2) and one o/p, which perform logical
conjunction based on the combinations of its inputs. The output of this gate is true only
when all the inputs are true. When one or more inputs of the AND gate’s inputs are false,
then only the output of the AND gate is false.
• The AND gate gives an output of 1 if all inputs are 1, it gives 0 otherwise.
Mathematically,
𝒀 = 𝑨. 𝑩
2-input AND Gate Truth Table of 2- Pin diagram of 7408 quad 2 I/Ps NAND
Input AND Gate Gate

𝒀 = 𝑨. 𝑩

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2-INPUT OR GATE
The OR gate is a digital logic gate with ‘n’ I/Ps ( n≥2) and one O/P, that performs a logical
conjunction based on the combinations of its inputs. The output of the OR gate is true only
when one or more inputs are true. If all the inputs of the gate are false, then only the output
of the OR gate is false.
• The OR gate gives an output of 1 if either one or more inputs are 1, it gives 0 otherwise.
• The OR gate gives an output of 0 if all inputs are 0, it gives 1 otherwise.
Mathematically, 𝒀 = 𝑨+𝑩
2-input OR Gate Truth Table of 2-Input OR Pin diagram of 7432 quad 2 I/Ps
Gate OR Gate

𝒀 = 𝑨+𝑩

NOT (INVERTER) GATE

The NOT gate is a digital logic gate with one input and one output that operates an inverter
operation of the input. The output of the NOT gate is the reverse of the input. When the
input of the NOT gate is true then the output will be false and vice versa. By using this gate,
we can implement NOR and NAND gates.
• The NOT gate gives an output of 1 input is 0 and vice-versa.
Mathematically,
̅
𝒀=𝑨
NOT Gate Truth Table NOT Gate Pin diagram of 7404 Inverter

̅
𝒀=𝑨

2-INPUT NAND GATE

The NAND gate is a digital logic gate with ‘n’ I/Ps ( n≥2 ) and one O/P, that performs the
operation of the AND gate followed by the operation of the NOT gate. NAND gate is designed
by combining the AND gate and NOT gates. If the input of the NAND gate high, then the
output of the gate will be low.

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• The NAND gate (negated AND) gives an output of 0 if all the inputs are 1, it gives 1
otherwise.
• If one or more I/Ps are ‘0’ the O/P will be ‘1’.
Mathematically, 𝒀 = ̅̅̅̅̅
𝑨. 𝑩

2-input NAND Truth Table of 2-Input NAND Pin diagram of 7400 quad 2 I/Ps
Gate Gate NAND Gate

𝒀 = ̅̅̅̅̅
𝑨. 𝑩

2-INPUT NOR GATE

The NOR gate is a digital logic gate with n inputs ( n≥2 ) and one output, that performs the
operation of the OR gate followed by the NOT gate. NOR gate is designed by combining the
OR and NOT gate. When any one of the I/Ps of the NOR gate is true, then the output of the
NOR gate will be false.
• The NOR gate (negated OR) gives an output of 1 if all inputs are 0, it gives 1 otherwise.
• If one or more I/Ps are ‘1’ the O/P will be ‘0’.
Mathematically, 𝒀=𝑨 ̅̅̅̅̅̅̅̅
+𝑩

2-input NOR Gate Truth Table of 2-Input NOR Pin diagram of 7402 quad 2 I/Ps
Gate NOR Gate

𝒀 = ̅̅̅̅̅̅̅̅
𝑨+𝑩

2-INPUT XOR GATE

The Exclusive-OR gate is a digital logic gate with ‘n’ inputs ( n≥2 ) and one output. The short
form of this gate is Ex-OR. It performs based on the operation of OR gate.

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If odd numbers of the inputs of this gate is high, then the output of the EX-OR gate will be
high.
• The XOR gate gives an output of 1 if odd numbers of Inputs are 1, it gives 0 otherwise.
Mathematically,
̅ + 𝑨
𝒀 = 𝑨. 𝑩 ̅. 𝑩
2-input XOR Gate Truth Table of 2-Input Pin diagram of 7486 quad 2 I/Ps XOR
XOR Gate Gate

̅ + 𝑨
𝒀 = 𝑨. 𝑩 ̅. 𝑩

2-INPUT XNOR GATE

The Exclusive-NOR gate is a digital logic gate with ‘n’ inputs (n≥2) and one output. The
short form of this gate is Ex-NOR. It performs based on the operation of NOR gate. When
even numbers of input are high, then the output of the EX-NOR gate will be high.
Otherwise, the output will be low.
• The XNOR gate (negated XOR) gives an output of 1, If even numbers of I/Ps are 1 and 0
otherwise.
̅. 𝑩
Mathematically, 𝒀 = 𝑨 ̅ + 𝑨. 𝑩
2-input XNOR Truth Table of 2-Input Pin diagram of 74266 quad 2 I/Ps
XNOR Gate XNOR Gate
Gate

̅. 𝑩
𝒀 = 𝑨 ̅ + 𝑨. 𝑩

Universal Logic Gates

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Out of the seven logic gates discussed above, NAND and NOR are known as universal gates
since they can be used to implement any digital circuit without using any other gate. This
means that every gate can be created by NAND or NOR gates only.

BUILDING BASIC GATES FROM UNIVERSAL GATES

NOT gate from NAND and NOR

Realization of Basic Logic gates& NOR Realization of Basic Logic gates & NAND
Gate from NAND Gate Gate from NOR Gate

For the XOR gate, NAND and NOR implementation is –

Implemented Using NAND Implemented Using NOR

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 EXPERIMENT-1

Note – For implementing XNOR gate, a single NAND or NOR gate can be added to the above

PRECAUTION
• Make the connections according to the IC Pin diagram.
• Make sure the connections are tight.
• The VCC and ground potential should be applied carefully at the specified pin only.
PROCEDURE
• Fix the ICs on breadboard horizontally but don’t switch on the power supply.
• Connect the positive terminal of the IC i.e., pin 14 to +5volt dc and pin 7 is to be
grounded.
• Give input at pin 1, 2 from input switches & connect pin 3 to an output LED of
breadboard.
• Again, verify the said connection and switch on the ac power supply as well as
breadboard power supply.
• Note the values of output for different combination of inputs (depending on input
switches are ON or OFF mod) & verify the truth table for each gate.
• The output LED will glow when the truth table output is high and will be off when
the truth table output is low.
• Follow the same connection step and verify the truth table for the ICs
7400,7408,7432,7486,74266 except for the ICs 7402,7404.
• Since IC7404 is Hex Inverter (used for NOT gate), it contains six not gates and each
gate is having single input and single output.
• For this, +Vcc and ground pin connections will be same as previous ICs and pin
number 1 will be connected to input switch and pin number 2 will be connected to
output Led of breadboard.
• Then verify the output according to the truth table.
• Similarly, in case of IC7402, +Vcc (+5v dc) and ground will be connected to pin no.14
& pin no. 7 respectively (same as other IC connections).
• Here pin no.2 & 3 will be connected to input switches and pin no.1 will be connected
to output LED of breadboard (reverse as compared to IC7400,7408,7432 etc.)
• Verify the truth table of NOR gate.
[NB: you can verify any one gate of the IC]
• To test the universal NAND and NOR gates or to design any logic gate using NAND or
NOR gate see the connections carefully.
• On the circuit diagram give pin numbers to each input and output as in the ICs and
make connections accordingly (like one output is input of another.

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• Again, verify the said connection and switch on the ac power supply as well as
breadboard power supply.
• Verify the truth table of designed logic gate which is designed using the universal
logic gates.

RESULT ANALYSIS
Observe the truth table of each gate after circuit connection is completed.
CONCLUSION
After completing this experiment
• We became more familiar with the truth tables of logic gates.
• Identified the 74 Series Integrated circuits (ICs) belong to logic gates and their pin
configurations.
• Tested logic behavior (truth tables) of Basic Gates (AND, OR, INVERT) and Derived
Gates (NAND, NOR, EX-OR, EX-NOR) ICs.
• Used universal Gates (NAND & NOR) to realize other gates and justified through truth tables.
QUESTIONNAIRE
1. Realize 2i/p AND gate using NAND gate.
2. Realize 2i/p OR gate using NAND gate.
3. Realize 2i/p EXOR gate using NOR gate.
4. Realize Buffer gate using NOR gate.
5. Define logic gates.
6. What are the basic logic gates?
7. How many universal gates exist? Name them.
8. State the level of input and output of logic gates.
9. Symbol and truth table of AND gate.
10. Why NAND and NOR gates are called universal gates?
11. What is different between Ex-or & Ex-nor gate?
12. Realize XNOR gate.
13. Explain buffer gate?
14. Draw truth table of XOR gate.
15. What is truth table?
16. Draw the pin configuration of IC 7400.
17. How many numbers of pins are available in IC 7432?
18. Mention the pin numbers of IC 7408 connected to supply and gnd.
19. What do you mean by DIP, PDIP,CDIP?
20. Why IC 7404 is called HEX Inverter?
21. Which logic is followed by74 series ICs?

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22. How many gates are available in IC 74266 and name the gate?
23. In the IC it is mentioned HD74LS00P.What is the full form of “LS”.
24. What is the minimum and maximum power supply can be given to 74 series ICs?
25. How many buffer gates are available in IC 7407? Mention the i/p and o/p pin for 4 th
gate.

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AIM OF THE EXPERIMENT

Gate-level minimization: Two level and multi-level implementation of Boolean functions.
OBJECTIVES
• To learn use of multiple ICs in the breadboard to design a circuit.
• To implement a given Boolean function in two level implementation using basic gates
after simplifying it.
• To implement a given Boolean function in multi-level implementation.
• Verify the truth table of Boolean function.
• Understand the difference between two level and multi-level circuit design.

COMPONENTS REQUIRED
• IC 7408,IC 7432,IC 7404,IC 7486
• Digital Trainer Kit
• Connecting wires
• Twizer
THEORY
The complexity of the digital logic gates that implements a Boolean function is directly
related to the complexity of the algebraic expression from which the function is
implemented. The simplified expression will be assured that the simplest algebraic
expression is one with fewest possible numbers of literals in each term. This produces a
minimum number of inputs for the gate. The simplest expression is not unique. It is
sometimes possible to find two or more expression that satisfies the minimization criteria.
While two level circuit representation of circuits strictly refers to the flattened view of the
circuit in terms of SOPs (sum of products).Design of a multilevel representation in a more
generic view of the circuit in terms of arbitrarily connected SOP, POS(product of sum)
factorized form etc.
TWO LEVEL MINIMISATION
EXAMPLE- CIRCUIT DIAGRAM
𝑭𝟏 = 𝑨𝑩’ + 𝑩’𝑪 + 𝑨𝑩’𝑪
= AB’(1 + C) + B’C A
C B’(A+C)
= AB’ + B’C
= B’(A + C) B LEVEL-2

LEVEL-1 2 LEVEL MINIMISATION

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TRUTH TABLE
A B C B’ A+C B’(A+C)
0 0 0 1 0 0
0 0 1 1 1 1
0 1 0 0 0 0
0 1 1 0 1 0
1 0 0 1 1 1
1 0 1 1 1 1
1 1 0 0 1 0
1 1 1 0 1 0

THREE LEVEL MINIMISATION

EXAMPLE- CIRCUIT DIAGRAM
𝑭𝟐 = 𝑨’𝑩𝑪 + 𝑨’𝑩’𝑪 + 𝑨’𝑩𝑪’ + 𝑨𝑩𝑪
B
C
= 𝑨’𝑩𝑪 + 𝑨𝑩𝑪 + 𝑨’𝑩’𝑪 + 𝑨’𝑩𝑪’
F2
= 𝑩𝑪 (𝑨 + 𝑨’) + 𝑨’(𝑩’𝑪 + 𝑩𝑪’ A

= 𝑩𝑪 + 𝑨’(𝑩(+)𝑪)
B
C
LEVEL-1 LEVEL-2 LEVEL-3

3 LEVEL MINIMISATION

TRUTH TABLE
A B C A’ BC B(+)C (B(+)C)A’ BC+A’(B(+)C)
0 0 0 1 0 0 0 0
0 0 1 1 0 1 1 1
0 1 0 1 0 1 1 1
0 1 1 1 1 0 0 1
1 0 0 0 0 0 0 0
1 0 1 0 0 1 0 0
1 1 0 0 0 1 0 0
1 1 1 0 1 0 0 1

PRECAUTION
• Make the connections according to the IC Pin diagram.
• Make sure the connections are tight.
• The VCC and ground potential should be applied carefully at the specified pin only.
PROCEDURE
For two-level Implementation
• Insert the ICs 7432, 7404, 7408 on the breadboard horizontally.

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• Pin no. 14 and pin no.7 of all ICs should be connected to +5v dc and ground of
breadboard respectively (you can short pin no. 14 of all ICs and pin no. 7 of all ICs
individually. Then you can connect +5v dc to any IC pin no 14 through single wire.
Similarly, you can connect ground to any IC pin no 7 through single wire)
• Connect three wires from input switches of breadboard named as A,B,C.
• A &C inputs will be connected to pin no 1 and 2 of 7432 (OR gate) IC.
• B inputs will be connected to pin no 1 of 7404 (NOT gate) IC.
• Pin no 3 of 7432 IC will be connected to pin no 1 of 7408 (AND gate) IC.
• Pin no 2 of 7404 IC will be connected to pin no 2 of 7408 (AND gate) IC.
• Pin no 3 of 7408 IC will be connected to LED output of breadboard which is the
required output of the circuit.
• After verification of the connection switch on the trainer kit and power supply.
• Apply input to the circuit according to the truth table (by ON OFF mode).
• Observe the output on 8-bit LED display.
• Repeat steps for different input as per truth table and observe the output.
For multi-level Implementation
• Insert the ICs 7486, 7404, 7408 on the breadboard horizontally.
• Pin no. 14 and pin no.7 of all ICs should be connected to +5v dc and ground of
breadboard respectively (you can short pin no. 14 of all ICs and pin no. 7 of all ICs
individually. Then you can connect +5v dc to any IC pin no 14 through single wire.
Similarly, you can connect ground to any IC pin no 7 through single wire).
• Connect three wires from input switches of breadboard named as A,B,C.
[Note: Before circuit connections better number the IC pins of all ICs.
• For e.g. :IC 7486-1st gate is pin 1,2,3
IC 7404-1st gate is pin no 1,2
IC 7408-1st gate is pin no 1,2,3
2nd gate is pin no 4,5,6
3rd gate is pin no 9,10,8
• Short pin no.1 of 7486 IC to pin no 1 of 7408 IC.
• Short pin no.2 of 7486 IC to pin no 2 of 7408 IC.
• Input A will be connected to pin no.1 of 7404 IC.
• B & C inputs will be connected according to the circuit diagram.
• Short pin no.3 of 7486 IC to pin no 4 of 7408 IC.

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• Short pin no.2 of 7404 IC to pin no 5 of 7408 IC.

• Short pin no.6 of 7408 IC to pin no 9 of same IC.
• Short pin no.3 of 7408 Ic to pin no 1 of same IC.
• Pin no 8 will be connected to output LED which is the required output.
• After verification of the connection switch on the trainer kit and power supply.
• Apply input to the circuit according to the truth table (by ON OFF mode).
• Observe the output on 8-bit LED display.
• Repeat steps for different input as per truth table and observe the output.
RESULT ANALYSIS
• Observe the truth table after circuit connection is completed.
CONCLUSION
• With the help of truth table, we observed that simplified function and the original
Boolean functions are same.
• Boolean function can be simplified using Boolean algebra postulates or using K-map
up to two level or three level so that it is easier for implementation.
• Hence to reduce the cost as well as the path delay time we need to simplify the function.
QUESTIONNAIRE
1. What do you mean by two level logic circuit?
2. The two-level logic can be classified into how many forms.
3. How many possible ways of realizing two level logic?
4. What are the two levels for implementation of logic program?
5. Which logic gate is helpful to implement a function in the product of sums form by
replacing all AND & OR gates?
6. What do you mean by degenerative form?
7. What do you mean by non-degenerative form?
8. Simplify the following Boolean function into minimum number of literals using
Boolean algebra and implement using two level logic. F=AB+A(B+C)+B(B+C)
9. What do you mean by standard form of Boolean functions? Give example
10. What do you mean by Canonical form of Boolean functions? Give example
11. Which logic gates are called basic gates?
12. F=A+BC. To design the circuit of the given Boolean function how many ICs are
required and name them?
13. Give the example of a Boolean function which can be implemented in two level
logic and three level logic.
14. What is logic high & logic low?
15. Implement the function in NAND-NAND.

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AIM OF THE EXPERIMENT

Combinational Circuits: Design, assemble and test adders and subtractors (Half- adder, Full
adder, Half-Subtractor, Full-Subtractor).

OBJECTIVE
• To form, analyse and design the truth table for Half adder, Full Adder, Half Subtractor and
Full Subtractor.
• From the truth table the output may be expressed as function of input variable in SOP/POS
form and simplified if required.
• The same may be implemented like Boolean function implementation.

COMPONENTS REQUIRED
• IC 7408, IC 7432, IC 7404, IC 7486
• Digital Trainer Kit
• Connecting wires
• Twizer

APPLICATIONS
Combinational circuits are logic circuits whose outputs respond immediately to the inputs
as there is no memory.

THEORY
Combinational Logic Circuits are memory less digital logic circuits whose output at any
instant in time depends only on the combination of its inputs present at that instant of time.
A hierarchical structure of a combinational logic circuit is shown in Fig. 3.1.
An adder is a digital logic circuit in electronics that implements addition of numbers. In many
computers and other types of processors, adders are used to calculate addresses, similar
operations and table indices in the ALU and also in other parts of the processors. Adders are
classified into two types: Half Adder and Full Adder.
The Binary Subtractor is another type of combinational arithmetic circuit that produces an
output which is the subtraction of two binary numbers7. Subtractors are classified into two
types: Half Subtractor and Full-Subtractor.

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[Figure 3.1: - Hierarchical Structure of Combinational Logic Circuit]

HALF ADDER (ADDING 2 BITS)
• A combinational logic circuit that performs the addition of two data bits is called a
half-adder.
• It has two inputs: A and B, which add two input digits and generate a carry and sum as
outputs.
• Addition will result in two output bits; one of which is the sum bit, S, and the other is
the carry bit, C.
• The Boolean functions describing the half-adder are:
𝑆 =𝐴⊕𝐵
𝐶 = 𝐴. 𝐵
TRUTH TABLE

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CIRCUIT DIAGRAM

[Figure 3.2: - Circuit Diagram of Half-Adder]

PROCEDURE
• Fix three ICs 7486 (XOR) and 7408 (AND) on the breadboard.
• Make proper connection of + Vcc and ground to all ICs.
• Apply input to the circuit from input switches of breadboard trainer kit as A and B as
shown in the diagram.
• Pin no. 1 of IC 7486 will be connected to pin no. 1 of IC 7408.
• Pin no. 2 of IC 7486 will be connected to Pin no. 2 of 7408.
• Pin no. 3 of IC 7486 will be connected to the output LED, which is the Sum (S).
• Pin no. 3 of IC 7408 will be connected to another output LED which is the Carry (C).
• Now switch on the breadboard trainer kit.
• Observe the output on 8-bit LED.
• Repeat steps for different inputs as per truth table.
FULL ADDER (Adding 2-Bits Along with Previous Carry)
• The half-adder does not take the carry bit from its previous stage into account.
• This carry bit from its previous stage is called carry-in bit.
• A combinational logic circuit that adds two data bits, A and B, and a carry-in bit, Cin ,
is called a full-adder.
• The two half adders put together gives a full adder.
• Addition will result in two output bits; one of which is the sum bit (S), and the other
is the carry bit (Cout ).
• In full adder sum output will be taken from X-OR Gate, carry output will be taken
from OR Gate.
• The Boolean functions describing the full-adder are:
𝑆 = 𝐴 ⊕ 𝐵 ⊕ 𝐶𝑖𝑛
𝐶𝑜𝑢𝑡 = ((𝐴 ⊕ 𝐵). 𝐶𝑖𝑛 ) + (𝐴. 𝐵)

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TRUTH TABLE

CIRCUIT DIAGRAM OF FULL-ADDER

[Figure 3.3:- Circuit Diagram of Full-Adder]

𝑺 = 𝑨 ⊕ 𝑩 ⊕ 𝑪𝒊𝒏
𝑪𝒐𝒖𝒕 = ((𝑨 ⊕ 𝑩). 𝑪𝒊𝒏 ) + (𝑨. 𝑩)

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PROCEDURE
• Fix three ICs 7486 (XOR), 7432 (OR) and 7408 (AND) on the breadboard.
• Make proper connection of + Vcc and ground to all ICs.
• Before connection on the breadboard, give number to the pins of the gates of the ICs.
• Apply input to the circuit from input switches of breadboard trainer kit as A, B and Cin
as shown in the diagram.
• The second XOR gate output will be connected to the output LED, which is the Sum (S).
• The output will be connected to another output LED which is the Carry (Cout ).
• Now switch on the breadboard trainer kit.
• Taking different combinations of inputs, observe the output on 8-bit LED (Repeat steps
for different inputs as per truth table).
HALF-SUBTRACTOR (Subtracting 2-Bits)
• Subtracting a single-bit binary value B from another A (i.e., A -B) produces a difference
bit (D) and borrow out bit (𝐵𝑜𝑢𝑡 ).
• This operation is called half subtraction and the circuit to realize it is called a half
subtractor.
• The half subtractor is constructed using X-OR and AND Gate. The difference can be
applied using X-OR Gate𝐵𝑜𝑢𝑡 can be implemented using an AND Gate and an inverter.
• The Boolean functions describing the Half-Subtractor are:
𝐷 =𝐴⊕𝐵
𝐵𝑜𝑢𝑡 = 𝐴̅ . 𝐵
TRUTH TABLE

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CIRCUIT DIAGRAM OF HALF-SUBTRACTOR

[Figure 3.4:- Circuit Diagram of Half-Subtractor]

𝐷 = 𝐴′ 𝐵 + 𝐴𝐵 ′
𝐵 = 𝐴′𝐵
PROCEDURE
• Fix three ICs 7486 (XOR), 7404 (NOT) and 7408 (AND) on the breadboard.
• Make proper connection of + 𝑉𝑐𝑐 and ground to all ICs.
• The circuit connections are same as Half Adder connections except another NOT gate
is added to the circuit.
• Apply input to the circuit from input switches of breadboard trainer kit as A and B as
shown in the diagram.
• IC 7486 will be connected to the output LED, which is the Difference (D).
• IC 7408 will be connected to another output LED which is the Borrow (B).
• Now switch on the breadboard trainer kit.
• Observe the output on 8-bit LED.
• Repeat steps for different inputs as per truth table.
FULL-SUBTRACTOR (Subtracting 2-Bits Along with Previous Borrow)
• The full subtractor is a combinational circuit which is used to perform subtraction of
three input bits: the minuend A, subtrahend B, and borrow in 𝐵𝑖𝑛 .
• The two half subtractor put together gives a full subtractor.
• The full subtractor generates two output bits: the difference (D) and borrow
out (𝐵𝑜𝑢𝑡 ).
• Bin is set when the previous digit is borrowed from A.
• Thus, Bin is also subtracted from A as well as the subtrahend B.
• The full subtractor is a combination of X-OR, AND, OR, NOT Gates.
• Boolean functions describing the Full-Subtractor are:
𝐷 = 𝐴 ⊕ 𝐵 ⊕ 𝐶𝑖𝑛
𝐵𝑜𝑢𝑡 ̅̅̅̅̅̅̅̅̅̅̅
= ((𝐴 ⊕ 𝐵). 𝐵𝑖𝑛 ) + (𝐴̅. 𝐵)

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TRUTH TABLE OF FULL-SUBTRACTOR

CIRCUIT DIAGRAM FOR FULL SUBTRACTOR

[Figure 3.4:- Circuit Diagram of Full-Subtractor]

𝐷 = 𝐴̅𝐵̅ 𝐵𝑖𝑛 + 𝐴̅𝐵 𝐵̅𝑖𝑛 + 𝐴𝐵̅ 𝐵̅𝑖𝑛 + 𝐴𝐵𝐵𝑖𝑛
= (𝐴̅𝐵̅ + 𝐴𝐵)𝐵𝑖𝑛 + (𝐴̅𝐵 + 𝐴𝐵̅ )𝐵̅𝑖𝑛
= ̅̅̅̅̅̅̅̅̅̅̅
(𝐴 ⊕ 𝐵)𝐵𝑖𝑛 + (𝐴 ⊕ 𝐵)𝐵̅𝑖𝑛
= 𝐴 ⊕ 𝐵 ⊕ 𝐵𝑖𝑛
𝐵𝑜𝑢𝑡 = 𝐴̅𝐵 + 𝐴̅𝐵𝑖𝑛 + 𝐵𝐵𝑖𝑛
PRECAUTION
• Make the connections according to the IC Pin diagram.
• Make sure the connections are tight.
• The VCC and ground potential should be applied carefully at the specified pin only.

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PROCEDURE
• Fix four ICs 7486 (XOR), 7404 (NOT), 7432 (OR) and 7408 (AND) on the breadboard.
• Make proper connection of + Vcc and ground to all ICs.
• The circuit connections are same as Full Adder connections except two NOT gates
are added to the circuit.
• Apply input to the circuit from input switches of breadboard trainer kit as A, B and
Bin as shown in the diagram.
• IC 7486 will be connected to the output LED, which is the Difference (D).
• IC 7432 will be connected to another output LED which is the Borrow (B).
• Now switch on the breadboard trainer kit.
• Observe the output on 8bit LED.
• Repeat steps for different inputs as per truth table.

RESULT ANALYSIS
• Observe the truth table after circuit connection is completed.

CONCLUSION
• With the help of truth tables, we observed that the theoretical values and the
experimental results of the designed circuits are same. Hence, the experiment is
completed successfully.
QUESTIONNAIRE
1. If A and B are the inputs of a half adder, the sum is given by __________
2. How many AND, OR and EXOR gates are required for the configuration of full adder?
3. What are the applications of full adder circuit?
4. Half subtractor is used to perform subtraction of how many bits.
5. What is the major difference between half adder and full adder?
6. How many 7486,7408,7404,7432 Ics are required to design a full subtractor?
7. What is the major difference between half adder and half subtractor?
8. Mention the name of ICs to design a half subtractor?
9. Find the Boolean function for sum in Full adder.
10. Half adder is used to perform the addition of how many bits.

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AIM OF THE EXPERIMENT

Design, assemble and test code converters: binary code to gray code, gray code to binary
and 7 segment displays.

OBJECTIVE
• To form the truth table taking Binary inputs and derive corresponding gray code
output. (3-bits/4 bits may be taken for testing purpose). From each column gray
output may be expressed as a function of binary variable and simplified if required.
• The simplified output may be implemented and truth table may be verified.
• The above steps may be repeated taking gray code as inputs and Binary output for 3
or 4 variables. Binary output may now be expressed as function of gray code inputs
and truth table may be verified.

COMPONENTS REQUIRED
• IC 7486,IC 7447,
• 7 segment display devices
• Resister (560 Ω)
• Digital Trainer Kit
• Connecting wires
• Twizer
THEORY
CODECONVERTER
A Code converter is a combinational logic circuit whose inputs are bit patterns representing
numbers in one code and whose outputs are the corresponding representations in a
different code.
➢ Binary to Gray Code Converter
Code is a symbolic representation of discrete information. Codes are of different types. Gray
Code is one of the most important codes. It is a non-weighted code which belongs to a class
of codes called minimum change codes. In this code, while traversing from one step to
another step only one bit in the code group changes. In case of Gray Code two adjacent code
numbers differs from each other by only one bit.

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Steps for Binary to Gray Code Conversion

 The M.S.B. of the gray code will be exactly equal to the first bit of the given binary
number. Now the second bit of the code will be exclusive-or of the first and second
bit of the given binary number, i.e., if both the bits are same the result will be 0 and
if they are different the result will be 1.
 The third bit of gray code will be equal to the exclusive-or of the second and third bit
of the given binary number. Thus, the Binary to gray code conversion goes on.
 One example given below can make your idea clear on this type of conversion. Let
(01001) be the given binary number.

 Thus, the equivalent gray code is 01101

Implementing 4 Bit Binary Code to Gray Code Converter

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Truth Table of Binary Code to Gray Code Converter

Circuit Diagram of Binary Code to Gray Code Converter

[Figure 4.1: - Binary-to-Gray Code Circuit]

PROCEDURE
• Fix the IC 7486 (XOR) on the breadboard.
• Give + 𝑉𝑐𝑐 and ground to the IC.
• Connect three wires to 3 switching input of the breadboard named as 𝐵0 , 𝐵1 , 𝐵2.
• It is always better to give number the gate pins before connecting the circuit.
• Input B0 will be connected to pin no. 1 of 7486.
• Input B1 will be connected to pin no. 2 as well as pin no. 4 of 7486 IC.
• Input B2 will be connected to pin no. 5 of 7486 IC.
• Pin no. 3 of 7486 IC will be connected to output LED and i.e.,𝐺0.
• Pin no. 3 of 7486 IC will be connected to 2nd output LED and i.e.,𝐺1.
• Input B2 will be connected to 3rd output LED and i.e.,𝐺2.
• Verify the connections once again and power ON the trainer kit.
• Taking different combinations of inputs (𝐵0 , 𝐵1 , 𝐵2), observe the outputs on LEDs
(𝐺0 , 𝐺1 , 𝐺2 ).

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➢ Gray Code to Binary Code Converter

Gray code to binary conversion is again very simple and easy process. Following steps can
make your idea clear on this type of conversions.
Steps for Gray to Binary Code Conversion
• The M.S.B of the binary number will be equal to the M.S.B of the given gray code.
• Now if the second gray bit is 0 the second binary bit will be same as the previous or
the first bit. If the gray bit is 1 the second binary bit will alter. If it was 1 it will be 0
and if it was 0 it will be 1.
• This step is continued for all the bits to do Gray code to binary conversion.
• One example given below. Let the gray code be 01101. The equivalent Binary
numbers in case of gray code to binary conversion will be (01001).

Implementing Gray Code to Binary Code

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Truth Table of Gray Code to Binary Code Converter

Circuit Diagram of Gray Code to Binary Code Converter

[Figure 4.2: - Gray-to-Binary Code Circuit]

PROCEDURE
• Fix the IC 7486 (XOR) on the breadboard.
• Give + Vccand ground to the IC.
• Connect three wires to 3 switching input of the breadboard named as 𝐺0 , 𝐺1 , 𝐺2.
• It is always better to give number the gate pins before connecting the circuit.
• Connections are small modification of Binary to Gray circuit.
• Input G0, G1, G2 will be connected to pin no. 1, 4 and 5 of 7486.
• Pin no. 6 will be shorted to pin no. 2 of 7486.
• Output B0, B1, B2will be taken from pin no. 3, 6, 5 of 7486 IC respectively.
• Input B2 will be connected to pin no. 5 of 7486 IC.
• Verify the connections once again and power ON the trainer kit.
• Taking different combinations of inputs (𝐺0 , 𝐺1 , 𝐺2) from the truth table, observe the
outputs on LEDs (𝐵0 , 𝐵1 , 𝐵2).

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BCD TO 7-SEGMENT DISPLAY

A seven-segment indicator is used for displaying any one of the decimal digits 0 through 9.
Usually, the decimal digit is available in BCD. A BCD to Seven segment decoder accepts a
decimal digit BCD and generates the corresponding seven-segment code.

[Figure 4.3:- IC Configurations of 7-Segment Display]

[Figure 4.4:- Circuit Diagram of CA Type 7-Segment Display]

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PROCEDURE FOR CODE CONVERTER

• Fix the IC 7447 (Driver IC) horizontally and the common anode type display vertically
on the breadboard as shown in the diagram.
• Give + Vcc(+5V D.C.) to pin no. 16 and ground is connected to pin no. 8 of the IC 7447.
• Connect four inputs A, B, C, D to pin no. 7, 1, 2 and 6 of IC 7337 respectively.
• Connect other pins of 447 IC to 7-segment display according to the diagram given.
• One 560 Ω resistor will be connected to pin no. of 7-segment display and the other
end of resistor will be connected to +5v D.C. supply as shown in figure.
• Verify the connections once again and power ON the trainer kit.
• Give the inputs through A, B, C, D and observe the output on 7-segment display
device.
➢ In our laboratory, we are using common Anode type display device. Similarly, you can
use common Cathode type display.
VERIFICATION TABLE

PRECAUTION
• Make the connections according to the IC Pin diagram.
• Make sure the connections are tight.
• The VCC and ground potential should be applied carefully at the specified pin only.
PROCEDURE FOR CODE CONVERTER
• Make the connections according to the IC pin diagram.
• The connections should be tight.
• The Vcc and GND should be applied carefully at the specified pin only.
• Apply input to the circuit according to the circuit diagram.

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• In case of binary to gray conversion, the inputs are given at respective pins and
outputs are taken for all the combinations and same for gray to binary conversion.
• Switch on the trainer kit.
• Observe the output AND VERIFY THR TRUTH TABLE
• Repeat steps for different input as per truth table.
PROCEDURE FOR CODE CONVERTER
• Make the connections according to the IC pin diagram.
• The connections should be tight.
• In 7-segment display, connect four switches to the four inputs of your decoder
inputs (D, C, B, and A) respectively& check the display for corresponding output.
• Connect the positive terminal of supply to pin 16 and pin 8 is to be grounded.
• Give input at corresponding pins & connect output pins to an output LED.
• Switch on the trainer kit.
• Note the values of output for different combination of inputs & verify the logic table
for each circuit.
• Observe the output and verify the truth table
• Repeat steps for different input as per truth table.
RESULT ANALYSIS
• Observe the output and verify the truth table

CONCLUSION
• With the help of truth tables, we observed that the theoretical values and the
experimental results of the designed circuits are same. Hence, the experiment is
completed successfully.
QUESTIONNAIRE
1. What is magnitude comparator?
2. What is IC?
3. What is most significant bit?
4. What is seven segment displays?
5. Covert gray to binary 01101.
6. What is equality?
7. What is inequality?
8. What is D’morgans theorem?

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AIM OF THE EXPERIMENT

Design, implement and test a given design example with (i) NAND Gates only (ii)NOR Gates
only and (iii) using minimum number of Gates.

OBJECTIVE
• Use of Universal Gates (NAND & NOR) to implement given Boolean function and
justify through truth tables.
• Simplify the Boolean function using algebraic laws or using KMAP.
• Design the simplified Boolean function with minimum number of gates (NAND &
NOR) and verify the truth table.
COMPONENTS REQUIRED
• IC 7400,IC7402
• Digital Trainer Kit
• Connecting wires
• Twizer
THEORY
NAND and NOR gate are said to be universal gate because any digital system can be
implemented with these two gates. Digital circuits are frequently constructed with NAND
and NOR gates are easier to design and used in all digital circuits. Designing a circuit with
minimum number of gates is more advantageous for digital systems as it requires minimum
space and a smaller number of gates, so less complex. We can use Boolean algebraic rules
and laws or KMAP to simplify a given Boolean function.
Boolean function
𝐹 = 𝐴𝐵’𝐶 + 𝐴’𝐵𝐶’ + 𝐷

(i) Using NAND Gates only

𝐹 = 𝐴𝐵’𝐶 + 𝐴’𝐵𝐶’ + 𝐷
= (𝐴𝐵’𝐶 + 𝐴’𝐵𝐶’ + 𝐷)’’
= ((𝐴𝐵’𝐶 )’. (𝐴’𝐵𝐶’) . 𝐷’)’

[Figure 5.1: - Circuit Diagram

Using NAND Gates Only]

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(ii) Using NOR Gates only

𝐹 = 𝐴𝐵’𝐶 + 𝐴’𝐵𝐶’ + 𝐷
= (𝐴𝐵’𝐶 + 𝐴’𝐵𝐶’ + 𝐷)’’
= ((𝐴𝐵’𝐶 )’. (𝐴’𝐵𝐶’) . 𝐷’)’
= ((𝐴’ + 𝐵 + 𝐶’)’ + (𝐴 + 𝐵’ + 𝐶)’ + 𝐷)’’

[Figure 5.2: - Circuit Diagram

Using NAND Gates Only]

(iii) Using minimum number of NAND Gates only

𝐹1 = 𝐴𝐵 ′ 𝐶 + 𝐴𝐵 ′ 𝐶 ′ + 𝐷
= 𝐴𝐵 ′ (𝐶 + 𝐶 ′ ) + 𝐷
= 𝐴𝐵 ′ + 𝐷

[Figure 5.3: - Circuit Diagram

Using NAND Gates Only]

TRUTH TABLE OF BOOLEAN FUNCTION ‘F’

A B C D F
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1

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TRUTH TABLE OF BOOLEAN FUNCTION ‘F1’

A B C D F
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1

PRECAUTION
• Make the connections according to the IC Pin diagram.
• Make sure the connections are tight.
• The VCC and ground potential should be applied carefully at the specified pin only.

PROCEDURE
FOR NAND GATE ONLY:
The function 𝐹 = 𝐴𝐵′𝐶 + 𝐴′𝐵𝐶′ + 𝐷 designed with NAND gate only and it requires seven
numbers of NAND gate out of which 3 are 3 input NAND and 4 are 2 input NAND gate as
shown in the diagram.

Since one 7400(2 input NAND gate) IC contains 4 no. of NAND gate and 7410 (3 input NAND
gate) IC contains 3 no. of NAND gate. In this experiment we require one 7400 (NAND) IC and
one 7410 (3 input NAND gate).

Before connecting the circuits, your number the IC pins for better understanding.

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• Fix one 7400 (2 input NAND) ICs and one 7410 (3I/P NAND) IC on the Breadboard.
• Make the connection for +VCC and ground to both the ICs.
• You should be clear about the input pins and the output pins of 3 input NAND (7410)
IC.
• Connect 4nos of connecting wires to input switch of Breadboard and all will be
connected to input of NAND gates such as A,B,C,D as shown in the diagram.
• Make internal connections having seen the diagram carefully.
• 'F' will be the final output which will be taken from third 3 input NAND gate output.
• 'F' will be connecting to the output LED of Breadboard.
• Verify the connections once again and then power ON the trainer kit.
• Give the inputs to A,B,C,D and at 'F' verify the Truth table.

FOR NOR GATE ONLY:

The function 𝐹 = 𝐴𝐵′𝐶 + 𝐴′𝐵𝐶′ + 𝐷 neither designed with NOR gate only and it requires
seven number ofNOR gate out of which 3 are 3 inputNOR (7427) gate and 4 are 2 input NOR
(7402) gate asshown in the diagram.

You should be clear about the output pins and input pins of IC 7402 and 7427.
In this Experiment we require one 7402 (NOR) IC and one 7427(3 input NOR) IC.

• Fix two ICs such as 7402 and 7427 on the Breadboard.

• Make the connection for +VCC and ground to both ICS.
• Just like using NAND gate only, here we require 4 inputs A,B,C,D and the output is 'F'.
• You should carefully connect the internal connections to design the circuit as shown
in the diagram.
• 'F' will be connecting to the output LED of the Breadboard.
• Verify the connections once again and then power ON the Trainer kit.
• Give the inputs to A, B, C, D and at F verify the output according to the Truth table.

RESULT ANALYSIS
Verify the truth table of Boolean functions F & F1 for both the circuits (using NAND & NOR gate).

CONCLUSION

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• With the help of truth table, we observed that the circuit designed using universal
gates for Boolean function F is same.
• After simplification of Boolean function F1 it is designed using NAND gate and truth
table is verified.
• It is understood that any Boolean function can be designed using NAND & NOR gates
hence called universal gates.
• To reduce the cost as well as the path delay time we need to simplify the function.

QUESTIONNAIRE
1. Why NAND and nor GATES ARE CALLED UNIVERSAL GATES?
2. Draw the truth table and logic symbol of 2input NAND gate.
3. Draw the truth table of 2input NAND gate.
4. Implement the given Boolean function using NAND gates only. F=AB+C
5. Implement the given Boolean function neither using nor gates only. F=AB+C
6. Implement the given Boolean function using nor gates only F=A’B+C
7. Which logic gates are called the basic gates?
8. Implement the given Boolean function using basic gates and NAND gates. F=AB+CD.
9. Simplify the Boolean function using KMAP and implement using universal gates.𝐹 =
∑ 𝑚 (0, 1, 2, 3, 4, 5, 6, 7 ).
10. Simplify the Boolean function using KMAP and implement using universal gates. 𝐹 =
∏(0, 4) .

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AIM OF THE EXPERIMENT

Study of Multiplexer, De-multiplexer. Design with multiplexers and de-multiplexer.

OBJECTIVES
• Identify the 74 Series Integrated circuits (ICs) belong to logic gate and MUX and
their pin configurations.
• Test logic behavior (truth tables) of 3 input AND gate.
• Design of 4:1 MUX and 1:4 DEMUX using basic gates(NOT,AND,OR) and justify
through truth tables.
• Implement Full Adder using 4:1 MUX (IC 74153) and verify the truth table of full
adder.
COMPONENTS REQUIRED
• IC 7411,IC 74153,IC7404,IC7432
• Trainer Kit
• Connecting wires
• Twizer
APPLICATIONS
• Multiplexers are also used in communications; the telephone network is an example
of a very large virtual Mux built from many smaller discrete ones.
• Instead of having a direct connection from every telephone to every telephone -
which would be physically impossible - the network "MUXes" individual telephones
onto one of a small number of wires as calls are placed.
• At the receiving end, a de-multiplexer, or "DEMUX", chooses the correct destination
from the many possible destinations by applying the same principle in reverse.

THEORY
MULTIPLEXER
• Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’
selection lines and single output line. One of these data inputs will be connected to
the output based on the values of selection lines. Multiplexer is also called as Mux
or MPX.

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• Multiplexers are also known as “Data n selector, parallel to serial convertor, many
to one circuit, universal logic circuit”. Multiplexers are mainly used to increase
amount of the data that can be sent over the network within certain amount of time
and bandwidth.

4:1 MULTIPLEXER
4:1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines S1 & s0 and one output Y.

[Figure 6.1:- Block Diagram of 4:1 Mux]

[Figure 6.2:- Circuit Diagram of 4:1 Mux]

[Figure 6.3:- Pin Configuration of 7411 IC]

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PROCEDURE
• Fix the ICs on the Breadboard such as 7404 (NOT gate), 7411 (3 Input AND) and 7432
(OR Gate) IC.
• Insert 2 no. of 7411 ICs because within one 7411 IC. It contains only 3 no. of 3 input
AND gate.
• Connect 6 no of wires to switching input of Breadboard out of which 2 input will be
selection lines S0and S1.Rest 4 inputs are input to the circuits such as I0, I1, I2 and I3.
• You should be clear about the output pins and input pins of IC 7411,7432 and 7404
• Design the circuit according to the diagram given.
• Final output will be 'Y' which is the MUX output.
• 'Y' will be connected to output LED of Breadboard.
• Verify the connections Once again and then Power ON the Trainer Kit.
• Depending on the input select lines S0 and S1 States, at output 'Y' which data will be
transferred from input lines to output it will display.
• Finally verify the Truth Table.

VERIFICATION TABLE
Selection Lines Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

DEMULTIPLEXER
De-Multiplexer is a combinational circuit that performs the reverse operation of
Multiplexer. Demultiplexer is in fact a circuit which can distribute or deliver multiple
outputs from a single input. It can often refer as data distributor or DEMUX. It can perform
as single input many output switches.
It has single input, ‘n’ selection lines and maximum of 2n outputs. The input will be
connected to one of these outputs based on the values of selection lines.
The 1 to 4 Demultiplexer consists of one input, four outputs, and two control lines to make
selections.

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[Figure 6.4:- Block Diagram of1:4 De-Mux]

[Figure 6.5: - Circuit Diagram of 1:4 De-Mux]

PROCEDURE
• Fix one no. of 7404 (NOT gate) IC and two no. of 7411 (3 input AND gate) IC on the
Breadboard Trainer Kit.
• Connect 3 no of wires to switching input of Breadboard out of which 2 input will be
select lines S1 and S2. The rest input is the data input to the circuit is 'I'.
• Design the circuit according to the diagram given.
• Since it is 1:4 DEMUX, it has 4 outputs i.e., Y1, Y2, Y3 and Y4.
• These 4 outputs will be connected to 4 no. of LEDs output of Breadboard.
• Verify the connections once again and then power ON the Trainer Kit.
• Depending on the input select lines S1 and S2 status; 'I' data will be transferred to
the Particular output out of 4 outputs (Y1, Y2, Y3, and Y4).
• Finally verify the Truth Table.

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VERIFICATION TABLE OF

Selection Inputs Outputs

𝑺𝟏 𝑺𝟎 𝒀𝟑 𝒀𝟐 𝒀𝟏 𝒀𝟎
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

IMPLEMENTATION OF FULL ADDER USING 4:1 MUX

A full adder can be implemented using two 4:1 MUX, IC74153.

[Figure 6.6:- Pin Configuration of 74153 IC]

Implementing Full-Adder
• A full adder is a combinational circuit that forms the arithmetic sum of three bits. It
consists of three inputs (two significant bits to be added and a carry from the
previous lower significant position) and two outputs (sum and carry).

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[Figure 6.3: - Logic Diagram of Full Adder Using7411 IC]

Truth Table of Full Adder in terms of select lines and data I/P

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IMPLEMENTATION OF FULL ADDER USING 4:1 MUX

• Insert two ICs such as 74153 (This IC contains 2 numbers of 4:1 MUX) and 7404
(NOT gate) IC.
[74153 IC is 16 pin DIP type IC. You should Very clear about the pins of the IC before
design the circuit Full adder]
• Make the connections for +VCC (+5 V dc) to pin no 16 and ground to pin no 8 of
74153.Similarly the connections for +VCC (+5 V dc) to pin no 14 and ground to pin no 7
of 7404.
• To implement the Full adder, you require 3 numbers of input and 2 no of outputs.
Here the inputs are 𝐴, 𝐵 𝑎𝑛𝑑 𝐶𝑖𝑛 and the outputs are SUM and CARRY Shown in the
diagram.
• Three Inputs A (pin no 14), B (pin no 2) and 𝐶𝑖𝑛 (pin no 3, 6, 11, 12 will be shorted)
will be connected to input switches of Breadboard and output SUM and CARRY will
be connected to output LEDs of Breadboard.
• Carefully make the connections for all the pins shown in the diagram including 7404 IC.
• Pin no. 1 and 15 will be enable pins. Pin no. 7 is SUM and 9 is CARRY.
• Verify the connections and power ON the Breadboard.
• Giving the different input values to , 𝐵 𝑎𝑛𝑑 𝐶𝑖𝑛 , Study the output at SUM and CARRY
output for Full adder.
PRECAUTION
• Make the connections according to the IC Pin diagram.
• Make sure the connections are tight.
• The VCC and ground potential should be applied carefully at the specified pin only.
RESULT ANALYSIS

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• Justify the verification table of MUX and DEMUX.

• Also verify the truth table of full adder.
CONCLUSION
• Identified the 74 Series Integrated circuits (ICs) belong to logic gate and MUX and their
pin configurations. Also, logic behavior (truth tables) of 3 input AND gate is tested.
• Using basic gates (NOT, AND, OR)4:1 MUX and 1:4 DEMUX is designed and justified
through truth tables.
• Full Adder is implemented using 4:1 MUX (IC 74153) and verified the truth table of
full adder.
QUESTIONAIRES
1. Explain the principle of Multiplexer?
2. Draw the circuit diagram of 4:1 Multiplexer.
3. What are the advantages of Multiplexer?
4. Make the Truth-table of 4:1 Multiplexer?
5. Explain about De-multiplexer?
6. Draw the circuit diagram of 1: 4 De-multiplexers.
7. What is the application of De-multiplexer?
8. What is the difference between Multiplexer and De-multiplexer?
9. What is another name of multiplexer?
10. How many selection lines are required to design a 16:1 multiplexer?

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AIM OF THE EXPERIMENT

To design binary to octal Decoder and Implementation of Boolean function using decoder.

OBJECTIVES
• To learn about the functionality of Decoder.
• To give Binary input and Obtain Octal output.
• To express and implement higher order Decoder using lower order Decoders.

HARDWARE REQUIRED
• IC 74hc238,
• Digital Trainer Kit
• Connecting wires
• Twizer

THEORY
A Decoder is a combinational circuit that converts binary information from n input lines to
a maximum of 2n unique output lines. (A decoder is a device which does the reverse
operation of an encoder, undoing the encoding so that the original information can be
retrieved. The same method used to encode is usually just reversed in order to decode). In
digital electronics, a decoder can take the form of a multiple- input, multiple-output logic
circuit that converts coded inputs into coded outputs, where the input and output codes are
different. e.g. n-to-2 n , binary-coded decimal decoders. Enable inputs must be on for the
decoder to function, otherwise its outputs assume a single "disabled" output code word. In
case of decoding all combinations of three bits eight (23 =8) decoding gates are required.
This type of decoder is called 3-8 decoder because 3 inputs and 8 outputs. For any input
combination decoder outputs are 1 i.e. at any time one of the output must be true and rest
are false. If inverted output is considered then one output must be false for any valid input
combination when rest is true. The truth table for binary to octal converter (which is 3 to 8
Decoder. It implies there are 3 input lines and 8 output lines).

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CIRCUIT DIAGRAM OF 3 x 8 LINE DECODER

[Figure 7.1: - Circuit Diagram of 3-to-8 Line Decoder]

PROCEDURE
• Fix the IC 74238(3:8 binary to octal decoder IC) on the Breadboard.
• Give +VCC and Ground to pin no 16 and pin no 8 respectively.
• Connect 4 input wires to the input switches of the breadboard out of which one is
Enable input (pin no 6) and three are address inputs 𝐴0 , 𝐴1 , 𝐴2 (Pin no 1,2,3).
• Pin no. 4 and 5 are active low enable inputs.
• Connect pin no. 7,9,10,11,12,13,14,15 to output LED of the breadboard named as
𝑌0 , 𝑌1 , 𝑌2 , 𝑌3 , 𝑌4 , 𝑌5 , 𝑌6 , 𝑌7 .
• Verify the connections and then power ON the broadband Trainer.
• Give Inputs to Enable and address inputs and observe the output LEDS.
• Finally verify The Truth Table.
TRUTH TABLE
E A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 X X X 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 0 1 0 0 0 0 0 0
1 0 1 0 0 0 1 0 0 0 0 0
1 0 1 1 0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0 1 0 0 0
1 1 0 1 0 0 0 0 0 1 0 0
1 1 1 0 0 0 0 0 0 0 1 0
1 1 1 1 0 0 0 0 0 0 0 1

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VERIFICATION TABLE
INPUTS OUTPUTS
̅𝟏
𝑬 ̅𝟐
𝑬 𝑬𝟑 𝑨𝟎 𝑨𝟏 𝑨𝟐 𝒀𝟎 𝒀𝟏 𝒀𝟐 𝒀𝟑 𝒀𝟒 𝒀𝟓 𝒀𝟔 𝒀𝟕
H X X X X X L L L L L L L L
X H X X X X L L L L L L L L
X X L X X X L L L L L L L L
L L H L L L H L L L L L L L
L L H H L L L H L L L L L L
L L H L H L L L H L L L L L
L L H H H L L L L H L L L L
L L H L L H L L L L H L L L
L L H H L H L L L L L H L L
L L H L H H L L L L L L H L
L L H H H H L L L L L L L H
NOTE: -H – High Voltage Level, L – Low Voltage level, X – Don’t care
IMPLEMENTATION OF FULL ADDER USING 3:8 DECODER

SUM = ∑m (1, 2, 4, 7)
Cout = ∑m( 3, 5, 6, 7)

[Figure 7.2: - Circuit Diagram of Full Adder Using 3:8 Line Decoder]

[Figure 7.3:- Pin Configuration of IC 74238]

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FUNCTIONAL DESCRIPTION OF IC 74HC238

• There are 3 address pins (A0, A1, and A2). These address pins control which output
pins turn on. So, again, with 3 pins, we can control 8 outputs. This is because 2:3=8.
• Our output devices will be LEDs. Since there are 8 outputs on the 74HC238 chip, we
will attach 8 LEDs to the chip.
• The 3 pins can be in either 1 of 2 states. They can either be LOW (tied to GND) or
HIGH (tied to VCC).
• So, if we have an address pin connected to ground, it has a value of 0. If an address
pin is connected to +5V, it has a value of 1.
• So, if all address pins are connected to ground, this gives a value of 000. This equates
to all the outputs (LEDs) being off.
• If the address pins have a value of 001, this equates to the first LED being on.
• If the address pins have a value of 010, this equates to the first 2 LEDs being on.
• If the address pins have a value of 011, this equates to the first 3 LEDS being on.
• If the address pins have a value of 100, this equates to the first 4 LEDs being on.
• If the address pins have a value of 101, this equates to the first 5 LEDs being on.
• If the address pins have a value of 110, this equates to the first 6 LEDs being on.
• If the address pins have a value of 111, this equates to all 7 LEDs being on. And this
how the address pins can affect all 8 outputs.
• It follows a binary-to-decimal code.
• The 74HC238 can be powered with +5V. Therefore, we can connect VCC to We connect
VSS to ground. This completes the powering that's necessary for the 74HC238.
• The enable pins are the pins that allow for outputs to be able to turn on when E1 and
E2 are LOW and E3 is HIGH. Without this combination, none of the output pins can
turn on. In other words, every output will be LOW unless E1 and E2 are LOW and E3 is
HIGH.
• The rest of the pins, Y0 to Y7, are the output pins. To these pins, we connect an LED
along with a series-limiting resistor to limit excess current to the LEDs, so they don't
get blown out.
PRECAUTION
• Make the connections according to the IC Pin diagram.
• Make sure the connections are tight.
• The VCC and ground potential should be applied carefully at the specified pin only.

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PROCEDURE
• Fix the IC 74238 on the breadboard.
• Fix the IC 74HC4072 (4 Dual input OR gate) IC on breadboard. [In case of non-
availability of 74HC4072, you can use 7427 and 7432 ICs].
• Give inputs to the IC 74238 named as A, B, and Cin.
• Connect the output pins of 74238 to Dual 4 inputs OR IC.
• First OR output, will be connected to one output LED which is SUM of Full Adder.
• Second OR output will be connected to another output LED which is carry, named as
Cout.
• Verify the connections once again and then power ON the broadband Trainer.
• Giving the inputs to decoder observe the output at LEDs and verify the Full adder
Truth table.

CONCLUSION
The output shown in the verification table was verified from the truth table.

QUESTIONNAIRE
1. How many 3-to-8-line decoders with an enable input are needed to construct a 6-to-64-
line decoder without using any other logic gates?
2. A 4-digit number of the form aabb is a perfect square. What is the value of a – b?
3. Design a 2 to 4 decoder with inverted output.
4. A decoder is a combinational/Sequential Circuit? Justify your answer.
5. How many inputs and outputs will a decimal-to-BCD encoder have?
6. How is an encoder different from a decoder?
7. If we record music in any recorder it is called as___________.
(Decoding/demultiplexing/multiplexing/Encoding)
8. Can a Decoder be used as a demultiplexer? If so how.
9. For an 8-bit Encoder how many valid input combinations are there?
10. If two inputs are active on a priority encoder simultaneously, what will be the output?

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AIM OF THE EXPERIMENT

Assemble, test and investigate operation of SR, D, J-K & T flip-flops.

OBJECTIVES
Design and verification SR, D, J-K,T flip flops.

COMPONENTS REQUIRED
1. IC7400,IC 7410, IC7404, 2. Digital Trainer Kit 3. Connecting wires 4. Twizer
APPLICATIONS
 Flip-flops are the most common and basic memory devices used for storage of one
bit information in sequential circuits.
 It is a basic building block for counters, registers, and other sequential control logic.
 A flip-flop can stay in one of two logical states. To change its state, we need a new
input signal. This makes the flip-flop a 1-bit memory device.
 A flip-flop circuit can maintain a binary state indefinitely until directed by an input
signal to switch state.
 The major differences among various types of flip-flops are in the number of inputs
they possess and in the manner in which the inputs affect the binary state.
 There are three basic types of flip-flops:
➢ Memory flip-flops have special inputs to be set or reset. The flip-flop preserves its
state as long as there is no new input signal.
➢ Delay flip-flops output the state their input had one cycle ago. If the input signal
changes at step ‘n’ the output changes at step ‘n+1’.
➢ Toggle flip-flop or “T” flip-flop changes its output on each clock cycle if the input
given to T is high (or 1). If the input of T is low (or 0) the output does not change,
meaning it is preserved.

[Figure 8.1: - Block Diagram of a

Sequential Logic Circuit] [Figure 8.2: - Block Diagram of a Flip-Flop]

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➢ Reset-Set (RS) Flip-flop

 A simple memory flip-flop is the RS FF. This device has two inputs - S for setting and
R for resetting the flip-flop (hence its name).
 The RS flip-flop preserves its states as long as the inputs S and Rare 0. If it receives a
set signal, it turns to 1, regardless of its former state. A reset signal enforces a 0 state.
This behavior is illustrated by the truth table below (Qn is the preceding state of Qn+1).

[Figure 8.3: - Symbol of a SR Flip-Flop] [Figure 8.4: - Circuit Diagram of a SR Flip-Flop]

PROCEDURE
• Fix the IC 7400 (Quad, 2 I/P NAND) on the bread board.
• Give +Vcc(+5V dc) to pin no. 14 and ground to pin no. 7 of the IC.
• Connect pin no. 1 (S) and 5 (R) of the IC from the input switch through wire
separately and pin no. 2 & 4 will be connected to the CLK input.
• Pin no. 3 will be connected to pin no. 9 and pin no. 6 will be connected to pin no. 13.
• Pin no. 8 will be get shorted with pin no. 12 and pin no. 10 will be get shorted with
pin no. 11.
• Pin no. 8 will be connected to o/p LED of the bread board which will be referred as
‘Q’ (output).
• Recheck the connection and then switch on the power supply of the bread board.
• Give the CLK i/p high (ON) condition.
• Give the input to the ‘S’ and ‘R’ through input switches of bread board and observe
the output through two outputs 𝑄 𝑎𝑛𝑑 𝑄̅ of the SR flip-flop.

TRUTH TABLE OF SR FLIP-FLOP

CLK S R Q CONDITION
H 0 0 X No Change
H 0 1 0 Reset
H 1 0 1 Set
H 1 1 ? Invalid
Delay (D) Flip-flop

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 Purpose of a D FF is to temporary store (or delay) a single bit. A signal of 0 or 1 present

at the input D is transferred to the output Q whenever the clock CLK is set to 1.

Figure 8.5: - Symbol: D Flip-flop Figure 8.6: - Circuit Diagram of D Flip-flop

PROCEDURE
• The connection is almost same as the procedure SR flip-flop with a few deviations.
• Fix the IC 7400 (Quad, 2 I/P NAND) and 7404 (NOT) on the bread board.
• Give +Vcc(+5V dc) to pin no. 14 and ground to pin no. 7 of the IC.
• Assuming the connection same as S and R inputs. Connect the input (D) from the
input switch to the pin no. 1 (S) of 7400 IC & 7404 IC whereas the pin no. 2 of 7404
IC will be connected to pin no. 5 (R) of the 7400 IC.
• The pin no. 2 & 4 of 7400 IC will be connected to the CLK input.
• (For 7400 IC) Pin no. 3 will be connected to pin no. 9 and pin no. 6 will be connected
to pin no. 13.
• (For 7400 IC) Pin no. 8 will be get shorted with pin no. 12 and pin no. 10 will be get
shorted with pin no. 11.
• (For 7400 IC) Pin no. 8 will be connected to o/p LED of the bread board which will
be referred as ‘Q’ (output).
• Recheck the connection and then switch on the power supply of the bread board.
• Give the CLK input high (ON) condition.
• Give the input to the ‘D’ through input switches of the bread board and observe the
output through two outputs 𝑄 𝑎𝑛𝑑 𝑄̅ of the D flip-flop.

TRUTH TABLE OF D FLIP-FLOP

CLK D Q CONDITION
H 0 0 Reset
H 1 1 Set

JUMP KILL (JK) FLIP-FLOP

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 The RS FF presented in the previous section has a serious disadvantage. For an RS FF

one input combination is not allowed.
 The JK FF is a modified RS FF (J corresponds to the set and K to the reset input), which
inverts its state when the input J = 1 and K = 1 occurs. Since it has no forbidden input
combinations, the JK FF can be easily used to generate other types of flip-flops.
 Here JK are synchronous inputs. There are three operations that can be performed
with flip flop set it to Logic 1, reset it to Logic 0 or complement its output.
 When both inputs are HIGH (Logic 1), then present output is complemented from of
previous output. So, output continuously changes between Logic 1 & Logic 0, on
application of clock pulse. So, the output toggles between Logic 1 & Logic 0. It is
known as Toggling condition.

Figure 8.7: - Symbol : JK Flip-flop

CIRCUIT DIAGRAM OF JK FF

Figure 8.8: - Circuit Diagram of JK Flip-flop

PROCEDURE
• Fix the IC 7410 (Triple I/P NAND) and one 7400 IC (Quad, 2 I/P NAND) on the bread
board.
• Give +Vcc(+5V dc) to pin no. 14 and ground to pin no. 7 of both ICs.
• For the IC 7410, connect the pin no. 1 (J) and pin no. 3 (K) from the input switch
through wires separately and pin no. 2 & 4 will be connected to the CLK input.
• Pin no. 12 of 7410 IC will be shorted with pin no. 1 of 7400 IC.
• Pin no. 6 of 7410 IC will be shorted with pin no. 5 of 7400 IC.
• Pin no. 2 and Pin no. 6 of 7400 IC will get shorted with each other.

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• Pin no. 3 and Pin no. 4 of 7400 IC will get shorted with each other.
• Pin no. 3 (J) and 6 (K) of 7400 IC will be connected to the output LED as ‘𝑄’ 𝑎𝑛𝑑 ′𝑄̅′
respectively.
• Now, pin no. 6 of 7400 IC will be connected to pin no. 13 of 7410 IC.
• Again, connect pin no. 5 of 7410 IC will be connected to pin no. 3 of 7400 IC.
• Recheck the connection and then switch on the power supply of the bread board.
• Give the CLK i/p high (ON) condition.
• For different values of the ‘J’ and ‘K’ as input, observe the output through two outputs
𝑄 𝑎𝑛𝑑 𝑄̅ of the JK flip-flop with different input combinations.

TRUTH TABLE OF JKFLIP-FLOP

CLK J K Q CONDITION
H 0 0 Qn No Change
H 0 1 0 Reset
H 1 0 1 Set
H 1 1 Qn’ Toggle

Figure 8.9: - Symbol: T Flip-flop

Figure 8.10: - Block Diagram of T Flip-flop

PROCEDURE
• The connection procedure of ‘T’ flip-flop is same as the procedure of JK flip-flop
except one modification.
• First connect for JK flip-flop.
• Short the J and K inputs and form it as a single input T.

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• Recheck the connection and then switch on the power supply of the bread board.
• Give the CLK i/p high (ON) condition.
• For different inputs of T, observe the output through two outputs 𝑄 𝑎𝑛𝑑 𝑄̅ of the T
flip-flop with different input combinations.
VERIFICATION TABLE
1. SR FLIP-FLOP
CLK S R Qn Qn+1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 ?
1 1 1 1 ?
0 X X 0 0
0 X X 1 1
2. D FLIP-FLOP
CLK D Qn Qn+1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
0 X 0 0
0 X 1 1

3. JK FLIP-FLOP
CLK J K Qn Qn+1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
0 X X 0 0
0 X X 1 1
4.T FLIP-FLOP

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CLK T Qn Qn+1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
0 X 0 0
0 x 1 1

Figure 8.11: - Pin Configuration of 3 input AND Gate

PRECAUTION
• Make the connections according to the IC pin diagram.
• The connections should be tight.
• The Vcc and ground should be applied carefully at the specified pin only.

PROCEDURE
• Make the connections according to the IC pin diagram.
• The connections should be tight.
• The Vcc and ground should be applied carefully at the specified pin only.
• Apply input to the circuit according to the circuit diagram.
• In case of gray to binary conversion, the inputs are given at respective pins and
outputs are taken for all the combinations.
• Switch on the trainer kit.
• Observe the output.
• Repeat steps for different input as per truth table.
• Verify the truth table.

CONCLUSION

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All the Flip-Flops are designed and verified. It is observed that the observation table is
matching with the truth table.

QUESTIONNAIRE
1. Draw the truth table of SR FF.
2. Write the excitation table of SR FF?
3. Write the characteristic equation of D ff?
4. Why DFF is called Delay FF?
5. Why DFF is called transparent FF?
6. If j=K=0 what will be the behavior of output?
7. Why TFF is called Toggle FF?
8. Differentiate between negative and positive edge trigger.
9. Differentiate between edge trigger and level trigger.
10. Mention the name of IC used for D FF.

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AIM OF THE EXPERIMENT

Shift Registers: Design and investigate the operation of all types of shift registers with
parallel load.

OBJECTIVE
• Identify the 74 Series Integrated circuits (ICs) belong to logic gate and D Flip Flop
and their pin configurations.
• To design Shift Registers (SISO, SIPO, PIPO,PISO) using D flip flops and investigate
the operation of all types of shift registers.
• To verify the truth tables.
COMPONENTS REQUIRED
• IC7474 (DUAL D FLIPFLOP),IC7432,IC7408,IC7404
• Digital Trainer Kit
• Connecting wires
• Twizer
THEORY
Shift registers are the sequential logic circuits, consisting of flip-flops which are important in
applications involving the storage and transfer of data in a digital system. They are generally
found in calculators, computers and data-processing systems. The storage capacity of a shift
register is the total number of bits (1’s and 0’s) of digital data it can retain. Each stage (flip-
flop) represents one bit of storage capacity; therefore, the number of stages determines its
storage capacity. The shifting capability permits the movement of binary information from
stage to stage within the register or into or out of the register upon application of clock
pulses. They are basically classified into following types:
 Serial-In/Serial-Out (SISO)
 Serial-In/Parallel-Out (SIPO)
 Parallel-In/Parallel-Out (PIPO)
 Parallel-In/Serial-Out (PISO)
Serial-In/Serial-Out (SISO)
The SISO shift register accepts data serially, that is, one bit at a time on a single data line. It
produces the stored information on its output also in serial manner. The Circuit Diagram

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represents a 3-bit SISO shift register which consists of three D-type flip-flops (positive edge
triggered) connected in cascade arrangement.

[Figure 9.1: - Circuit Diagram of 3 Bit SISO]

VERIFICATION TABLE
No of positive edge of Clock Serial Input Q2 Q1 Q0
0 - 0 0 0
1 1LSB 1 0 0
2 1 1 1 0
3 0MSB 0 1 1LSB
4 - - 0 1
5 - - - 0MSB

Pin Diagram of IC 7474

Function Table
(Dual D-FF)

PROCEDURE
• Fix two nos. of 7474 IC (dual ‘D’ flip-flop) on the bread board horizontally (since it
requires 3 nos. of D-flip flop and it is 3 bit SISO).
• The two 7474 IC should be identical.
• Connect +Vcc (+5V dc) to pin no. 14 and ground to pin no. 7 to both the 7474 ICs.
• Connect four wires from input switches of bread board separately.

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• First wire is the SET connection and will be connected to pin no. 4 of first 7474 IC.
• Short the pin no. 4 and 10 of first of first IC and again connected it to pin no. 4 of
second 7474 IC.
• Second wire is the clock (CLK) connection and will be connected to pin no. 3 of
second again connect it to pin no. 3 of second 7474 IC.
• Third wire is the RESET connection and will be connected to pin no. 1 and 13 of first
IC and again connect pin no. 1 of second 7474 IC.
• Fourth wire is the serial input (I/P Data) connection and will be connected to pin no.
2 of first 7474 IC. (i.e., first D-flip flop input).
• First D-flip flop output will be connected to 2nd D-flip flop input. (i.e., pin no. 5 of first
7474 IC will be connected to pin no. 12 of same IC).
• The output of second D-flip flop will be connected to input of the third D-flip flop
(i.e., pin no. 9 of first 7474 IC will be connected to pin no. 2 of second 7474 IC).
• Pin no. 5 of second IC will be connected to output LED and that is serial output (Q 0)
of the register.
• Verify the ICs connections once again.
• Now switch ON the power supply as well as bread board.
• Give the input data through serial input point.
• Give three clock (CLK) pulses and the data ‘1’ will be appear at serial output point
(Q0) which is the required output.
• Similarly, all other data can be sent serially and study the output at serial output point.

EXPLANATION
• Let us see the working of 3-bit SISO shift register by sending the binary
information “011” from LSB to MSB serially at the input.
• Assume, initial status of the D flip-flops from leftmost to rightmost is Q2Q1Q0=000.
• The initial status of the D flip-flops in the absence of clock signal is Q2Q1Q0=000.
• Here, the serial output is coming from Q0. So, the LSB 1 is received at 3rd positive
edge of clock and the MSB 0is received at 5th positive edge of clock.
• Therefore, the 3-bit SISO shift register requires five clock pulses in order to produce
the valid output.
• Similarly, the N-bit SISO shift register requires 2N-1 clock pulses in order to shift ‘N’
bit information.

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Serial-In/Parallel-Out (SIPO)
The Circuit Diagram illustrates a SIPO shift register, into which the data bits are entered
serially (right-most bit first). The difference is the way in which the data bits are taken out
of the register; in the parallel output register, the output of each stage is available. Once the
data are stored, each bit appears on its respective output line and all bits are available
simultaneously, rather than on a bit-by-bit basis as with the serial output.

[Figure 9.2: - Circuit Diagram of 3 Bit SIPO]

PROCEDURE
• Fix two nos. of 7474 IC (dual ‘D’ flip-flop) on the bread board horizontally (since it
requires 3 nos. of D-flip flop and it is 3-bit SIPO).
• The two 7474 IC should be identical.
• Connect +Vcc (+5V dc) to pin no. 14 and ground to pin no. 7 to both the 7474 ICs.
• Connect four wires from input switches of bread board separately.
• First wire is the SET connection and will be connected to pin no. 4 of first 7474 IC.
• Short the pin no. 4 and 10 of first of first IC and again connected it to pin no. 4 of
second 7474 IC.
• Second wire is the clock (CLK) connection and will be connected to pin no. 3 of
second again connect it to pin no. 3 of second 7474 IC.
• Third wire is the RESET connection and will be connected to pin no. 1 and 13 of first
IC and again connect pin no. 1 of second 7474 IC.
• Fourth wire is the serial input (I/P Data) connection and will be connected to pin no.
2 of first 7474 IC. (i.e., first D-flip flop input).
• First D-flip flop output will be connected to 2nd D-flip flop input. (i.e., pin no. 5 of first
7474 IC will be connected to pin no. 12 of same IC).

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• The output of second D-flip flop will be connected to input of the third D-flip flop
(i.e., pin no. 9 of first 7474 IC will be connected to pin no. 2 of second 7474 IC).
• Pin no. 5 of second IC will be connected to output LED.
• In this case three outputs (Q2, Q1, Q0) will be taken instead of one and all these
outputs will be connected to output of bread board separately.
• Pin no. 5 of first 7474 IC is connected to Q0, Pin no. 9 of first 7474 IC is connected to
Q1, Pin no. 5 of second 7474 IC is connected to Q2. Accordingly, the outputs will be
taken from these pins.
• Verify the ICs connections once again.
• Now switch ON the power supply as well as bread board.
• Give the input data through serial input point. (As in the truth table)
• It will require three clock pulses to get the data at the output terminals.
• Similarly, all other data can be sent serially and study the output at parallel output
point.

VERIFICATION TABLE
No of positive edge of Clock Serial Input Q2 Q1 Q0
0 - 0 0 0
1 1LSB 1 0 0
2 1 1 1 0
3 0MSB 0 1 1

EXPLANATION
• Let us see the working of 3-bit SIPO shift register by sending the binary
information “011” from LSB to MSB serially at the input.
• Assume, initial status of the D flip-flops from leftmost to rightmost is Q2Q1Q0=000.
Here, Q2 & Q0 are MSB & LSB respectively.
• The initial status of the D flip-flops in the absence of clock signal is Q2Q1Q0=000. The
binary information “011” is obtained in parallel at the outputs of D flip-flops for
third positive edge of clock.
• So, the 3-bit SIPO shift register requires three clock pulses in order to produce the
valid output. Similarly, the N-bit SIPO shift register requires N clock pulses in order
to shift ‘N’ bit information.

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Parallel-In/Parallel-Out (PIPO)
The Circuit Diagram illustrates a PIPO shift register the data bits are entered simultaneously
into their respective stages on parallel lines rather than on a bit-by-bit basis on one line as
with serial data inputs. Also, the output of each stage is available simultaneously.

[Figure 9.3: - Circuit Diagram of 3 Bit PIPO]

PROCEDURE
• Fix two nos. of 7474 IC (dual ‘D’ flip-flop) on the bread board horizontally (since it
requires 3 nos. of D-flip flop and it is 3-bit PIPO).
• The two 7474 IC should be identical.
• Connect +Vcc (+5V dc) to pin no. 14 and ground to pin no. 7 to both the 7474 ICs.
• Connect three wires from input switches of bread board separately for SET, Clock
(CLK), and RESET connections.
• First wire is the SET connection and will be connected to pin no. 4 of first 7474 IC.
• Short the pin no. 4 and 10 of first of first IC and again connected it to pin no. 4 of
second 7474 IC.
• Second wire is the clock (CLK) connection and will be connected to pin no. 3 of
second again connect it to pin no. 3 of second 7474 IC.
• Third wire is the RESET connection and will be connected to pin no. 1 and 13 of first
IC and again connect pin no. 1 of second 7474 IC.
• Connect the pin no. 2 (D0) of first 7474 IC. (i.e., first D-flip flop input). D1 will be
connected to the pin no. 12 (D0) of first 7474 IC and D2 will be connected to the pin
no. 2 of the second 7474 IC.
• Connect three wires to output LEDs separately and will be connected to Q2, Q1, Q0.

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• Pin no. 5 of first 7474 IC is connected to Q0, Pin no. 9 of first 7474 IC is connected to
Q1, and Pin no. 5 of second 7474 IC is connected to Q2. Accordingly, the outputs will
be taken from these pins.
• Verify the ICs connections once again.
• Now switch ON the power supply as well as bread board.
• Give the input data through input switches (D2, D1, D0) in parallel and the data will
be transferred to output (Q2, Q1, Q0) with single clock pulse. (As in the truth table)
• It will require three clock pulses to get the data at the output terminals.
• Similarly, all other data can be sent serially and study the output at parallel output
point.
VERIFICATION TABLE
No of positive edge of Parallel Input
Q2 Q1 Q0
Clock D2 D1 D0
0 0 0 0 0 0 0
1 1 0 0 1 0 0
2 1 1 0 1 1 0
3 0 1 1 0 1 1

EXPLANATION
• The binary information “000” is obtained in parallel at the outputs of D flip-flops
before applying positive edge of clock.
• Therefore, the 3-bit PIPO shift register requires zero clock pulses in order to produce
the valid output. Similarly, the N-bit PIPO shift register doesn’t require any clock
pulse in order to shift ‘N’ bit information.

Parallel-In/Serial-Out (PISO)
Fig illustrates a 3-bit PISO shift register. D0 and D1 are the two-parallel data-input lines and an
input allow 3 bits of data to load in parallel into the register. When goes LOW, the rightmost
AND gate is enabled, allowing the data bit to be applied to D1 of 2nd flip-flop. When it is HIGH,
the 1st AND gate is enabled, thereby permitting the data bit to shift right from one stage to
the next stage. The OR gate allow either the normal shifting operation or the parallel data-
entry operation, depending on which AND gate is enabled by the level of.

Circuit Diagram of 3-bit PISO Shift Register

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[Figure 9.4: - Circuit Diagram of 3 Bit PISO]

PROCEDURE
• Fix the following ICs on the Breadboard as per the circuit diagram for 3-bit PISO Shift
register.
o NOT gate (7404) IC ---1no.
o OR gate (7432) IC----1no.
o AND gate (7408) IC---2nos.
o Dual D Flip-flop (7474) IC-2nos.
• ICs should be tight and properly inserted.
• Short all pin 14 of the ICs and connect it to +VCC (+5V dc) of the Breadboard.
• Short all pin 7 of the ICs and connect it to ground of the Breadboard.
• Connect five input wires from the input switches of Breadboard.
• First input will be connected as clock (CLK) input and will be connected to pin no. 3
& 11 of 1st D Flip-flop (7474) IC and will be shorted to pin no. 3 of 2nd D Flip flop
(7474) IC.
• Second input will be connected as Load /Shift (active low) input and will be
connected to pin no. 1 of NOT (7404) IC.
• Pin no. 2 of 7404 IC will be connected to pin no. 1 and 9 of 1st AND (7408) IC and
again it will be shorted to pin no, 1 of 2nd AND (7408) IC.
• Second input also shorted to pin no. 5 of 1st AND (7408) IC and pin no. 13 of 2nd AND
(7408) IC.
• Third, Fourth and Fifth inputs are data lines named as D 0, D1 and D2.
• D2 will be connected to pin no. 2 of 1st AND (7408) IC.
• D1 will be connected to pin no. 10 of 1st AND (7408) IC.
• D0 will be connected to pin no. 2 of 2nd AND (7408) IC.
• Pin no. 3 of 1st AND (7408) IC will be connected to pin no. 2 of 1st D Flip-flop, i.e.D2.
• Q2 of 1st D Flip flop (i.e., pin no. 5) will be connected to pin no. 4 of 1stAND (7408) IC.

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• Pin no. 6 and pin no. 8 of 1st AND (7408) IC will be connected to pin no. 1 and 2 of OR
(7432) IC respectively.
• Q1 of 1st D Flip flop(i.e., pin no.9) will be connected to pin no 12 of 1stAND (7408) IC.
• Pin no. 11 of 1st AND (7408) IC will be connected to pin no. 4 of OR (7432) IC.
• Pin no. 3 of 2nd AND (7408) IC will be connected to pin no. 5 of OR (7432) IC.
• Pin no. 6 of OR (7432) IC will be connected to pin no. 2 of 2nd D Flip flop (7474) IC and
i.e., D0.
• Pin no. 5 of 2nd D Flip flop (7474) IC i.e., Q0 will be connected to output LED and that
is Serial Data output.
• Verify the connections once again according to the circuit diagram with step-by-step
procedure.
• Switch ON the Breadboard now.
• Give the inputs through D0, D1 and D2 (Example- Input data is “011”) and find the
output at Q0 after two clock pulse.

VERIFICATION TABLE
No of positive edge of Clock Q2 Q1 Q0
0 0 1 1LSB
1 - 0 1
2 - - 0LSB

EXPLANATION
• Let us see the working of 3-bit PISO shift register by applying the binary
information “011” in parallel through preset inputs.
• Since the preset inputs are applied before positive edge of Clock, the initial status
of the D flip-flops from leftmost to rightmost will be Q2Q1Q0=011.
• Here, the serial output is coming from Q0. So, the LSB ‘11’ is received before applying
positive edge of clock and the MSB ‘00’ is received at 2ndpositive edge of clock.
• Therefore, the 3-bit PISO shift register requires two clock pulses in order to produce
the valid output. Similarly, the N-bit PISO shift register requires N-1 clock pulses in
order to shift ‘N’ bit information.

CONCLUSION

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We have designed all the Shift Registers (SISO, SIPO, PIPO, PISO) and investigated the
operation of all types of shift registers after identifying the 74 Series Integrated circuits (ICs)
belong to logic gate and D Flip Flop and their pin configurations. Also verified the truth
tables.

QUESTIONNAIRE
1. What type of shift register is fastest?
2. Based on how binary information is entered or shifted out, shift registers are
classified into _______ categories.
3. What is meant by parallel load of a shift register?
4. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel
output shift register with an initial state 01110. After three clock pulses, the register
contains ________
5. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store
the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-
most bit first)
6. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register
in ________
7. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to
achieve a time delay (td) of ________
8. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After
three clock pulses, the data outputs are ________
9. What type of register would have a complete binary number shifted in one bit at a
time and have all the stored bits shifted out one at a time?
10. The register is which type of circuit.
11. How many methods of shifting of data are available?

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AIM OF THE EXPERIMENT

Counters: Design, assemble and test various ripple and synchronous counters.

OBJECTIVES
 Design and Implement MOD-8 Asynchronous UP &Down Counter using JK flip flop.
 To verify the truth table of asynchronous counter by applying clock pulse and
changing the input.
 Design and Implement MOD-8 Synchronous Counter.
 To verify the truth table of synchronous counter by applying clock pulse and changing
the input. Also draw the timing diagram using the truth table.
COMPONENTS REQUIRED
• IC 7476(DUAL JK FLIPFLOP)
• IC7408
• Digital Trainer Kit
• Connecting wires
• Twizer
Theory
A Digital Counter is a set of Flip Flops (FFs) whose states change in response to pulses applied
at the input to the counter. The FFs are interconnected such that their combined state at
any time is the binary equivalent of the total no. of pulses that have occurred up to that
time. We know that JK flip-flop toggles the output either for every positive edge of clock
signal or for every negative edge of clock signal. An ‘N’ bit binary counter consists of ‘N’ JK
flip-flops. If the counter counts from 0 to 2𝑁 − 1, then it is called as binary up counter.
Similarly, if the counter counts down from 2 𝑁 − 1 to 0, then it is called as binary down
counter. Counter may be synchronous or asynchronous counter.
• Asynchronous counters are also called as ripple counter where the FFs are not triggered
simultaneously i.e. the FFs are not made to change the state (o/p) exactly at the same
time. Only the first flip-flop is externally clocked using clock pulse while the clock input
for the successive flip-flops will be the output from a previous flip-flop.
✓ In The 3-bit Asynchronous binary up counter contains three JK flip-flops and the
JK-input of all the flip-flops are connected to '1'. All these flip-flops are negative
edge triggered but the outputs change asynchronously. The clock signal is directly
applied to the first JK flip-flop.

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✓ The output of first T flip-flop is applied as clock signal for second JK flip-flop. So,
the output of second JK flip-flop toggles for every negative edge of output of first
JK flip-flop. Similarly, the output of third JK flip-flop toggles for every negative edge
of output of second JK flip-flop, since the output of second JK flip-flop acts as the
clock signal for third JK flip-flop.
✓ The block diagram of 3-bit Asynchronous binary down counter is similar to the
block diagram of 3-bit Asynchronous binary up counter. But the only difference is
that instead of connecting the normal outputs of one stage flip-flop as clock signal
for next stage flip-flop, connect the complemented outputs of one stage flip-flop
as clock signal for next stage flip-flop. Complemented output goes from 1 to 0 is
same as the normal output goes from 0 to 1.

CIRCUIT DIAGRAM OF MOD-8 ASYNCHRONOUS UP COUNTER

TRUTH TABLE OF MOD-8 ASYNCHRONOUS UP COUNTER

Present State Next State
QC QB QA QC QB QA
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
CIRCUIT DIAGRAMOF MOD-8 ASYNCHRONOUS DOWN COUNTER

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TRUTH TABLE OF MOD-8 ASYNCHRONOUS DOWN COUNTER

Present State Next State
QC QB QA QC QB QA
0 0 0 1 1 1
0 0 1 0 0 0
0 1 0 0 0 1
0 1 1 0 1 0
1 0 0 0 1 1
1 0 1 1 0 0
1 1 0 1 0 1
1 1 1 1 1 0

In a ‘Synchronous counter’, all the flip-flops change their state simultaneously, the operation
of each being initiated by the clock. This is done by connecting the input clock to each flip-
flop of the counter; hence all flip-flops are clocked simultaneously. These counters are
classified according to, a) Sequence of states, b) Number of states, c) Number of flip-flops
(stages) used in the counter. Here all flip-flops are triggered simultaneously. Hence, these
counters are called “parallel counters”.
Synchronous binary counter: In a synchronous binary counter, we must note the following,
1. Clock pulse is applied common to all flip-flops.
2. The flip-flop in the lowest-order position is complemented with every clock pulse
and the JK inputs are maintained at logic 1 (to get toggling action).
3. The flip-flop in any other position is complemented with a pulse, provided all the
bits in the lower-order positions are equal to 1.
4. The binary count dictates the next bit to be complemented.
The above procedures are illustrated by taking a 3-bit synchronous counter.
CIRCUIT DIAGRAM OF [MOD-8 (3-BIT) SYNCHRONOUS COUNTER]

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TRUTH TABLE OF MOD-8 (3-BIT) SYNCHRONOUS COUNTER

TIMING DIAGRAM OF MOD-8 (3-BIT) SYNCHRONOUS COUNTER

Pin Diagram of IC 7476 Function Table

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Pin Details of IC 7476

Pin 1 is an input pin. It is used to give the clock pulse to the first JK flip
1 CLK Pin 1
flop. HIGH to LOW pulse will only affect the flip flop.
Pin 2 is a preset input pin. It is used to make the output (1Q) of first flip
1 PRE’ Pin 2
flop HIGH. It’s an active LOW pin.
Pin 3 is a clear input pin of the first flip flop. It is used to reset the
1 CLR’ Pin 3
output of first flip flop. It’s an active LOW pin.
Pin 4 is the first input pin of the first flip flop. It is used to give the first
Input 1, J Pin 4
input data bit to the IC. It can be HIGH or LOW.
Pin 5 is used as the power pin. It is used to power up the IC to make it
VCC Pin 5
functional.
Pin 6 is an input pin. It is used to give the clock pulse to the clock of the
2 CLK Pin 6
second JK flip flop. HIGH to LOW pulse will only affect the IC.
Pin 7 is a preset input pin of the second flip flop. It is used to make the
2 PRE’ Pin 7
output (2Q) of second flip flop HIGH. It’s an active LOW pin.
Pin 8 is a clear input pin of the second flip flop. It is used to reset the
2 CLR’ Pin 8
output of second flip flop. It’s an active LOW pin.
Pin 9 is the first input pin of the second flip flop. It is used to give the
Input 2, J Pin 9
first input data bit to the IC. It can be HIGH or LOW.
Pin 10 is the second output pin of the second flip flop. It will give the
2Q’ Pin 10
inverted output of Pin 11.
Pin 11 is the first output pin of the second first flop. It will give the
OUTPUT 2Q Pin 11
output bit of the second flip flop.
Pin 12 is the second input pin of the second flip flop. It is used to give
Input 2K Pin 12
the second input data bit to the IC. It can be HIGH or LOW.
Pin 13 is a ground pin. It is used to make common ground with power
GND Pin 13
supply and other devices if there’s any.
Pin 14 is the second output pin of the first flip flop. It will give the
1Q’ Pin 14
inverted output of Pin 15.
Pin 15 is the first output pin of the first flip flop. It will give the output
OUTPUT 1Q Pin 15
bit of the first flip flop.
Pin 16 is the second input pin of the first flip flop. It is used to give the
Input 1K Pin 16
second input data bit to the IC. It can be HIGH or LOW.
We can also use IC 7473 (DUAL JK FF) instead of IC7476
Pin Diagram of IC 7473 Function Table

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Pin Details of IC 7473

PROCEDURE MOD-8 (3-BIT) ASYNCHRONOUS COUNTER

• Make the connections according to the IC pin diagram.
• The connections should be tight.
• The Vcc and ground should be applied carefully at the specified pin only.
• Apply input to the circuit according to the circuit diagram.
• Switch on the trainer kit.
• Observe the output on 8-bit LED display
• Repeat steps for different input as per truth table.
• Verify the truth table.

PROCEDURE MOD-8 (3-BIT) SYNCHRONOUS COUNTER

• Set JA = 0 and KA= 0, so flip-flop A is in toggling condition.
• Flip-flop B toggles, when QA= 1 and when QB= 0, flip-flop B is in the no-change mode
and remains in its present state.
• From the truth table it can be noticed that flip-flop C has to change its state only
when QA& QB both are at logic 1.

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• This condition is detected by AND gate and applied to JC and KC inputs of flip-flop C.
• Whenever both QA& QB both are at logic 1, the output of the AND gate makes the J
and K inputs of flip-flop C HIGH, and flip-flop C toggles on the clock pulse. At other
times (i.e., other than QA& QB= 1), the J and K inputs of flip-flop ‘C’ are held LOW by
the AND gate output, and the flip-flop does not change its state.

CONCLUSION
We have designed and Implemented MOD-8 Asynchronous UP & Down Counter and MOD-
8 Synchronous Counter using JK flip flop. Also verified the truth table of counters by applying
clock pulse and changing the input and drawn the timing diagram using the truth table.

QUESTIONNAIRE
1. How many natural states will there be in a 4-bit ripple counter?
2. Mention major drawbacks to the use of asynchronous counters.
3. Internal propagation delay of asynchronous counter is removed by which type of
counter.
4. What happens to the parallel output word in an asynchronous binary down counter
whenever a clock pulse occurs?
5. How many different states does a 3-bit asynchronous counter have?
6. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns
propagation delay. The total propagation delay (tp(total)) is ____________
7. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How
many transitional states are required?
8. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from
clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a
total of ____________
9. A 4-bit counter has a maximum modulus of ____________
10. What is the maximum possible range of bit-count specifically in n-bit binary counter
consisting of ‘n’ number of flip-flops?
11. How many different states does a 3-bit asynchronous down counter have?
12. In a down counter, which flip-flop doesn’t toggle when the inverted output of the
preceding flip-flop goes from HIGH to LOW.

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AIMOF THE EXPERIMENT

Counters: Design, assemble and test Decimal counter, Binary counter with parallel load.

OBJECTIVE
Design, Implement and Verification of
• MOD-10 Asynchronous (Decimal) Counter
• Binary Counter with Parallel Load.

COMPONENTS REQUIRED
• IC 7476(DUAL JK FLIPFLOP)
• IC7404
• IC 74161(For Binary counter with parallel load)
• Trainer Kit
• Connecting wires
• Twizer
THEORY:
MOD-10 Asynchronous (Decimal) Counter: A decimal (MOD-10 Asynchronous) counter
follows a sequence of ten states and returns to 0 after the count of 9. The counters with
ten states in their sequence called are ‘decade counters’. These counters are useful in
display applications in which BCD is required for conversion to a decimal read out. A
counter with a count sequence of 0 (0000) through 9 (1001) is called a BCD counter,
because it’s ten-states sequence is the BCD code. The sequence of states is shown in the
state diagram as follows,

MOD-10 (4-BIT) ASYNCHRONOUS COUNTER STATE DIAGRAM

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CIRCUIT DIAGRAM OF MOD-10 (4-BIT) ASYNCHRONOUS COUNTER

TRUTH TABLE OF MOD-10 (4-BIT) ASYNCHRONOUS COUNTER

TIMING DIAGRAM OF MOD-10 (4-BIT) ASYNCHRONOUS COUNTER

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PROCEDURE TO DESIGN MOD-10 ASYNCHRONOUS (DECIMAL) COUNTER

• Connect the clock input to the first flip-flop only.
• The second, third and fourth flip-flops are triggered by the outputs QA, QB, and QC
respectively. The output Q of the counter is given by, Q = QDQCQBQA.
• From the timing diagram it can be observed that the output HIGH-to-LOW transition
of QA occurs only one delay time after the clock pulse.
• The HIGH-to-LOW transition of QB occurs one delay time after QA.
• The LOW-to-HIGH transition of QC occurs one delay time after QB.
• The QD occurs only one delay time after QC. In this manner, the counting process
continues from the count 0000 to 1001.
• When the counter goes to count 1010, the NAND gate output goes LOW and all flip-
flop are in clear condition. Thus, when 10th clock pulse occurs, the counter output Q
is 0000 instead of 1010.

BINARY COUNTER WITH PARALLEL LOAD

A binary counter is basically a state machine that just cycles through its states for each of a
clock signal. A parallel load of a counter refers that, all the connected flip-flops are preset
with data. Counters employed in digital systems quite often require a parallel load capability
for transferring an initial binary number into the counter prior to count operation. The input
load control when equal to 1 disables the count operation and causes a transfer of data from
the four data inputs into the four flip-flops. A counter with parallel load can be used to
generate any desire count sequence.
IC type 74161 is a four-bit synchronous binary counter with parallel load and asynchronous
clear. The pin assignments to the inputs and outputs are shown in Fig. When the load signal
is enabled, the four data inputs are transferred into four internal flip-flops, QA through QD,
with QD being the most significant bit. There are two count-enable inputs called P and T .
Both must be equal to 1 for the counter to operate. To load the input data, the clear input
must be equal to 1 and the load input must be equal to 0. The two count inputs have don’t-
care conditions and may be equal to either 1 or 0. The internal flip-flops trigger on the
positive transition of the clock pulse. The circuit functions as a counter when the load input
is equal to1 and both count inputs P and T are equal to 1. If either P or T goes to 0, the output

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Circuit Diagram of 4-Bit Binary Counter with parallel load

Pin Configuration of IC 74161(Used for 4 bit Binary counter with parallel load)

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PROCEDURE:
• Make the connections according to the IC pin diagram.
• The connections should be tight.
• The Vcc and ground should be applied carefully at the specified pin only.
• Apply input to the circuit according to the circuit diagram.
• Switch on the trainer kit.
• Observe the output.
• Repeat steps for different input as per truth table.
• Verify the truth table.
CONCLUSION
We have designed and implemented MOD-10 Asynchronous (Decimal) Counter and Binary
Counter with Parallel Load. Also verified through truth table.
QUESTIONNAIRE
1. BCD counter is also known as ____________
2. What do you mean by BCD counter?
3. Draw state diagram of BCD counter.
4. How many flip-flops are required to make a MOD-32 binary counter?
5. The terminal count of a modulus-11 binary counter is ________.
6. Why Synchronous counters eliminate the delay problems encountered with
asynchronous counters?
7. What do you understand by counter?
8. What is asynchronous counter?
9. What is synchronous counter?
10. What do you understand by modulus?
11. What do you understand by state diagram?
12. Why Asynchronous counter is known as ripple counter?
13. Which type of counter is used in traffic signal?

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AIM OF THE EXPERIMENT

Memory Unit: Investigate the behavior of RAM unit and its storage capacity – 16 X4 RAM:
testing, simulating and memory expansion.

OBJECTIVES
• To learn about the function of RAM.
• To calculate the total memory capacity of RAM from its given specifications.
• To understand the difference between Static and Dynamic RAM and how is it
different from ROM.
HARDWARE REQUIRED
1-bit RAM 16*4 RAM
• IC 2114 • Oscilloscope
• Patch Cords • Signal generator
• IC Trainer Kit. • Two TTL 16x4 RAM (7489)
• One TTL binary counter (7493)
• One TTL inverter (7404)
• Four LEDs and limiting resistors
THEORY
Static random-access memory (static RAM or SRAM) is a type of random-access
memory (RAM) that uses latching circuitry (flip-flop) to store each bit. SRAM is volatile
memory, data is lost when power is removed. A typical SRAM cell is made up of
six MOSFETs. Each bit in an SRAM is stored on four transistors (M1, M2, M3, M4) that form
two cross-coupled inverters. This storage cell has two stable states which are used to
denote 0 and 1. Two additional access transistors serve to control the access to a storage
cell during read and write operations
The term static differentiates SRAM from DRAM (dynamic random-access memory) which
must be periodically refreshed. Unlike dynamic RAM (DRAM), which stores bits in cells
consisting of a capacitor and a transistor, SRAM does not have to be periodically refreshed.
SRAM provides faster access to the data and more expensive than DRAM, it is typically used
for CPU cache while DRAM is used for a computer's main memory.
The size of an SRAM with m address lines and n data lines is 2m words, or 2m × n bits. The
most common word size is 8 bits, meaning that a single byte can be read or written to each
of 2m different words within the SRAM chip. Several common SRAM chips have 11 address
lines (thus a capacity of 2m = 2,048 = 3d words) and an 8-bit word, so they are referred to as
"2k × 8 SRAM".

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SRAM cell circuit diagram (made up of six MOSFETs)

Pin Diagram of IC 2114

16*4 RAM
RAM circuits on the market have different configurations depending upon how the memory
cell array is organized. A memory cell array organized with N by M cells can store N words
with each word being M bits long. For example, the IC type 7489 is a 16 by 4 RAM chip. It
can store up to 16 different words, and each word is 4 bits long. Apart from memory cell
array, RAM circuits also need address decoding logic and read/write control logic. The
address decoding logic translates the data address (usually in binary format) into the
physical location of a particular word in the memory cell array. Therefore, the memory cells
in the specified memory word are activated and ready to either put the data on to the data
output pins (read process), or to receive data from the data input pins (write
process). Whether the process is read or writes, depends upon the read/write control
logic. Read and write processes are also referred to as data fetch and data load respectively.
IC 7489 pin assignment to the inputs and outputs is shown in Fig.

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Pin Connection of IC 7489

The four address inputs select one of the 16 words in the memory. The least significant bit
of the address is A, and the most significant bit is D. The read/write control logic has two
control inputs. The memory enable (ME) input must be equal to low to enable the memory.
If ME is high, the memory is disabled and all four outputs are at high impedance level. The
write operation is performed when WE is low. This is a transfer of the binary data from the
data inputs lines into the selected word in memory. The read operation is performed
when WE is high. This transfers the value stored in the selected word into the output data
lines (complemented). The inverted outputs are open-collector to allow external wired logic
for memory expansion.
TESTING
An open-collector gate requires an external resistor for proper operation. However, an
open-collector gate can be operated without an external resistor if its output is connected
to the input of another gate. Since the outputs of the 7489 produce complemented values,
we might as well insert four inverters to change the outputs to their normal values and, at
the same time, avoid the need for external resistors. Let’s connect the address inputs to a
binary counter using IC 7493 as shown in Fig. Below
Address inputs connection to a binary counter using IC 7493

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Now Let’s connect the four data inputs to toggle switches and the data outputs to four 7404
inverters. Provide four LEDs for the address and four more for the outputs of the inverters.
Connect ME to ground and WE to a pulser that provides a negative pulse. Store a few
words into the memory and then read them to verify that the write and read operations
function properly. Leave the WE in the read mode (high), unless you want to write into
memory. The proper way to write is first set the address using the counter and the inputs
with the four toggle switches. To store the word in memory, pulse the WE switch to the
write position. Be careful not to change the address or the inputs when WE is asserted.
EXPANSION
The memory unit may be expanded to a 32 by 4 RAM using two 7489 ICs. The ME input may
be used to select between the two ICs. Since the data outputs are open-collector, we can tie
pairs of terminals together to obtain a logic wired-OR operation in conjunction with the
output inverter.
PROCEDURE
• Connections are made as appropriate to the IC 2114 as shown in the logic diagram
using the pin details of the gates.
• Connect Vcc and GND to respective pins of each IC.
• For writing the data make the CS and WR to low.
• For a 4-bit data, select any address input from A0 to A9, e.g. select A0 to A3 and
connect the data input/outputs I/O4-I/O1.
• Write a 4-bit data in each address input or memory location.
• By doing repeatedly above 3 steps data will be stored in the memory locations.
• Similarly, for reading the data:
• Make WR to high and CS to low.
• Disconnect the data inputs I/O4-I/O1 from input lines and connect them to
output lines.
• Give the address inputs of the data which you have stored and observe the
output through I/O4-I/O1.
• Switch on the supply on the Trainer.

CONCLUSION
The circuit is designed and tested.

QUESTIONNAIRE:

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1. What is meant by the term RAM?

2. What are the two kind of main memory?
3. What is the name given to the memory which works on time sharing principle in
order to create an illusion of infinite memory space?
4. What is the main advantage of semiconductor RAM?
5. Why is SRAM more preferably in non-volatile memory?
6. Which storage element is used by MAC and IBM PC?
7. Which type of storage element of SRAM is very fast in accessing data but consumes
lots of power?
8. What is approximate data access time of SRAM?
9. How many MOSFETs are required for SRAM?
10. Which of the following memory technology is highly denser?

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AIM OF THE EXPERIMENT

Clock-pulse generator: design, implement and test.

OBJECTIVE
To design, implement and verify the Clock-pulse generator circuit

COMPONENTS REQUIRED
• A 555 Timer IC (NE555P)
• Capacitors (10nF, 47uF)
• Resistors (1kΩ, 10kΩ, 4.7kΩ)
• Light Emitting Diode – Green
• Trainer Kit
• Connecting wires
• Twizer
THEORY
In this experiment we are going to design a circuit that generates an automatic clock signal,
which we can use to drive our digital circuits. The digital circuits can be clocked manually,
but an automatic solution would be preferred if we wish to clock many times in a row. Also,
one limitation is that we need a clock signal that is slow enough to see what is happening in
the circuit - if we were to have a clock signal of 1 MHz, we would not be able to observe the
changes in the circuit as they would occur at the rate of 1,000,000 times per second. We will
examine the use of the 555 Timer to output a very low frequency rectangular clock pulse of
approximately 1Hz.
As discussed earlier the flip-flops have two stable states; therefore, they are bistable
multivibrators. There is also a type of circuit that has no stable stages – this is called as an
astable multivibrator.
The 555 Timer as an Astable Multivibrator
The 555 Timer is a TTL compatible IC that operates in three modes: Monostable, Bistable
and Astable. The astable mode allows the timer to operate as an oscillator that outputs a
continuous rectangular pulse of a designed frequency. This is a very popular chip that is used
widely in electronic circuits because of its stability and its low cost. It can be used to generate
clock signals of a very high frequency, but we will use the timer to output a very low
frequency rectangular clock pulse of approximately 1Hz, i.e., 1 cycle per second. This will
allow us to see the effects of the clock pulse on our circuit.

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The 555 Timer (NE555P) IC Pin Configuration

Figure 1. The 555 Timer (NE555P) Pin Layout

Figure 1 illustrates the pin layout of the 555 timer that is in your kit, the NE555P. The 555
timer is a versatile device that can be used in several different configurations. For this
experiment we don't need to be overly concerned with the function of each pin as we are
choosing only one configuration i.e., stable mode.
In the astable mode configuration, we need two resistors (R1, R2) and two capacitors (C1,
C2) to design a circuit that will operate at the frequency required. The frequency and duty
cycle (explained below) are controlled with these two resistors and the first capacitor. The
threshold level is usually 2/3 of Vcc and the trigger levels are usually 1/3 of Vcc. Through
some clever circuitry, these levels cause an internal flip-flop to be set and reset. This IC can
operate in the range of 5V to 15V, but if we use a 5V supply then it is compatible with our
TTL circuitry.
Circuit Diagram of The 555 Timer used in Astable Mode

Figure 2. The 555 Timer used in Astable Mode

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Figure 2, illustrates a 555-timer configuration for astable mode operation. The capacitor C2
is optional and is dependent on the application, but decoupling CONT to GND through a
capacitor can improve operation. We will use a value of 10nF for C2. Now, we must choose
values for the other three components - in astable mode the frequency (f) of the clock signal
can be designed by choosing appropriate values of R1, R2 (in Ω (ohms)) and C1 (in farads) as
follows:

Where the high pulse time is given by:

And the low pulse time is given by:

These equations describe how we can choose these 3 values to decide on the frequency of
our signal and the high and low times of our signal. The ratio of high to low time in a single
period of our signal is called the duty-cycle, or more particularly the fraction of the time that
the signal is high. With the 555 timer the minimum value of R1 in this configuration is
typically 1kΩ and this means that we cannot get a perfect 50% duty cycle - If we make R2 >>
R1 then we can get close. If we set R1 < 1kΩ it will draw excessive current and could damage
the 555 IC.

Figure 3. The Clock Cycle and the Duty Cycle

Figure 3 illustrates the clock signal that we wish to generate. Our signal has a period T, and
therefore a frequency of f=1/T. In our case we wish to have a frequency of approximately 1
second, with thigh = flow = 0.5 sec. The duty cycle:

which in our case = 0.5sec/1sec = 0.5 or 50%.

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PRECAUTION
Before starting to configure the 555 chip, we must ground ourselves since static electricity
can give a lethal jolt. Also, we must be careful when soldering the 1µF capacitor (C1) and the
LED as they are polarized. The negative side of the capacitor will be marked with negative
symbols on the capacitor’s body. The flat edge on the LED indicates the negative side or you
can look at the LED's legs. The shorter leg is the negative lead.

PROCEDURE
1.1 Let’s configure the above circuit. When looking at the chip from above (top view), the
pin to the left of the notch is pin #1. The chip is powered by a 5 V DC source. The
resistors and capacitors of standard values are mentioned which many be connected
and the circuit may look like as shown below.

1.2 The RC combinations control the timer's threshold at pin #6. The output of the timer
(pin#3) oscillates between high (on) and low (off). The oscillation frequency is
obviously a function of the values of the resistors and the capacitor. A large RC time
constant results in lower blinking frequency (longer duration). We may select C1 in the
range of 1 µF - 100 µF. A larger capacitance value may be chosen if the blinking speed
is too fast. We may repeat the experiment with higher capacitance value to control
interval i.e., the frequency in a way.

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CONCLUSION
This experiment has provided us with a useful tool for future experiments. Rather than
manually clocking our flip-flop or counter circuits, we will be able to automatically clock our
circuits. The 555 timers also work at much higher frequencies and is a useful timer for small
circuits that you may wish to build - which explains why up to a billion of these timers are
sold annually.

QUESTIONNAIRES
1. What is a 555 IC?
2. List a few applications of 555 IC?
3. What is a 7555 IC?
4. What are astable, monostable and bistable multivibrators?
5. Write the formula to calculate the time period of the astable and monostable
multivibrator?
6. What is called frequency and duty cycle?
7. How to calculate frequency and duty cycle of an astable multivibrator output?
8. Why the Reset pin of IC 555 is normally connected to Vcc?
9. Why the control voltage pin (pin 5) of 555 timers is connected to ground through a
0.01µf capacitor?
10. Calculate the ON time, OFF time, Total time period, Duty cycle and Frequency of the
output generated by an astable multivibrator using resistors RA = 5k, RB =5K and
capacitor C = 10µf.

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AIM OF THE EXPERIMENT

Design, implement and test Parallel adder and Accumulator.

OBJECTIVE
• To design and implement 4-bit parallel adder.
• To observe the output of 4-bit Parallel adder.
• To design an Accumulator circuit.

COMPONENTS REQUIRED
• IC 7483 (4-bit parallel adder).
• Digital Trainer Kit
• Connecting wires
• Twizer

THEORY
Ripple Carry Adder is a combinational logic circuit. It is used for the purpose of adding two
n-bit binary numbers. It requires n full adders in its circuit for adding two n-bit binary
numbers. A 4-bit adder is a circuit which adds two 4-bits numbers, say, A and B. In addition,
a 4-bit adder will have another single-bit input which is added to the two numbers called
the carry-in (Cin). The output of the 4-bit adder is a 4-bit sum (S) and a carry-out (Cout) bit.

Using ripple carry adder, this addition is carried out as shown by the following logic diagram.

Block diagram of 4-bit Adder

Any two 4-bit binary numbers A3A2A1A0 and B3B2B1B0 are added as shown below.

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Pin Diagram of IC 7483

[Logic Diagram of IC 7483]

PRECAUTIONS
• Make the connections according to the IC pin diagram.
• The connections should be tight.
• The Vcc and ground should be applied carefully at the specified pin only.
PROCEDURE
1. Make the connections as per the logic diagram.
2. Connect +5v and ground according to pin configuration.
3. Apply diff combinations of inputs to the i/p terminals.
4. Note o/p for summation.
5. Verify the truth table.

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OBSERVATION TABLE of 4-bit Parallel Binary Adder

QUESTIONARIES
1. What do you understand by parallel adder?
2. What happens when an N-bit adder adds two numbers whose sum is greater than or
equal to2N?
3. Is Excess-3 code a weighted code or not? Ans. Excess-3 is not a weighted code.
4. What is IC no. of parallel adder?
5. What is the difference between Excess-3 & Natural BCD code?
6. What is the Excess-3 code for (396)10?
7. Can we obtain 1’s complement using parallel adder?
8. Can we obtain 2’s complement using parallel adder?
9. How many bits can be added using IC7483 parallel adder?
10. Can you obtain subtractor using parallel adder?

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AIM OF THE EXPERIMENT

Binary Multiplier: design and implement a circuit that multiplies 4-bit unsigned numbers to
produce 8-bitproduct.

OBJECTIVE
To extend the application of adder circuits to implement a multiplier.
HARDWARE REQUIRED
• IC 7408,
• IC 7483,
• Patch Cords
• IC Trainer Kit

THEORY
Multiplication is a very common arithmetic operation and under digital logic the same can
be performed using Digital Multiplier designing which is our aim. Digital Multiplier is a type
of combinational logic circuit which multiplies two numbers. The numbers are represented
in binary form. The two numbers are more specifically known as multiplicand and multiplier
and the result is known as a product. The multiplicand & multiplier can be of various bit size.
The product’s bit size depends on the bit size of the multiplicand & multiplier. The bit size
of the product is equal to the sum of the bit size of multiplier & multiplicand. Binary
multiplication method is same as decimal multiplication. Binary multiplication of more than
1-bit numbers contains 2 steps. The 1st step is single bit-wise multiplication known as partial
product and the 2nd step is adding all partial products into a single product. Partial products
or single bit products can be obtained by using AND gates. However, to add these partial
products we need full adders & half adders. The design becomes complex with the increase
in bit size of the multiplier.
Saying unsigned number just means that two numbers are positive and no negative number
has been considered i.e., no extra bit is reserved for representing the sign. So all the binary
bits represent the magnitude of the equivalent decimal number.
4×4 Bit Multiplier
This multiplier can multiply a binary number of 4-bit size & gives a product of 8-bit size
because the bit size of the product is equal to the sum of bit size of multiplier and
multiplicand. The maximum number it can calculate us 15 x 15 = 225. You can also evaluate
the number of bits from the maximum output range. Suppose multiplicand A3 A2 A1 A0 &
multiplier B3 B2 B1 B0 & product as P7 P6 P5 P4 P3 P2 P1 P0 for 4×4 multiplier.

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In 4×4 multiplier, there are 4 partial products and we need to add these partial products to
get the product of multiplier.
They can be added using 4-bit full adders or single bit adders (half-adder & full-adder). The
design using Single bit adders is very complicated compared to using 4-bit full adders. The
implementation of 4×4 multiplier using 4-bit full adders While A and B are two 4-bit numbers
consisting of A0-A3 and B0-B3 respectively the product is shown below.

As shown above that there is one to one topological correspondence with manual
multiplication. The same may be implemented as shown below.

Circuit Diagram of 4×4 Bit Multiplier

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If we want to display the final output on 7-segment displays, but since the output of the
multiplier is in binary, we have to convert it before we can display it. (We may do the same
using the Decoder which we have already discussed).
The chip diagram for the implementation is shown in the figure below.
Pin Diagram of IC 7483

PROCEDURE
• Make the connections according to the IC pin diagram.
• The connections should be tight.
• The Vcc and ground should be applied carefully at the specified pin only.
• Apply input to the circuit according to the circuit diagram.
• In case of gray to binary conversion, the inputs are given at respective pins and
outputs are taken for all the combinations and same for gray to binary conversion.
• In 7-segment display connect four switches to the four inputs of your decoder inputs
(D, C, B, and A) respectively& check the display for corresponding output.
• Switch on the trainer kit.
• Observe the output.
• Repeat steps for different input as per truth table.
• Verify the truth table.
• Connect the positive terminal of supply to pin 14 and pin 7 is to be grounded.
• Give input at corresponding pins & connect output pins to an output LED.
• Note the values of output for different combination of inputs & verify the logic table
for each circuit.

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CONCLUSION
The 4-bit multiplier was designed successfully and output was verified. The logic may be
applied for implementation of higher order multipliers.

QUESTIONNAIRE:
1. Design a 2-bit multiplier.
2. What is the maximum number that may result if you design a 3-bit multiplier?
3. How to convert from binary to BCD?
4. What is the difference between binary and BCD?
5. What is the difference between signed number and unsigned number?
6. Using 8 bits what is the range of signed number that can be represented?
7. Multiplier is combinational /Sequential? Why?
8. Can you extend the application for designing a divider circuit?

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AIM OF THE EXPERIMENT

Design, implement and test one bit and two-bit magnitude comparator.

OBJECTIVE
• To learn and understand the working of IC 7485 used for magnitude comparator.
• To realize One- & Two-Bit Comparator and verify the function table.
• To learn about various applications of comparator.

COMPONENTS REQUIRED
IC 7411, IC 7432, IC 7408, IC 7404, IC 7485, Patch Cords & IC Trainer Kit

THEORY
Magnitude Comparator is a type of Combinational logic circuit, which compares two signals
A and B and generates output depending on their values. There are three logical outputs,
which are A > B, A = B and A< B. IC 7485 is a high speed 4-bit Magnitude Comparator, which
compares two 4-bit words. The A and B input must be held appropriately for proper compare
operation. The logic applied here is we must check the MSB of the two numbers irrespective
of LSB. If one MSB is higher that number is higher. But if for both numbers MSB are equal
then we must check the next LSB. This process continues if no of bits increase for the two
numbers under comparison.
There are two main types of Digital Comparator available and these are
1. Identity Comparator – an Identity Comparator is a digital comparator that has only one
output terminal for when A = B either “HIGH” A = B = 1 or “LOW” A = B = 0
2. Magnitude Comparator – a Magnitude Comparator is a digital comparator which has
three output terminals, one each for equality, A = B greater than, A > B and less than A < B.
Digital or Binary Comparators are made up from standard AND, NOR and NOT gates that
compare the digital signals present at their input terminals and produce an output
depending upon the condition of those inputs.
TRUTH TABLE OF 1-BIT COMPARATOR
Input Output
A B Y1: A=B Y2: A<B Y3: A>B
0 0 1 0 0
0 1 0 1 0
1 0 0 0 1
1 1 1 0 0

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CIRCUIT DIAGRAM OF 1BIT COMPARATOR

TRUTH TABLE OF 2-BIT COMPARATOR

KMAP

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CIRCUIT DIAGRAM OF 2-BIT COMPARATOR

We can also design a two bit magnitude comparator using the chip configuration may be
drawn as shown below. The lower order comparators may be analyzed too considering zero
to the higher order bits.

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Pin diagram of IC 7485

PROCEDURE
• Connections are made as shown in the logic diagram using the pin details of the
gates.
• Connect + Vcc& GND to respective pins of each IC.
• Switch on the Trainer kit.
• Connect the A > B and A < B cascading inputs to logic 0 level and A = B input to logic
1 level.
• Connect the input bits to be compared to the toggle switches and outputs A > B, A =
B and A = B the LED‟s and verify the compare operation for different input
combinations.
CONCLUSION
The magnitude comparator was designed and the output was verified.
QUESTIONNAIRE
1. For 2-bit comparison draw the logic gate for A=B.
2. For 2-bit comparison draw the logic gate for A<B.
3. What do you mean by MSB?
4. Why MSB carries important role in making comparison.
5. Draw logic diagram for 3-bit comparator.
6. If A and B are 4-bit numbers applied to a 4-bit comparator then for no of
combinations A greater than B is …………...?
7. What’s the basic difference between subtractor and comparator?
8. Comparator circuit is Combinational/sequential? Why?

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AIM OF THE EXPERIMENT

Design of special type of counters (four-bit ring counter & Johnson counter) using JK flip-flops.

OBJECTIVE
 To learn about Ring Counter and its application.
 To learn about Johnson Counter and its application.

COMPONENTS REQUIRED
- Digital trainer kit
- Patch chords
- +5v power supply
- IC 7476
- IC 7495.

THEORY
RINGCOUNTER
The ring counter is a shift-register (cascaded connection of flip flops), in which the output of
last flip flop is connected to input of first flip flop. In ring counter if the output of any stage
is 1, then its reminder is 0. The Ring counters transfers the same output throughout the
circuit.

That means if the output of the first flip flop is 1, then this is transferred to its next stage i.e.
2nd flip flop. By transferring the output to its next stage, the output of first flip flop becomes
0. And this process continues for all the stages of a ring counter. If we use n flip flops in the
ring counter, the ‘1’ is circulated for every ‘n’ clock cycles.

A basic ring counter can be slightly modified to produce another type of shift register
counter called Johnson counter. Here complement of last output is connected back to the
not gate input and not gate output is connected back to serial input. A four bit Johnson
counter gives 8 state output.

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[Ring Counter Using J-K Flip-Flop]

[Pin Diagram Using Shift Register] [Truth Table]

PROCEDURE
- Initially a low clear (CLR) pulse is applied to all flip-flops. Hence FF-3, FF-2, FF-1 will be
reset but FF-0 will be set. So, outputs are: QD QC QB QA = 0001
- The clear terminal is made inactive by applying a high level to it. The clock signal is then
applied to all the flip-flops simultaneously. Note that all the flip-flops are negative edge
triggered
- On first negative going CLK edge: As soon as first falling edge of clock hits, only FF-1 will
be set Q0=J1=1. The FF-0 will reset because J0=Q3=0 and there is no change in the status
of FF-2 and FF-3. Hence after the first clock pulse the outputs are: QD QC QB QA = 0010
- On the second falling edge of clock: At the second falling edge of clock, only FF-2 will be
set as J2 = Q1 = 1. The FF-1 will reset since J1 = Q0 = 0. There is no change in status of
FF-3 and FF-0. So, after second clock pulse the outputs are, QD QC QB QA = 0100.
- Similarly after third clock pulse outputs are: QD QC QB QA = 1000
- After fourth pulse outputs are: QD QC QB QA = 0001

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[Timing Diagram of Ring Counter]

APPLICATIONS
• Ring counters are used to count the data in a continuous loop.
• They are also used to detect the various numbers values or various patterns within a
set of information, by connecting AND & OR logic gates to the ring counter circuits.
• 2 stage, 3 stage and 4 stage ring counters are used in frequency divider circuits as
divide by 2 and divide by 3 and divide by 4 circuits, respectively.
• The 3 stage Johnson counter is used as a 3-phase square wave generator which
produces 1200 phase shift.
• The 5 stage Johnson counter circuit is generally used as synchronous decade (BCD)
counter and also as divider circuit.
• The 2 stage Johnson counters are also known as “Quadrature oscillator” which is used
to produce 4 level individual outputs which are out of phase with 900 with each other.
This quadrature generator is used to produce 4 phase timing signals.

Johnson Counter (Twisted Pair Ring Counter)

In the ring counter the outputs of FF-3 were connected directly to inputs of FF-0 i.e., QD to
J0&QD to K0. Instead if the outputs are cross coupled to the inputs i.e. if QD is connected to
K0&QD’ is connected to J0 then the circuit is called as twisted ring counter or Johnson‘s
counter.

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[Johnson Counter Using J-K Flip-Flop]

[Pin Diagram Using Shift Register] [Truth Table]

PROCEDURE
- Initially a short negative going pulses is applied to the clear input of all the flip-flop. This
will reset all the flip-flops. Hence initially the outputs are QD QC QB QA=0000.
- But ̅̅̅̅
Q D = 1and since it is coupled to J0 it is also equal to 1. Hence, J0=1 and K0 =0 ……
initially.
On the first falling edge of clock pulse:
1) As soon as the first negative edge of clock arrives, FF-0 will be set Hence QA will
become 1.
2) But there is no change in the status of any other flip-flop.
3) Hence after the first negative going edge of clock the flip –flop outputs areQD QC
QB QA = 0001
On the second negative going clock edge:
1) ̅̅̅̅
Before the second negative going clock edge, QD=0 &Q D = 1, Hence J0=1and K0 =0.

Also, QA=1.Hence J1=1.

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2) Hence the second falling clock edge arrives, FF-1 continues to be in the set mode
̅̅̅̅
and FF-1 will now set. Hence Q1 will become 1 &Q A = 0.

3) There is no change in the status of any other FF.

4) Hence the second clock edge the outputs are QD QC QB QA= 0011.

- Similarly, after the third clock pulses, the outputs are QD QC QB QA=0111.
- And after the fourth clock pulses, the outputs are QD QC QB QA=1111.
- Hence as soon as the fifth negative going clock pulses strikes FF-0 will reset. But the
outputs of the other flip-flops will remain unchanged, So after the fifth clock, the outputs
are, QD QC QB QA= 1110.
- This operation will continue till we reach to all zero-output state QD QC QBQA=0000.

[Timing Diagram of Johnson Counter]

APPLICATIONS OF JOHNSON COUNTER:
• Johnson counter is used as a synchronous decade counter or divider circuit.
• It is used in hardware logic design to create complicated Finite states machine. ex: ASIC
and FPGA design.
• The 3 stage Johnson counter is used as a 3-phase square wave generator which
produces 1200 phase shift.
• It is used to divide the frequency of the clock signal by varying their feedback.

CONCLUSION
We have designed four-bit ring counter & Johnson counter using JK flip-flops and verified
the truth tables.

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QUESTIONNAIRE
1. In a 4-bit Johnson counter sequence; there are a total of how many states, or bit
patterns?
2. If a 10-bit ring counter has an initial state 1101000000, what is the state after the
second clock pulse?
3. How much storage capacity does each stage in a shift register represent?
4. Ring shift and Johnson counters are called what type of counters.
5. What is the difference between a shift-right register and a shift-left register?
6. What is the preset condition for a ring shift counter?
7. To design a8 bit ring counter how many ffs are required?
8. Draw the state diagram of a ring counter, where the initial data is 1000.
9. Draw the state diagram of a ring counter, where the initial data is 1000.
10. Design a 3-bit ring counter using D FF

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AIM OF THE EXPERIMENT:

Verilog/VHDL simulation and implementation of logic gates.

OBJECTIVE:
• To learn the software Xilinx ISE Simulator (VHDL), ORCAD (Verilog)
• To develop the coding skill to write a program (VHDL/Verilog) in dataflow modeling
style.
• Synthesize the program of different logic gates in frontend so that the RTL schematic
will be developed at the backend.
• Simulate the program to see the output as a waveform.
• Verify the truth table of the logic gates from the waveform.

SOFTWARE REQUIRED:
Xilinx ISE Simulator (VHDL), ORCAD (Verilog)

THEORY:
HARDWARE DESCRIPTION LANGUAGE (HDL)
A language used for describing a digital system like a network switch or a microprocessor
or a memory or a flip−flop. It means, by using a HDL we can describe any digital hardware
at any level. Designs, which are described in HDL are independent of technology, very easy
for designing and debugging, and are normally more useful than schematics, particularly for
large circuits.
There are now two industry standard hardware description languages, VHDL and Verilog
supported by IEEE.
• Verilog is easier to understand and use. For several years it has been the language of
choice for industrial applications that required both simulation and synthesis. It
lacks, however, constructs needed for system level specifications.
• VHDL is more complex, thus difficult to learn and use. However, it offers a lot more
flexibility of the coding styles and is suitable for handling very complex designs.
INTRODUCTION TO VHDL
VHDL stands for VHSIC (Very High-Speed Integrated Circuits) Hardware Description
Language. This was developed from an initiative by US. Dept. of Defense.

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• It is not case sensitive and a strongly typed language which needs to declare always
the type of every object that can have values such as signals, constants, variables,
etc.
• Every VHDL design description consists of at least one entity / architecture pair, or
one entity with multiple architectures. The entity section of the HDL design is used
to declare the I/O ports of the circuit, while the description code resides within
architecture portion.
• A system library IEEE library is used in case of VHDL and is included prior to the entity
declaration. This is accomplished by including the code "library ieee;" and "use
ieee.std_logic_1164.all;".
BASIC STRUCTURE OF VHDL
• Entity declaration
• An architecture body

ENTITY DECLARATION
• The entity declaration defines the NAME of the
entity and lists the input and output ports.
• The general form is as follows
entity NAME_OF_ENTITY is
port(signal names: mode type;
signal names: mode type;
signal names: mode type);
end NAME_OF_ENTITY;
• Where, The NAME_OF_ENTITY is a user-selected identifier.
THE ARCHITECTURE BODY:
• It specifies how the circuit operates and how it is implemented.
• The architecture body looks as follows
Architecture
Architecture name of NAME_OF_ENTITY is
-- Declarations
-- Components declarations
-- signal declarations
-- Constant declarations

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-- Function declarations
begin
-- Statements
:
endarchitecture_name;

INTRODUCTION TO VERILOG HDL:

Verilog HDL
Developed by Cadence Data systems and later transferred to a consortium called Open
Verilog International (OVI).
• It uses a hierarchical, functional unit-based design approach: – The whole design
consists of several smaller modules
• It is Case sensitive - keywords are lower case
• It uses pre-defined keywords, identifiers that define the language constructs.
• A module is the building block in Verilog.
• It is declared by the keyword module and is always terminated by the keyword
endmodule.
BASIC STRUCTURE OF VERILOG HDL
Modulemodule_name (port list);
port declaration syntax: <direction><data type><size><port name>
example:
1-bit input port: input wire op1;
16-bit output register: output reg [15:0] result;
Description of the functionality
example:
assign result = op1 + op2;
endmodule
PRECAUTION:
• Prevent harmful and unpractical way of coding.
• Introduce a common and clear appearance for Verilog/VHDL.
• Increase readability for reviewing purposes.
PROCEDURE:

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Create a new folder in any drive in your computer or system to save the program.
STEPS TO SIMULATE THE XILINX 14.7 SOFTWARE WITH VHDL LANGUAGE
1. Double click on the icon iSE Design Suite 14.7
• Go to File → New project
• It will display Create new project window. Give the project name.
• As example:-‘SIT’

2. Click on Next
• It will display New project Wizard window. Set the property, family, device,
package and language etc as shown.

3. Click on Next →Finish

4. Go to process window. Right click as shown and select New Source.

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5. Click on VHDL Module and give the file name

6. As example: Here file name is ‘OR_gate’

7. Click on Next.
• It will display New source wizard where you have to define the modules.
Change the architecture name as dataflow (since it is dataflow model). Give
inputs and output as given. Then click on Next →Finish

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8. It will open the program window where you have to write the program.

9. After writing the code you should save it.

10. Select implementation View.
11. Then click on OR_gate dataflow which is under SIT in design window.
12. After that go to process window and open synthesize-XST.
• Under synthesize you will find check syntax.
13. Double click on check syntax and a green tick mark will come just left side of check
syntax.

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14. Right Click on OR_gate_dataflow(OR_gate.vhd) which is under SIT project

→ New source

15. Select VHDL test bench.

16. Give file name (Here it is ORTEST given)
17. Then Next→Next→Finish
• It will open simulation program window.

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18. Write the program code as written for OR gate and delete the clock related lines as
well as the comment lines for your better understanding.
19. Select simulation view in design window.

20. Double click on simulate behavioral model which is in the process window and wait
for output.
21. Now you can see the simulated output in the simulation window.
• You can adjust’ Zoom to Full’ View and ‘zoom in’ in that simulated screen.

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22. This is the required simulated output for OR gate.

PROGRAM:
Below program is written in dataflow model by using the Boolean function.
VHDL CODE VERILOG CODE
1.OR GATE 1. OR gate
library ieee; module andgate (x, y, F);
use ieee.std_logic_1164.all; input x, y;
--------------------------------------
output F;
entity OR_gate is
assign F = x | y;
port ( x: in std_logic;
endmodule
y: in std_logic;
2.NOR gate
F: out std_logic);
module NOR_2gate (x, y, F);
end OR_gate;
--------------------------------------- input x, y;
architecture OR_dataflow of OR_gate is output F;
begin assign F = ~(x | y);
F <= x or y; endmodule
end OR_dataflow;
2. NOR gate
library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------
entity NOR_gate is
port( x: in std_logic;
y: in std_logic;
F: out std_logic);
end NOR_gate;
------------------------------------------
architecture dataflow of NOR_gate is
begin
-- compare to truth table
F <= x nor y;
end dataflow;

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TEST BENCH CODE FOR OR GATE in VHDL

stim_proc: process
begin
wait for 10 ns;
x<='0'; y<='0';
wait for 10 ns;
x<='0'; y<='1';
wait for 10 ns;
x<='1'; y<='0';
wait for 10 ns;
x<='1';y<='1';
wait for 10 ns;
end process; End;
SIMULATED OUTPUT OF OR GATE

TEST BENCH CODE FOR NOR GATE in VHDL

stim_proc: process
begin
wait for 10 ns;
x<='0'; y<='0';
wait for 10 ns;
x<='0'; y<='1';
wait for 10 ns;
x<='1'; y<='0';
wait for 10 ns;
x<='1'; y<='1';
wait for 10 ns;
end process;
end;

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SIMULATED OUTPUT OF NOR GATE

Likewise we can write the VHDL/Verilog program for AND,NAND, EX-OR, EX-NOR, Invert and
Buffer gates in dataflow modeling.

OBSERVATION:
The two major purposes of HDLs are logic simulation and synthesis.
• During simulation, inputs are applied to a module, and the outputs are checked to
verify that the module operates correctly.
• The test bench checks whether the output results are correct (only for simulation
and cannot be synthesized).
• A simulator interprets the HDL description and produces a readable output, such as
a timing diagram, that predicts how the hardware will behave before it is actually
fabricated.
• During synthesis, the textual description of a module is transformed into logic gates.
Circuit descriptions in HDL resemble code in a programming language.
CONCLUSION:
• After learn the software Xilinx ISE Simulator (VHDL), ORCAD (Verilog) we wrote
programs (VHDL/Verilog) in dataflow modeling style.
• Synthesized the programs of different logic gates in frontend and studied the RTL
schematic developed at the backend.
• Simulated the program to see the output as a waveform and verified the truth table
of the logic gates from the waveform.

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QUESTIONNAIRES
1. Write the correct syntax for entity declaration?
2. To write name of entity what are the rules to be followed.
3. Write a VHDL Code in dataflow model of a three input NAND gate?
4. In what aspect, HDLs differ from other computer programming languages?
5. Why do we need concurrent processing for describing digital systems in HDLs?
6. What are the differences between assignments in initial and always constructs?
7. What are the different approaches of connecting ports in a hierarchical design?
8. What do VHDL stand for?
9. A VARIABLE y is declared of STD_LOGIC_VECTOR type of 4 bits, if you want to
assign 1001 to “y”, then what is the write assignment statement?
10. ______ operator is unary as well as binary operator.

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AIM OF THE EXPERIMENT:

Verilog/VHDL simulation and implementation of different combinational circuits in dataflow
and behavioral modeling.
OBJECTIVE:
• To develop the coding skill to write a program (VHDL/Verilog) in dataflow and
behavioral modeling style.
• Synthesize the program of Half Adder, Full Adder, half subtractor, full subtractor,
Decoder, Multiplexer in frontend so that the RTL schematic can be checked at the
backend.
• Run the simulation to see the output as a waveform.
• Verify the truth table of all the circuits from the waveform.

SOFTWARE REQUIRED:
Xilinx ISE Simulator (VHDL), ORCAD (Verilog).

THEORY:
In VHDL the modeling of architecture body can be described in any one (or a combination)
of the following modeling techniques.
• DATAFLOW MODEL:
➢ The flow of data through the entity is expressed using concurrent signal
assignment statements.
➢ This makes the concurrent signal assignment statements even triggered
which implies that any concurrent is executed only when any event occurs on
the signal that are used in the expression of concurrent signal assignment
statement.
• BEHAVIORAL MODEL:
➢ In this the behavior of the entity is expressed using statements which are
executed sequentially. Generally, process statement is used.
➢ One important aspect of behavioral code is that it is not limited to sequential
logic. Indeed, with it, we can build sequential circuits as well as
combinational circuits.
➢ The behavioral statements are IF, WAIT, CASE, and LOOP. VARIABLES are also
restricted and they are supposed to be used in sequential code only.

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Example: design of flip-flop, register, counter.

✓ Requirement of sensitivity list.
✓ Declarative part
✓ Statement part
• STRUCTURAL MODEL
➢ Sub-components are used to design higher models.
Eg.–Design of FA using HA.
IN VERILOG:
A module can be described in any one (or a combination) of the following modeling
techniques.
1. Gate-level modeling using instantiation of primitive gates and user defined modules.
➢ This describes the circuit by specifying the gates and how they are connected with
each other.
2. Dataflow modeling using continuous assignment statements with the keyword assign.
➢ This is mostly used for describing combinational circuits.
3. Behavioral modeling using procedural assignment statements with keyword always.
➢ This is used to describe digital systems at a higher level of abstraction
PROCEDURE
Step 1: Start the Xilinx project navigator by Stat->programs->Xilinx ISE->Project Navigator
Step 2: In the project navigator window click on new project->give file name->next.
Step 3: In the projector window right click on project name-> new source->VHDL module-
>give file name->define ports->finish.
Step 4: Write the VHDL code for any gate or circuit.
Step 5: Check Syntax and remove error if present.
Step 6: Write the VHDL test bench code for any gate or circuit.
Step 7: Simulate design.
Step 8: In the project navigator window click on simulation->click on simulate behavioral
model.
Step 9: Give inputs by right click
Step 10: Run simulation.
Step 11: Analyze the waveform with reference to truth table.

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PROGRAM
VHDL Code in Dataflow Modeling Verilog Code in Dataflow Modeling
1.Half Adder 1.Half Adder
library ieee; modulehalf_adder (input a, b, output s, c);
use ieee.std_logic_ 1164.all; assign s = a ^ b;
use ieee.std_logic_unsigned.all;
assign c = a & b;
-------------------------------------------------
entity half_adder is endmodule
port (a: in std_logic;
b: in std_logic;
s: out std_logic;
c: out std_logic);
end half_adder;
architecture dataflow of half_adder is
begin
s<= a xor b;
c<= a and b;
end dataflow;
2.Full Adder 2.Full Adder
library ieee; module fulladder( input a, input b, input
use ieee.std_logic_ 1164.all; cin,outputsum,output carry );
use ieee.std_logic_unsigned.all; assign x=a ^ b;
------------------------------------------------- assign sum=a^b^cin;
entity full_adder is assign y=(a^b) &cin;
port (a,b,c: in std_logic; assign z=a & b;
s,cout: out std_logic); assign carry= y | z;
end full_adder; endmodule
-------------------------------------------------
architecture dataflow of full_adder is
begin
s<= a xor b xor c;
cout<= (a and b) or (a and c) or (b and
c);
end dataflow;
3. Half Subtractor 3. Half Subtractor
library ieee; module Half_Subtractor_2(output D, B, inp
use ieee.std_logic_1164.all; ut X, Y);
entity half_sub is assign D = X ^ Y;
port(a,c:in bit; diff,borrow:out bit); assign B = ~X & Y;
end half_sub; endmodule
---------------------------------------

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architecture data of half_sub is

begin
diff<= a xor c;
borrow<= (a and (not c));
end data;
4. Full Subtractor 4. Full Subtractor
library ieee; module Full_Subtractor_3(output D, B,
use ieee.std_logic_ 1164.all; input X, Y, Z);
use ieee.std_logic_unsigned.all; assign D = X ^ Y ^ Z;
-- ------------------------------------------ assign B = ~X & (Y^Z) | Y & Z;
entity full_subtractor is
endmodule
port (a,b,c: in std_logic;
diff,borrow: out std_logic);
end full_adder;
----------------------------------------------------
architecture dataflow of full_subtractor is
begin
diff<= a xor b xor c;
borrow<= (a and b) or (a and c) or (b
and c);
end dataflow;
5. 4:1 Multiplexer 5 . 4:1 Multiplexer
library ieee; module m41 ( input a,
use ieee.std_logic_ 1164.all; input b,
use ieee.std_logic_unsigned.all; input c,
use ieee.std_logic_arith.all; input d,
---------------------------------------------------- input s0, s1,
entity mux4to1 is output out);
Port ( i : in std_logic_ vector(03 assign out = s1 ? (s0 ? d : c) : (s0 ? b : a);
downto 00); endmodule
s : in std_logic_ vector (01 downto
00);
y : out std_logic);
end mux4to1;
-------------------------------------------------
architecture dataflow of mux4to1 is
begin
y<=((not s(0)and not s(1)and
i(0))or(not s(0)and s(1)and
i(1))or(s(0)and not s(1)and
i(2))or(s(0)and s(1)and i(3)));
end dataflow;

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6. 2-to-4-line Decoder 6. 2-to-4-line Decoder

library ieee;
use ieee.std_logic_ 1164.all; module decoder_2_4(a,b,w,x,y,z);
use ieee.std_logic_unsigned.all; output w,x,y,z;
use ieee.std_logic_arith.all; input a,b;
------------------------------------------------------ assign w = (~a) & (~b);
entity decoder2_4line is assign x = (~a) & b;
Port ( a,b : in std_logic; assign y = a & (~b);
d : out std_logic_ vector (03 downto 00)); assign z = a & b;
end decoder2_4line; endmodule
------------------------------------------------------
architecture dataflow of decoder2_4line is
begin
d(0)<=(not a and not b);
d(1)<=(not a and b);
d(2)<=(a and not b);
d(3)<=(a and b);
end dataflow;

VHDL Code in Behavioral Modeling Verilog Code in Behavioral Modeling

1. Half Adder 1. Half Adder
libraryieee; module halfadder4(input x, y, outputreg s,
use ieee.std_logic_1164.all; c);
use ieee.std_logic_unsigned.all; always@(x or y)
use ieee.std_logic_arith.all;
begin
entity halfadder2 is
if (x == 0&& y == 0)
port(a, b : in bit;
begin
s, c : out bit);
s = 0;
end halfadder2;
-------------------------------------------------- c = 0;
architecture behavioral of halfadder2 is end
begin elseif (x == 1&& y == 1)
process(a,b) begin
begin s = 0;
if a & b = "00" then
c = 1;
s <= '0'; c<= '0';
elsif a & b = "01" or a & b = "10" then end
s <= '1'; c <= '0'; else
else begin
s <= '0'; c <= '1';
s = 1;
end if;
end process; c = 0;
end behavioral; end

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2. Full Adder 2. Full Adder

libraryieee; full_adder( A, B, Cin, S, Cout);
use ieee.std_logic_ 1164.all; input wire A, B, Cin;
use ieee.std_logic_unsigned.all; outputreg S, Cout;
useieee.std_logic_arith.all; always @(A or B or Cin)
------------------------------------------------ begin
entity FULLADDER_BEHAVIORAL is
S = A ^ B ^ Cin;
Port ( A : in std_logic_ vector (2
Cout = A&B | (A^B) &Cin;
downto 0);
O : out std_logic_ vector (1 downto 0)); end
end FULLADDER_BEHAVIORAL; endmodule
----------------------------------------------
architecture Behavioral of
FULLADDER_BEHAVIORAL is
begin
process (A)
begin
if (A = "001" or A = "010" or A = "100"
or A = "111") then
O(1) <= '1';
else
O(1) < = '0';
end if;
if (A = "011" or A = "101" or A = "110"
or A = "111") then
O(0) <= '1';
else
O(0) <= '0';
end if;
end process;
end Behavioral;
3. Half subtractor 3. Half Subtractor
library ieee; modulehalfsubtbeh(diff,borrow,a, b);
use ieee.std_logic_ 1164.all; outputdiff,borrow;
use ieee.std_logic_unsigned.all; inputa,b;
useieee.std_logic_arith.all; regdiff,borrow;
------------------------------------------- always @(a,b)
entity HS is
diff = a ^ b;
Port (A,B : instd_logic ;

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 EXPERIMENT-19

Diff , Borrow: out std_logic); borrow=(~a&b);

end HS; endmodule
-------------------------------------
architecture Behavioral of HS is
begin
process(A,B)
begin
if(A='0' and B='0')THEN
Diff<='0'; Borrow<='0';
elsif(A='0' and B='1')THEN
Diff<='1'; Borrow<='1';
elsif(A='1' and B='0') THEN
Diff<='1'; Borrow<='0';
elsif(A='1' and B='1') THEN
Diff<='0'; Borrow<='0';
else
Diff<='Z'; Borrow<='Z';
end if; end process; end Behavioral;
4. Full Subtractor 4. Full Subtractor
Library ieee; module p11(a,b,c ,diff ,borrow );
use ieee.std_logic_ 1164.all; output diff, borrow;
use ieee.std_logic_unsigned.all; input a,b,c;
use ieee.std_logic_arith.all; reg diff, borrow;
------------------------------------------------------ always@(a,b,c)
entity FS is
diff = a ^ b ^ c;
Port (A,B,C : instd_logic ;
borrow = ((~a) & b) | (b & c) | (c & (~a));
Diff , Borrow: out std_logic);
endmodule
end FS;
----------------------------------------------------
architecture Behavioral of FS is
begin
process(A,B,C)
begin
if (A='0' and B='0' and C='0') THEN
Diff<='0';Borrow<='0';
elsif(A='0' and B='0' and C='1')THEN
Diff<='1'; Borrow<='1';
elsif(A='0' and B='1' and C='0') THEN

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Diff<='1'; Borrow<='1';
elsif(A='0' and B='1' and C='1') THEN
Diff<='0'; Borrow<='1';
elsif(A='1' and B='0' and C='0') THEN
Diff<='0'; Borrow<='0';
elsif(A='1' and B='0' and C='1') THEN
Diff<='0'; Borrow<='0';
elsif(A='1' and B='1' and C='0') THEN
Diff<='0'; Borrow<='0';
elsif(A='1' and B='1' and C='1') THEN
Diff<='1';Borrow<='1';
else
Diff<='Z'; Borrow<='Z';
end if; end process; end Behavioral;
5. 4*1 Multiplexer 5. 4*1 Multiplexer
libraryieee; module m41 ( a, b, c, d, s0, s1, out);
use ieee.std_logic_ 1164.all; input wire a, b, c, d;
use ieee.std_logic_unsigned.all; input wire s0, s1;
useieee.std_logic_arith.all; outputreg out;
entity MUX_4*1is always @ (a or b or c or d or s0, s1)
Port ( S : in std_logic _vector(1 begin
downto 0); case (s0 | s1)
I : in std_logic _vector (3 2'b00 : out <= a;
downto 0); 2'b01 : out <= b;
Y : out std_logic); 2'b10 : out <= c;
end MUX_4*1; 2'b11 : out <= d;
----------------------------------------------------- endcase
architecture Behavioral of MUX_SOURCE is
end
begin
process (S,I) endmodule
begin
if (S <= "00") then
Y <= I(0);
elsif (S <= "01") then
Y <= I(1);
elsif (S <= "10") then
Y <= I(2);
else
Y <= I(3);
end if; endprocess;end behavioral;

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6. 2-to-4-line Decoder 6.2-to-4-line Decoder

library ieee; module decoder2_4 ( din ,dout );
use ieee.std_logic_ 1164.all; output [3:0] dout ;
use ieee.std_logic_unsigned.all; reg [3:0] dout ;
use ieee.std_logic_arith.all; input [1:0] din ;
--------------------------------------------------- wire [1:0] din ;
entity decoder is
always @ (din) begin
Port ( s : in in std_logic _vector (1
downto 0); if (din==0)
y : out in std_logic _vector (3 downto dout = 8;
0)); else if (din==1)
end decoder;
dout = 4;
------------------------------------------------------------
architecture Behavioral of decoder is else if (din==2)
begin dout = 2;
process(s) else
begin dout = 1;
case(s) is end
when "00"=>y<="0001"; endmodule
when "01"=>y<="0010" ;
when "10"=>y<="0100" ;
when "11"=>y<="1000" ;
when others=>null;
end case; end process;
end Behavioral;

Simulated output of Half Adder

Simulated output of Full Adder

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Simulated output of half subtractor

Simulated output of full subtractor

Simulated output of 4:1 Multiplexer

SIMULATED OUTPUT of 2:4 DECODER

CONCLUSION:
After learning the coding skill to write a program (VHDL/Verilog) in dataflow and behavioral
modeling style we Synthesized the program of Half Adder, Full Adder, half subtractor, Full
subtractor, Decoder, Multiplexer in frontend so that the RTL schematic can be checked at
the backend. Also run the simulation to see the output as a waveform and truth table is
verified.

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QUESTIONAIRES
1. What is the type of result of MOD operator?
2. The operators like =, /=, <, >, >= are called _________
3. The most basic form of behavioral modeling in VHDL is _______
4. The signal assignment is considered as a ________
5. The sequential assignment statement is activated, whenever ________
6. Who developed the Verilog?
7. ______ operator usually comes before the operand.
8. What is the difference between dataflow and behavioral modeling in Verilog?
9. What is test bench?
10. What are the different levels of design abstraction at physical design?

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AIM OF THE EXPERIMENT:

Verilog/VHDL simulation and implementation of full adder,8-bit adder in structural
modeling.

OBJECTIVE:
• To develop the coding skill to write a program (VHDL/Verilog) in structural modeling
style.
• Synthesize the program of full adder,8-bit adder in frontend so that the RTL
schematic can be checked at the backend.
• Run the simulation to see the output as a waveform.

SOFTWARE REQUIRED:
Xilinx ISE Simulator (VHDL), ORCAD (Verilog).
THEORY:
A Full adder is a combinational circuit that adds two one-bit numbers along with a carry from
the lower stage and produces the sum and the carry as output.

This 1-bit FA can be cascaded to perform multi-bit addition. The block diagram shown below
gives details of multibit addition. To design a 8-bit adder we need 8 FAs.

N-Bit Parallel Adder

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HIERARCHICAL DESCRIPTION OF A DESIGN

• There are two basic types of design methodologies.
• Top down: In top-down design, the top-level block is defined and then sub-
blocks necessary to build the top-level block are identified.
• Bottom up: Here the building blocks are first identified and then combine to
build the top-level block.
• In a top-down design, a 4-bit binary adder is defined as top-level block with 4 full
adder blocks. Then we describe two half-adders that are required to create the full
adder.
• In a bottom-up design, the half-adder is defined, then the full adder is constructed
and the 4-bit adder is built from the full adders.
To design a circuit by writing a code in structural modeling we need to look at the
following points.
• Structural description shows how components of a circuit are put together
– similar to a schematic capture approach to designing a circuit
– It is to combine smaller blocks or predefined components into a larger circuit
by describing the way that the blocks interact
• The structural method is similar to a block diagram
– smaller components are used to make a circuit without knowing what is
happening in the block.
In structural model approach we use port map statement to achieve the structural
model (components instantiations). The following example of FA shows how to write the
program to incorporate multiple components in the design of a more complex circuit. In
order to simulate the design, a simple test bench code must be written to apply a sequence
of inputs (Stimulators) to the circuit being tested (UUT). The output of the test bench and
UUT interaction can be observed in the simulation waveform window.
Signals are used to connect the design components and must carry the information between
current statements of the design.

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PROGRAM FOR FULL ADDER

VHDL Code in structural Modeling Verilog Code in structural Modeling
Code for FULL ADDER module Full_Adder (input a, b, c, output
library IEEE; carry, sum);
use IEEE.STD_LOGIC_1164.ALL; wire x1, x2, x3;
entity fulladder1 is // Instantiate two Half Adders: HA1, HA2
Port ( a,b,c : in STD_LOGIC; // The ports are matched by position
sum,carry : out STD_LOGIC); Half_Adder HA1 (a, b, x1, x2);
end fulladder1; Half_Adder HA2 (x2, c, x3, sum);
architecture structural of fulladder1 is or #2 (carry, x1, x3);
component mhalf is endmodule
Port ( a,b:instd_logic ; module Half_Adder(input a, b, output cout,
sum,carry:outstd_logic); sum);
end component; and #2 (cout, a, b);
component mor is xor #3 (sum, a, b);
Port(a,b: in std_logic ; endmodule
c : out std_logic);
end component;
signal x1,x2,x3:std_logic ;
begin
U1:mhalf port map(a,b,x1,x2);
U2:mhalf port map(c,x1,sum,x3);
U3:mor port map(x3,x2,carry);
end structural;
HALF Adder as a component
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mhalf is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end mhalf;
architecture dataflow of mhalf is
begin
sum<= a xor b;
carry<= a and b;
end dataflow;

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Orgate as a component
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mor is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end mor;
architecture dataflow of mor is
begin
c<=a or b;
end dataflow;

SIMULATED OU PUT OF FULL ADDER

Program for 8 bit Adder using ‘8’ full adders

VHDL Code in structural Modeling Verilog Code in structural Modeling
Code for 8 bit Adder Code for 8 bit Adder
library IEEE; module ripplemod(a, b, cin, sum, cout);
use IEEE.STD_LOGIC_1164.ALL; input [07:0] a;
entity adder8 is input [07:0] b;
Port ( Cin : in STD_LOGIC; input cin;
A : in STD_LOGIC_VECTOR (7 downto 0); output [7:0]sum;
B : in STD_LOGIC_VECTOR (7 downto 0); output cout;
S : out STD_LOGIC_VECTOR (7 downto 0); wire[6:0] c;
Cout : out STD_LOGIC); // instantiating 8 1-bit full adders in Verilog
end adder8; fulladd a1(a[0],b[0],cin,sum[0],c[0]);
architecture structural of adder8 is fulladd a2(a[1],b[1],c[0],sum[1],c[1]);
signal c1,c2,c3,c4,c5,c6,c7:std_logic; fulladd a3(a[2],b[2],c[1],sum[2],c[2]);
component fulladd is fulladd a4(a[3],b[3],c[2],sum[3],c[3]);

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 EXPERIMENT-20

port(Cin,x,y: in std_logic; fulladd a5(a[4],b[4],c[3],sum[4],c[4]);

s,Cout: outstd_logic); fulladd a6(a[5],b[5],c[4],sum[5],c[5]);
end component; fulladd a7(a[6],b[6],c[5],sum[6],c[6]);
begin fulladd a8(a[7],b[7],c[6],sum[7],cout);
stage0: fulladd port map endmodule
(Cin,A(0),B(0),S(0),c1); Full adder as a module in 8 bit adder
stage1: fulladd port map module fulladd(a, b, cin, sum, cout);
(c1,A(1),B(1),S(1),c2); input a;
stage2: fulladd port map input b;
(c2,A(2),B(2),S(2),c3); input cin;
stage3: fulladd port map output sum;
(c3,A(3),B(3),S(3),c4); output cout;
stage4: fulladd port map assign sum=(a^b^cin);
(c4,A(4),B(4),S(4),c5); assign cout=((a&b)|(b&cin)|(a&cin));
stage5: fulladd port map endmodule
(c5,A(5),B(5),S(5),c6);
stage6: fulladd port map
(c6,A(6),B(6),S(6),c7);
stage7: fulladd port map
(c7,A(7),B(7),S(7),Cout);
end structural;
Component for full adder using in 8bit
adder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladd is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
Cin : in STD_LOGIC;
s : out STD_LOGIC;
Cout : out STD_LOGIC);
end fulladd;
architecture dataflow of fulladd is
begin
s <= x xor y xorCin;
Cout<=(x and y)or(Cin and x)or(Cin and y);
end dataflow;

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TESTBENCH CODE FOR 8 BIT ADDER

In VHDL In Verilog
stim_proc: process module rippleadder_b;
begin reg [7:0] a;
wait for 10 ns; reg [7:0] b;
A<="00011001"; reg cin;
B<="01101011"; wire [7:0] sum;
Cin<='0'; wire cout;
wait for 10 ns; ripplemoduut
A<="10111001"; (.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout) );
B<="01101011"; initial begin
Cin<='1'; #10 a=8’b00000001;b=8’b00000001;cin=1’b0;
wait for 10 ns; #10 a=8’b00000001;b=8’b00000001;cin=1’b1;
A<="00111001"; #10 a=8’b00000010;b=8’b00000011;cin=1’b0;
B<="11101011"; #10 a=8’b10000001;b=8’b10000001;cin=1’b0;
Cin<='0'; #10 a=8’b00011001;b=8’b00110001;cin=1’b0;
wait for 10 ns; #10 a=8’b00000011;b=8’b00000011;cin=1’b1;
A<="00011001"; #10 a=8’b11111111;b=8’b00000001;cin=1’b0;
B<="01111011"; #10 a=8’b11111111;b=8’b00000000;cin=1’b1;
Cin<='0'; #10 a=8’b11111111;b=8’b11111111;cin=1’b0;
wait for 10 ns; #10 $stop;
A<="01011001"; end
B<="01101011"; endmodule
Cin<='1';
wait for 10 ns;
end process;
END;

SIMULATED OU PUT OF 8-BIT RIPPLE CARRY ADDER

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CONCLUSION
We learn the coding skill to write a program (VHDL/Verilog) in structural modeling style
and synthesize the program of full adder,8-bit adder in frontend so that the RTL schematic
can be checked at the backend. Also run the simulation to see the output as a waveform.

QUESTIONAIRES
1. What is the basic unit of structural modeling?
2. What do you mean by component instantiation?

3. The structural model is similar to___________

4. Syntax for component declaration?

5. In which part of the VHDL code, components must be declared?

6. How many ways are there in VHDL to map the components and what are they?

7. It is not necessary that the order of the arguments in PORT MAP is taken as the
order in which ports are declared.
8. How to declare a 2 input OR gate in the structural modeling?
9. What is the correct syntax for mapping a GENERIC parameter in structural
modeling?
10. It is possible to use a GENERIC parameter as a separate component.

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AIM OF THE EXPERIMENT

Verilog/VHDL simulation and implementation of SR-FF, D-FF, JK-FF, T-FF in behavioral
modeling.

OBJECTIVE
• To develop the coding skill to write a program (VHDL/Verilog) in behavioral modeling
style.
• Synthesize the program of SR-FF, D-FF, JK-FF, T-FF in behavioral modeling in frontend
so that the RTL schematic can be checked at the backend.
• Run the simulation to see the output as a waveform.

SOFTWARE REQUIRED
Xilinx ISE Simulator (VHDL)/ORCAD(Verilog)

THEORY
A flip flop is an electronic circuit with two stable states and hence they are bistable
multivibrators. The two stable states are High (logic 1) and Low (logic 0). The term flip flop
is used as they can switch between the states under the influence of a control signal (clock
or enable) i.e. they can ‘flip’ to one state and ‘flop’ back to other state that can be used to
store binary data. Flip – flops are edge sensitive or edge triggered devices i.e. they are
sensitive to the transition rather than the duration or width of the clock signal. The stored
data can be changed by applying varying inputs. Flip-flops are fundamental building blocks
of digital electronics systems used in computers, communications, and many other types of
systems. It is the basic storage element in sequential logic. Each flip flop can store one bit of
data. These are also called as sequential logic circuits.

Some of the most common flip flops are SR lip flop (Set – Reset), D Flip – flop (Data or Delay),
JK Flip – flop and T Flip – flop.

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PROGRAM
VHDL Code in behavioral modeling Verilog Code in behavioral modeling
1. SR FlipFlop 1. SR FlipFlop
library IEEE; module srff_behave(s,r,clk, q, qbar);
use IEEE.STD_LOGIC_1164.ALL; input s,r,clk;
entity SRFF is output reg q, qbar;
Port ( S,R,CLK : in STD_LOGIC; always@(posedgeclk)
Q,QBAR : inout STD_LOGIC); begin
end SRFF; if(s == 1)
architecture Behavioral of SRFF is begin
begin q = 1;
PROCESS(CLK) qbar = 0;
begin end
if (CLK='1' AND CLK'EVENT ) then else if(r == 1)
if (S='0' AND R='1') then begin
Q<='0'; q = 0;
QBAR<= '1'; qbar =1;
elsif (S='0' AND R='0') then end
Q<=Q; else if(s == 0 & r == 0)
QBAR<= not (Q); begin
elsif (S='1' AND R='0') then q <= q;
Q<='1'; qbar<= qbar
QBAR<= '0'; end
else end
Q<='Z'; endmodule
QBAR<= 'Z'; 2. D FlipFlop
end if;end if; module dff_behavioral(d,clk,clear,q,qbar);
end PROCESS; input d, clk, clear;
end Behavioral; output reg q, qbar;
always@(posedgeclk)
2. D FlipFlop begin
library IEEE; if(clear== 1)
use IEEE.STD_LOGIC_1164.ALL; q <= 0;
entity DFLIPFLOP is qbar<= 1;
Port ( D,clk : in STD_LOGIC; else
Q : out STD_LOGIC); q <= d;
end DFLIPFLOP; qbar= !d;

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 EXPERIMENT-21

architecture Behavioral of DFLIPFLOP is end

begin endmodule
process(clk, D) JK Flipflop
begin module JK_FF (J,K,CLK,Q,Qnot);
if (clk'event AND clk='1' ) then outputQ,Qnot;
Q<=D; input J,K,CLK;
end if; reg Q;
end process; assignQnot = ~ Q ;
end Behavioral; always@(posedge CLK)
JK FF case({J,K})
library IEEE; 2'b00: Q = Q;
use IEEE.STD_LOGIC_1164.ALL; 2'b01: Q = 1'b0;
use IEEE.NUMERIC_STD.ALL; 2'b10: Q = 1'b1;
entity JKFF is 2'b11: Q = ~ Q;
Port ( j,k,clk : in STD_LOGIC; endcase
q,qb : out STD_LOGIC); endmodule
end JKFF; T Fllipflop
architecture Behavioral of JKFF is module mytff(t,q,qb,clk);
signal tmp:std_logic:='0'; input t,clk;
begin output q,qb;
PROCESS(clk) reg q,qb;
begin initial q=0;
if (CLK='1' AND CLK'EVENT) then
if (j='0' and k='0') then always@(posedgeclk)
tmp<=tmp; begin
elsif (j='0' and k='1') then if (t==1)
tmp<='0'; begin
elsif (j='1' and k='0') then q=~q;
tmp<='1'; end
else else
tmp<=not(tmp); begin
end if; q=q;
end if; end
end PROCESS; qb=~q;
q<=tmp; end
qb<=NOT(tmp); endmodule
end Behavioral;

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 EXPERIMENT-21

T Flipflop:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Tff is
Port ( t : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC;
qn : out STD_LOGIC);
end Tff;
architecture Behavioral of Tff is
signal tmp:std_logic:='0';
begin
PROCESS(clk)
begin
if (CLK='1' AND CLK'EVENT) then
if (t='0') then
tmp<=tmp;
elsif t='1' then
tmp<=not(tmp);
end if;
end if;
end PROCESS;
q<=tmp;
qn<=NOT(tmp);
end Behavioral;

TEST BENCH CODE:

T Flipflop in VHDL T Flipflop in Verilog
ENTITY tff_tb IS TEST BENCH :
END tff_tb; `timescale 1ns/1ns
ARCHITECTURE behavior OF tff_tb IS module tff (t,clk,q,qb);
-- Component Declaration for the Unit input t,clk;
Under Test (UUT) output q,qb;
COMPONENT Tff reg q, qb;
PORT( initial
t : IN std_logic; begin
clk : IN std_logic; q=0; q=1;
q : OUT std_logic; end
qn : OUT std_logic always@(posedge (clk))

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 EXPERIMENT-21

); begin
END COMPONENT; if(t==0)
--Inputs q=q;
signal t :std_logic := '0'; else
signal clk :std_logic := '0'; q=qb;
--Outputs qb=~q;
signal q :std_logic; end
signal qn :std_logic; endmodule
-- Clock period definitions `timescale 1ns/1ns
constant clk_period : time := 100 ns; module tff_tb;
BEGIN reg a,b;
-- Instantiate the Unit Under Test wire y,yb;
(UUT) tff out(.t(a), .clk(b),.q(y),.qb(yb));
uut: Tff PORT MAP ( initial
t => t, begin
clk =>clk, a=0; b=0; #100;
q => q, b=1; #100;
qn =>qn a=1; b=0; #100;
); b=1; #100;
-- Clock process definitions end
clk_process :process endmodule
begin
clk<= '0';
wait for clk_period/2;
clk<= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
--wait for 100 ns;
wait for clk_period*1;
-- insert stimulus here
t<='0';
wait for 100 ns;
t<='1';
wait for 100 ns;
end process;
END;

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SIMULATED OUTPUT OF SR FLIPFLOP

SIMULATED OUTPUT OF D FLIPFLOP SIMULATED OUTPUT OF JK FLIPFLOP

SIMULATED OUTPUT OF T FLIPFLOP

CONCLUSION

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We have developed the code (VHDL/Verilog) in behavioral modeling style and synthesized
the program of SR-FF, D-FF, JK-FF, T-FF in frontend so that the RTL schematic can be checked
at the backend. Also run the simulation to see the output as a waveform.

QUESTIONAIRES
1. What is the basic unit of structural modeling?

2. What do you mean by component instantiation?

3. The structural model is similar to___________

4. Syntax for component declaration?

5. In which part of the VHDL code, components must be declared?

6. How many ways are there in VHDL to map the components and what are they?
7. It is not necessary that the order of the arguments in PORT MAP is taken as the
order in which ports are declared.
8. Draw the truth table of SR FF.
9. Write the excitation table of SR FF?
10. Write the characteristic equation of D ff?
11. Why DFF is called Delay FF?
12. Why DFF is called transparent FF?
13. If j=K=0 what will be the behavior of output?
14. Why TFF is called Toggle FF?
15. Differentiate between negative and positive edge trigger.
16. Differentiate between edge trigger and level trigger.

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 APPENDIX

Appendix-1
IC 7400 specifications:
• The voltage supply is 5 V.
• Propagation delay for each gate will be 10 ns.
• Maximum toggle speed is 25 MHz.
• Power utilization for each gate is 10 mW.
• Independent 2-i/p NAND Gates- 4.
• The output can be interfaced with TTL, NMOS, CMOS.
• The range of operating voltage will be large.
• Operating conditions are extensive.
• Not suitable for new designs which use 74LS00.
• Using 7400 family-based integrated circuits, an engineer can design flip-flops (FFs),
counters, buffers, and logic gates in different packages, and these can be connected
as preferred to solve an exact problem.
IC 7402 specifications:
• Operating voltage range: +4.75 to +5.25V
• Maximum supply voltage:7V
• Maximum current allowed to draw through each gate output: 8mA
• TTL outputs
• Low power consumption
• Maximum ESD: 3.5KV
• Typical Rise Time: 15ns
• Typical Fall Time: 15ns
• Operating temperature:0°C to 70°C
• Storage Temperature: -65°C to 150°C
IC 7404 specifications:
• Supply voltage range: +4.75V to +5.25V
• Maximum supply voltage: +7V
• Maximum current allowed to draw through each gate output: 8mA
• Totally lead free
• TTL outputs
• Maximum Rise Time: 15ns
• Maximum Fall Time: 15ns
• Operating temperature:0°C to 70 °C
IC 7408 specifications:
• Operating voltage range: +4.75 to +5.25V
• Recommended operating voltage: +5V
• Maximum supply voltage:7V
• Maximum current allowed to draw through each gate output: 8mA
• TTL outputs

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 APPENDIX

• Low power consumption

• Typical Rise Time: 18ns
• Typical Fall Time: 18ns
• Operating temperature:0°C to 70°C
• Storage Temperature: -65°C to 150°C
IC 7486 specifications:
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2 V to 6V Operating Range
• Low Noise: VOLP = 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
IC 7486 specifications:
• 4 OR gates in a 14-Pin DIP Package
• Outputs Directly Interface to CMOS, NMOS and TTL
• Large Operating Voltage Range
• Wide Operating Conditions
• CMOS low power consumption
• Schmitt Trigger Action at All Inputs
• Voltage Rating: 2.0 to 6.0V
• Temperature Rating: 0 to 70Deg C

IC 7410 specifications:
• 3 input NAND Gates
• Large operating voltage range.
• Wide Operating Conditions.
• Supply Voltage : 7V
• Input Voltage : 5.5V
• Operating Free Air Temperature : 0°C to +70°C
• Storage Temperature Range : -65°C to +150°C

IC 74151 specifications:

• Advanced oxide-isolated, ion-implanted Schottky TTL process

• Switching performance is guaranteed over full temperature and VCC supply range
• Pin and functional compatible with LS family counterpart
• Improved output transient handling capability
• Type: CMOS
• Voltage Rating: 5VDC
• Temperature Rating: -65 to 165 Deg C
• Mounting: Through Hole

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 APPENDIX

Appendix-2

Projects that can be done:

1) Design a 1010 sequence detector with overlapping permitted.

2) Design a 1010 sequence detector with overlapping not permitted.
3) Design a circuit which will provide output “1” when a sequence “110” is detected
and maintain the output t “1” till it detects the next sequence”110” and then the
output will be “0”.
4) Design a traffic light controller which will show red, green and yellow in sequence
after an equal interval of time i.e.1s.
5) Design a serial parity detector.
6) Design a serial adder.
7) Magnitude comparator which will compare any multibit number.
8) A bus controller that receives requests on separate lines R0..R3 from four devices
to use the bus. Among the four outputs G0…G3 only one will be “1”. The lowest
number device has the highest priority.

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