LD7592

06/05/2017

Transition-Mode PFC Controller with

Fault Condition Protection

REV. 00

General Description Features

The LD7592 is a voltage mode PFC controller operating on  Transition Mode of PFC Pre-Regulator
transition mode, with several integrated functions of  Voltage Mode Control
protection, such as OVP, OCP, and Brown-in protection. It  Programmable Max. On-Time
reduces the components counts and is available in a  ZCD Auxiliary Winding is Unnecessary
SOP-8 or DIP-8 package. Those make it an ideal design  Low Startup Current (<1A)
for low cost applications.  UVLO (Under Voltage Lockout)
 LEB (Leading-Edge Blanking) on CS pin
It provides functions of low startup current, over voltage
 VCC OVP (Over Voltage Protection) on VCC pin
protection, open feedback protection, disable function,
 VO OVP (Over Voltage Protection) on INV pin
over current protection, under voltage lockout and
 Bulk Cap OVP (Over Voltage Protection) on OVP pin
integrated LEB of current sensing. The LD7592 adopts
 OCP (Cycle by Cycle Current Limit)
transition mode for power factor correction and realizes
 900/-1200mA Driving Capability
high efficiency and a low switching noise by zero current
 Internal OTP (Over Temperature Protection)
switching.
Applications
 Adaptor of Output above 75W.
 LCD TV Power Supply

Typical Application for Boost PFC

AC EMI
Input Filter

CS OUT

VCC INV

LD7592
RAMP OVP

COMP GND

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Pin Configuration
SOP-8 & DIP-8 (TOP VIEW)

GND

OVP
VCC
OUT
8 7 6 5

TOP MARK YY: Year code (D:2004, E:2005…)

WW: Week code
YYWWPP
PP: Production code

1 YYWWPP
2 3 4
INV

RAMP

COMP
CS

Ordering Information
Part number Package Top Mark Shipping

LD7592 GS SOP-8 Green package LD7592GS 2500 /tape & reel

LD7592 GN DIP-8 Green package LD7592GN 3600 /tube /Carton

The LD7592 is RoHs compliant/ Green Packaged.

Protection Mode

Part number VCC_OVP OCP OVP OTP

LD7592 Auto-Restart Cycle by Cycle Auto-Recovery Auto-Restart

Pin Descriptions

Pin NAME FUNCTION

1 INV Output voltage feed back control

2 RAMP Ramp generator, connecting a resistor to GND pin to set the saw tooth signal

3 COMP Output of the error amplifier for voltage loop compensation to achieve stable
This pin is the input of the zero current detection and over-current protection
4 CS
comparator
The OVP pin is used to detect PFC output over-voltage when the INV pin
5 OVP
information is not correct
6 GND Ground

7 OUT Gate drive output to drive the external MOSFET

8 VCC Supply voltage pin

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Block Diagram
VCC

SET
S Q Protection
VCC OVP

21V
PG R CLR Q
VCC OK internal bias All
& Vref Blocks
12V/7.5V

VCC OVP PG Vref OK

Int. OTP UVP

Protection
Burst Driver
Mode Stage
OUT
13V

Start
Timer

ZCD
Freq Limit
S Q

OCP
R
ZCD
ZCD
Comparator 2.675V/
2.55V
CS 2μA

OCP OVP OVP2

OCP
Comparator
200μA

UVP
UVP2
0.45V/
0.35V

Ramp
RAMP Generator
Freq Limit TCR mode
Control
PWM
Comparator
INV
GM
2.675V/
Vref
2.55V
Burst
OVP2 Mode
OVP
0.95V/1.0V

UVP2 UVP
0.45V/
0.35V

GND COMP

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Absolute Maximum Ratings

Supply Voltage VCC -0.3V ~ 30V
OUT -0.3V ~ VCC +0.3V
COMP, INV, CS, RAMP, OVP -0.3V ~ 6V
Maximum Junction Temperature 150C
Storage Temperature Range -65C to 150C
Package Thermal Resistance (SOP-8, JA) 160C/W
Package Thermal Resistance (DIP-8, JA) 100C/W
Power Dissipation (SOP-8, at Ambient Temperature = 85C) 250mW
Power Dissipation (DIP-8, at Ambient Temperature = 85C) 400mW
Lead temperature (Soldering, 10sec) 260C
ESD Voltage Protection, Human Body Model 2.5 KV
ESD Voltage Protection, Machine Model 250 V
Gate Output Current 900mA/-1200mA

Caution:
Stresses beyond the ratings specified in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only
rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied.

Recommended Operating Conditions

Item Min. Max. Unit

Operating Junction Temperature -40 125 C

VCC pin capacitor 22 47 F
COMP pin capacitor 0.1 4.7 F
RAMP pin resistor 4.7 100 k

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Electrical Characteristics
(VCC=14.0V, TA = 25C unless otherwise specified.)
PARAMETER CONDITIONS SYM. MIN TYP MAX UNITS
Supply Voltage (VCC Pin)
Startup Current VCC<UVLO (on) ICC_ST 0 1 A
VCOMP=0V ICC_OP1 0.25 0.5 0.75 mA
Operating Current VCOMP=3V ICC_OP2 1 3 5 mA
(with 1nF load on OUT pin) VCC_OVP ICC_OPA1 0.15 0.4 0.45 mA
VINV=0V ICC_OPA2 30 100 170 A
UVLO (off) VCC_OFF 7 7.5 8 V
UVLO (on) VCC_ON 11.0 12.0 13.0 V
VCC OVP Level VCC_OVP 19.5 21 22.5 V
Error Amplifier (COMP Pin)
Feedback Input Voltage VREF 2.465 2.500 2.535 V
Transconductance gmCOMP 100 140 180 mho
VINV=VREF+0.05V ISINK1 5 7 9 A
Output Sink Current
VINV=VREF+1V ISINK2 160 200 240 A
VINV=VREF-0.05V ISOURCE1 -5 -7 -9 A
Output Source Current
VINV=VREF-1V ISOURCE2 -160 -200 -240 A

Output Upper Clamp Voltage VINV=VREF-0.1V VCOMPCLAMP 4.8 5 5.2 V

Zero Duty Threshold VCOMP VZDC 0.9 0.95 1.0 V
Zero Duty Hysteresis Hysteresis VZDCH 20 50 80 mV
Fixed Frequency Mode Threshold VN 1.75 V
Touch Current Reduced Mode
100kHz VG 1.25 V
Threshold
Maximum Frequency FMAX 800 kHz
Green Mode Frequency FSW_GREEN 100 kHz
INV pin
UVP 0.4 0.45 0.5 V
Output Brown IN
Hysteresis UVP_HYS 0.05 0.1 0.15 V
OVP Trip Level OVP 2.62 2.675 2.73 V
OVP pin
UVP2 0.4 0.45 0.5 V
Output Brown IN
Hysteresis UVP2_HYS 0.05 0.1 0.15 V
OVP Trip Level OVP2 2.62 2.675 2.73 V

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PARAMETER CONDITIONS SYM. MIN TYP MAX UNITS

Current Sensing (CS Pin)
Current Sense Input Threshold Voltage OCP 200 A
Input bias current VCS=0V~1V IBIAS1 1 A
Leading Edge Blanking Time LEB 350 ns
CS Lower Clamp Voltage ICS=-2mA VCSCLAMP 0 -0.3 V
ZCD Trip Level IZCD 2 A
Maximum ON-Time, Ton-max (RAMP Pin)
Maximum On Time Voltage RRAMP=40.5K VRAMP 2.784 2.900 3.016 V
Maximum On Time Programming RRAMP=40.5K TRAMP1 20 24 28 s
Maximum On Time RRAMP≥100K TRAMPMAX1 36 40 44 s
Minimum OFF-Time
Minimum OFF-Time TMIN 1 s
Gate Drive Output (OUT Pin)
VCC=12V,
Output Low Level VOL 0.5 V
ISINK=20mA
VCC=12V,
Output High Level VOH 9 12 V
ISOURCE=20mA
Output High Clamp Level VCC=18V VO_CLAMP 11 13 15 V
VCC=12V,
Rising Time Tr 75 ns
CL=1000pF
VCC=12V,
Falling Time Tf 75 ns
CL=1000pF
Starter
Start Timer Period TSTART 120 150 180 s
Internal OTP
OTP Trip level * TINOTP 140 C
OTP Hysteresis * TINOTP_HYS 30 C
*: Guaranteed by design

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Typical Performance Characteristics

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Application Information
Operation Overview to deliver the gate drive signal, the supply current is

The LD7592 is an excellent voltage mode PFC controller. provided from the auxiliary winding of the PFC choke.

It meets the IEC61000-3-2 requirement and is intended Lower startup current requirement on the PFC controller

for the use in those pre-regulator that demands low power will help to increase the value of R1 and then reduce the

harmonics distortion. It integrates more functions to power consumption on R1. By using CMOS process and

reduce the external components counts and the size. Its the special circuit design, the maximum startup current of

major features are described as below. LD7592 is only 1A. If a higher resistance value of R1 is
chosen, it usually takes more time to start up. To carefully
Under Voltage Lockout (UVLO)
select the value of R1 and C1 will optimize the power
An UVLO comparator is implemented in it to detect the
consumption and startup time.
voltage on the VCC pin. It would assure the supply
voltage enough to turn on the LD7592 PFC controllers
Vin
and further to drive the power MOSFET. As shown in Fig.
8, a hysteresis is built in to prevent the shutdown from the
voltage dip during start up. The turn-on and turn-off
threshold level are set at 12.0V and 7.5V, respectively. CS OUT
R1
Vcc VCC INV

C1
LD7592
UVLO(on) RAMP OVP

UVLO(off) COMP GND

Fig. 9
t

I(Vcc) Output Voltage Setting

operating current (~ mA)

The LD7592 monitors the output voltage signal at INV pin

through a resistor divider pair Ra and Rb. A
startup current
(~µA) transconductance amplifier is used instead of the
t conventional voltage amplifier. The transconductance
Fig. 8 amplifier (voltage controlled current source) aids the
implementation of OVP and disables function. The output
Startup Current and Startup Circuit
current of the amplifier changes according to the voltage
The typical startup circuit to generate the LD7592 VCC is difference of the inverting and non-inverting input of the
shown in Fig. 9. During the startup transient, the VCC is amplifier. The output voltage of the amplifier is compared
lower than the UVLO threshold. Thus, there is no gate with the internal ramp signal to generate the turn-off
pulse produced from LD7592 to drive power MOSFET. signal. The output voltage is determined by the following
Therefore, the current through R1 will provide the startup relationship.
current and charge the capacitor C1. Whenever the VCC Ra
VO  2.5 V(1  ) (V)
voltage is high enough to turn on the LD7592 and further Rb

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INV
Where Ra and Rb are top and bottom feedback resistor
OVP Tripped
values (as shown in the Fig. 10).
2.675V
2.55V
OVP 2.675V/
2.55V

UVP
t
VO
0.45V/ OUT
0.35V
Vref = 2.5V Ra
GM

INV
Rb Disable
ON OFF

t
COMP
Fig. 11
Fig. 10
Brown in Protection
OVP and Disable Function
The LD7592 features Brown-in function on INV pin. The
To prevent the over voltage on the output capacitor from
built-in comparator detects the VINV and VOVP voltage
the fault condition, LD7592 is implemented with an OVP
condition, as shown in Fig. 12. This is done as follows:
function on INV pin. Whenever the INV pin voltage is
1. The INV and OVP voltage is higher than UVP
higher than OVP, the output gate drive circuit will be
2. The COMP voltage rise up and higher than VZDC
shutdown simultaneously to stop the switching of the
power MOSFET until the INV pin down to (OVP -
VINV.VOVP
OVP_HYS). The OVP function in LD7592 is an
auto-recovery type protection. The Fig. 11 shows its
operation.
UVP

The disable comparator disables the operation of the t

VComp
LD7592 when the voltage of the inverting input is lower
than 0.35V and there is 100mV hysteresis. An external
small signal MOSFET can be used to disable the IC. If the VZDC

IC is disabled, operating current decreases below 100μA t

OUT
to reduce power consumption.
The LD7592 can provide additional over voltage
protection on OVP pin. If INV pin voltage divider gets OFF ON

damaged, then OVP pin can supply additional over t

voltage protection. If OVP pin protection is not required, Fig. 12

the OVP pin can connect with INV pin.
Ramp Generator Block
The output of the gm error amplifier and the output of the
ramp generator block are compared to determine the
MOSFET on time, as shown in Fig. 13. The slope of the
ramp is determined by an external resistor connected to

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the RAMP pin. The voltage of the RAMP pin is 2.9V and is set at 200μA. From above, the inductor peak current
the slope is proportional to the current flowing out of the can be obtained from below.
RAMP pin. The internal ramp signal has a 1V offset; 200 A  R SNS
therefore, the drive output will be shut down if the voltage
IPEAK(MAX)  (A)
R CS
of the COMP pin is lower than 0.95V. The programmed
A 350ns leading-edge blanking (LEB) time is included in
on-time will be at its maximum when the COMP pin pulls
the input of CS pin to prevent the false-trigger from the
high. The COMP pin open voltage is about VCompclamp.
current spike.
According to the slope of the internal ramp, the maximum
on-time can be programmed. The necessary maximum Zero Current Detection
on-time will be achieved depending on the boost inductor, In DCM operation, the inductor current decreases during
lowest AC line voltage, and maximum output power. The MOSFET off. The current, ISNS, sourced from CS pin
resistor value should be designed properly. The also decreases simultaneously. When ISNS becomes
maximum on-time can be obtained from below smaller than IZCD, MOSFET will be turned on again. Since
RRAMP the voltage of CS pin is clamped at 0V, ISNS can be shown
TONTime(MAX)  (Sec)
1.6875  10 9 below, as shown in Fig. 14 and Fig. 15.

- VCSA
ISNS  (A)
R SNS
1V Offest Because of the inrush current of the boost topology,

RAMP Saw VCSA will be a large negative voltage at startup.

Tooth
Turn-off Meanwhile, LD7592 may be not enabled so the clamping
RRAMP 2.9V Greneator Signal
circuit of CS pin does not work. ISNS flowing through the

Comp ESD diode of CS pin can only be limited by RSNS. To

prevent too large ISNS from damaging LD7592, the
Fig. 13 resistance value of RSNS is recommended to be larger
than 1kΩ.
Output Drive Stage
An output stage of a CMOS buffer, with typical
900mA/-1200mA driving capability, is incorporated to
drive a power MOSFET directly. The output voltage is +
RCS I
clamped at 13V to protect the MOSFET gate even when CS RSNS -
the VCC voltage is higher than 13V.
ZCD
ZCD
Comparator
ISNS VCSA
Current Sensing and Leading-Edge 2μA
Blanking
The typical voltage mode of PFC controller feedbacks the
voltage signals to close the control loop and achieve Fig. 14
regulation. The LD7592 detects the inductor current from
the CS pin, which is for the pulse-by-pulse current limit.
The maximum current threshold of the current sensing pin

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IL 3. The VCC capacitor CVCC should be placed close to
VCC pin.

4. Signal ground will be separated, as shown in Fig.16

(green area).

t AC EMI
VCSA Input
 I ZCD t Filter
RSNS ZCD ZCD

RCS

CVCC
VCC OUT GND OVP

VCSA
LD7592
INV RAMP COMP CS

OUT
RSNS

OFF ON OFF ON
Fig. 16

Fig. 15

Fault Protection
There are several critical protections integrated in the
LD7592 to prevent the power supply or adapter from
being damaged. Those damages usually come from open
or short condition on the pins of LD7592.

Under the conditions listed below, the gate output will turn
off immediately to protect the power circuit:

1. Ramp pin short to ground

2. Ramp pin floating

3. CS pin floating

GND Layout Suggestion

LD7592 GND layout suggestion is shown in Fig.16.
The LD7592 current sense loop is very important for the
stable operation.
The following are GND layout suggestion for LD7592:

1. The current sense loop path should be minimized, as

shown in Fig.16 (red line loop).

2. The current sense resistor RCS should be placed

close to IC GND.

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Package Information
SOP-8

Dimensions in Millimeters Dimensions in Inch

Symbols
MIN MAX MIN MAX

A 4.801 5.004 0.189 0.197

B 3.810 3.988 0.150 0.157

C 1.346 1.753 0.053 0.069

D 0.330 0.508 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.178 0.229 0.007 0.010
I 0.102 0.254 0.004 0.010
J 5.791 6.198 0.228 0.244
M 0.406 1.270 0.016 0.050
θ 0° 8° 0° 8°

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Package Information
DIP-8

Dimension in Millimeters Dimensions in Inches

Symbol
Min Max Min Max

A 9.017 10.160 0.355 0.400

B 6.096 7.112 0.240 0.280

C ----- 5.334 ------ 0.210

D 0.356 0.584 0.014 0.023

E 1.143 1.778 0.045 0.070

F 2.337 2.743 0.092 0.108

I 2.921 3.556 0.115 0.140

J 7.366 8.255 0.29 0.325

L 0.381 ------ 0.015 --------

Important Notice
Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers

should verify the datasheets are current and complete before placing order.

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Revision History

REV. Date Change Notice

00 06/05/2017 Original Specification

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