EE537 Circuit Simulation Lab

Experiment 4
Name: Ahmad Raza Ansari
ID Number: 2024EEM1016 August 28, 2024

AIM: Design of basic gain stages using MOS transistors

1 Design a Common-Source (CS) amplifier stage

Design the following configurations of CS amplifier with total current consumption of 100 µA,
output voltage swing of 500 mV, CL = 5 pF, fugb > 20 MHz, and maximize the voltage gain. The
overdrive of the input transistor should be greater than 200 mV. Show the DC operating point
simulation and annotate Id , gm, region, and overdrive(Vdsat ). Show the achieved specifications
using transient and AC analysis.

1.1 With resistive load

In this simulation experiment, we will be using gpdk 0.18 µm and VDD = 1.8 V. We sketched a
common source amplifier with resistive load in which we are using NMOS transistor and DC voltage
and AC voltage as shown in Figure 1.

Figure 1: Common Source Amplifier with resistive load

We have given a condition that fugb > 20M Hz using which we find a transconductance condition
as shown in equation 2.

g m = 2π ∗ C L ∗ f ugb (1)
The values of components are:
• fugb = 20 MHz
• CL = 5 pF
g m > 0.628 mA/V (2)

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 We know the formula of gm related to drain current and gate to source voltage as shown in
equation 3.

2ID
gm = (3)
VGS − VT H

we assume gm = 0.8 mA/V and the given drain current is 100 uA and the threshold voltage is 440
mV we have to find Vgs using 3.

2 ∗ 100 ∗ 10−6
0.8 ∗ 10−3 =
VGS − VT H

V GS = 690 mV (4)

From drain current equation 5 we have to find the aspect ratio.

un Cox W (VGS − VT H )2
ID = (5)
2L

Given values

• ID = 100 uA

• VGS − Vth = 250 mV

• un Cox = 310 uA/V 2

After calculation, the aspect ratio found as shown in equation 6

W 10.3
= (6)
L 1

Output After substituting the value I got through the calculation the bandwidth I found is 25
MHZ the gain is 9.4 and also the voltage swing is 500 mV as shown in Figure 2.

Figure 2: Common Source Amplifier with resistive load

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1.2 With diode connected PMOS load.

In this simulation experiment, we will be using gpdk 0.18 µm and VDD = 1.8 V. We sketched a
common source amplifier with PMOS load in which we are using an NMOS transistor and DC
voltage and AC voltage as shown in Figure 3.

Figure 3: Common Source Amplifier with PMOS load

In this, our main focus on putting PMOS is in saturation so that we can achieve maximum gain.
We mostly used previous calculations and just a little bit for this part because our NMOS is in
saturation we achieved in the last one. We did some calculations for PMOS.

Output We use the NMOS transistor with resistive load result in this too and also we put the
precise value after calculation for PMOS so that it operates in saturation region and we achieve
our required result. We get a swing of 500 mV and the bandwidth is 24 MHz as shown in Figure 6.

Figure 4: Common Source Amplifier with PMOS load

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1.3 With diode connected NMOS load.
In this simulation experiment, we will be using gpdk 0.18 µm and VDD = 1.8 V. We sketched a
common source amplifier with NMOS load in which we are using an NMOS transistor and DC
voltage and AC voltage as shown in Figure 5.

Figure 5: Common Source Amplifier with NMOS load

Observation of the load NMOS is always in saturation region because we connect the gate to drain
and for saturation VDS >= VGS − VT H it is always true. Current is constant that is 100 uA so we
have to calculate the W/L for this and we use the Current equation 5 and get 2:1.

Output We use the NMOS transistor with resistive load result in this too and also we put the
precise value after calculation for PMOS so that it operates in saturation region and we achieve
our required result. We get a swing of approx 500 mV and the bandwidth is 25.1 MHz as shown
in Figure 6.

Figure 6: Common Source Amplifier with NMOS load

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1.4 With PMOS current source as load.
In this simulation experiment, we will be using gpdk 0.18 µm and VDD = 1.8 V. We sketched a
common source amplifier with PMOS current source as load in which we are using an NMOS
transistor and DC voltage and AC voltage as shown in Figure 8.

Figure 7: Common Source Amplifier with PMOS current source as load

For PMOS to act in saturation region it must follow the given condition as shown in equation 7.

V SD ≥ V SG − |VT H | (7)

Output For the current to be 100 uA the value of W/L we have to take very carefully because
even a small change in the transistor changes its operating region. We put the precise value after
calculation for PMOS so that it operates in saturation region and we achieve our required result.
We get a swing of approx 500 mV and the bandwidth is 25.1 MHz as shown in Figure 8.

Figure 8: Common Source Amplifier with PMOS current source as load

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1.5 With resistive load and source degeneration. Determine its output impedance
using simulation.
We sketched a common source with resistive load and source degeneration for finding output
impedance we put an AC voltage and one more capacitance we added to the circuit as shown
in Figure 9.

Figure 9: Common Source Amplifier with resistive load and source degeneration.

Output
We find the output voltage and current through capacitance and these data to the calculator divide
the voltage by the current and take the graph of impedance as shown in Figure 10. We get the
impedance by taking the mean of the graph which is 5.915 ∗ 103 G.

Figure 10: Common Source Amplifier with resistive load and source degeneration.

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2 Design a Common-Gate (CG) amplifier stage
Design the CG amplifier with resistive load, total current consumption of 100 µA, output voltage
swing of 500 mV, CL = 5 pF, fugb > 20 MHz and maximize the voltage gain. Overdrive of the input
transistor should be greater than 200 mV. The source of the amplifier is driven by an ideal voltage
source. Show the DC operating point simulation and annotate Id, gm, region and overdrive(vdsat).
Show the achieved specifications using transient and AC analysis.

2.1 Design a common gate amplifier with given conditions.

In this simulation experiment, we will be using gpdk 0.18 µm and VDD = 1.8 V. We sketched a
common gate amplifier with resistive load in which we are using NMOS transistor and DC voltage
and AC voltage as shown in Figure 11.

Figure 11: Common Gate Amplifier

We have given a condition that fugb > 20M Hz using which we find a transconductance condition
as shown in equation 9.
g m = 2π ∗ C L ∗ f ugb (8)
The values of components are:
• fugb = 20 MHz
• CL = 5 pF
g m > 0.628 mA/V (9)

2ID
gm = (10)
VGS − VT H
we assume gm = 0.97 mA/V and the given drain current is 100 uA and the threshold voltage is
544 mV we have to find Vgs using equation 15.

2 ∗ 100 ∗ 10−6
0.97 ∗ 10−3 =
VGS − VT H

V GS = 750 mV (11)

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 un Cox W (VGS − VT H )2
ID = (12)
2L

Given values

• ID = 100 uA

• VGS − Vth = 206 mV

• un Cox = 310 uA/V 2

After calculation, the aspect ratio found as shown in equation 13

W 15.38
= (13)
L 1

Output
We get the desired bandwidth 22.93 MHz and also the voltage swing of 500 mV as shown in figure
12. To get the desired output we did a precise calculation and then after we substituted the value
of the transistor for getting a voltage swing of 500 mV we varied the amplitude of sinusoidal voltage
until we got the desired output.

Figure 12: Common Gate Amplifier

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2.2 Determine the input impedance by simulation and verify the same by hand
calculations.
We sketched a common gate amplifier using cadence virtuoso to find input impedance. we are using
gpdk180nm library for the NMOS transistor we put the AC source voltage to the source and try
to find the voltage by the current for the input impedance schematic as shown in figure 14.

Figure 13: Common Gate Amplifier

Hand calculation

The input impedance of the common gate amplifier is shown in the equation 15.
RD + r o
Rin = (14)
1 + (g m + g mb )ro

if (gm + gmb ) >> 1 then modify equation is

RD 1
Rin ≈ + (15)
(g m + g mb )ro g m + g mb

We got values from cadence after simulation and the circuit schematic that we put.

• RD = 9.5 KΩ

• gm = 0.725 mA/V

• gmb = 0.218 mA/V

• ro = 229.7 KΩ

Rin = 1.10 KΩ (16)

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 Output

We got the input impedance after using 15 is 1.10 KΩ and we got the input impedance of the
common gate amplifier through cadence simulation after taking the average value 1.3 KΩ. We see
a small change in hand calculation and simulation calculations because cadence takes all cases that
affect the circuit like parasitic capacitance and so many things that we neglect in hand calculation
even that in equation 15 I consider as (gm + gmb ) >> 1 but in cadence it into consideration that
we neglect that’s why we have seen a small change in the input impedance. The input impedance
of the circuit is shown below 14.

Figure 14: Common Gate Amplifier

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2.3 Find out the overall gain of the amplifier when the amplifier is driven by
a voltage source having the source resistance of 1 KΩ. Modify the gate
bias voltage to maintain the same overdrive and current of the transistor.
Explain the difference (if any) between gain using an ideal voltage source
and gain using a voltage source with source resistance
We sketched the circuit using cadence virtuoso and using the gpdk180nm library for NMOS. It is a
common gate amplifier and we do some modification that is we put a resistance that is connected to
the source and ground. We have to maintain the NMOS in saturation and try to find the maximum
gain we can achieve in the circuit as shown in figure 15

Figure 15: Common Gate Amplifier input impedance

For NMOS the saturation condition is VDS ≥ VGS − VT H and after some calculation, we put the
value of source and gate voltage keep in mind that the NMOS is in saturation region and also we
maintain the current near about 100 uA we maintaining the overdrive voltage as same as common
gate amplifier without source resistance. We have a gain formula for the circuit given in equation 17.

(g m + g mb )ro + 1
Av = RD (17)
ro + (g m + g mb )ro RS + RS + RD

As we shown the equation 17 we put the RS in the circuit that also reflect in the gain of the circuit.

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 Output of the CG amplifier with source resistance

The output of the circuit we get is shown in figure 16. We achieve the voltage swing of 500
mV but the bandwidth is 12 MHz. For this circuit, we have to focus on so many things that change
simultaneously even with the small change in W/L ratio or anything. we are concerned about the
current that has to near around 100 uA.

Figure 16: Common Gate Amplifier

Explain the difference (if any) between gain using an ideal voltage source and gain
using a voltage source with source resistance

Ideal voltage source has zero internal resistance and voltage sources often have some internal re-
sistance. Ideal voltage It maintains a fixed voltage across its terminals, regardless of the load
connected. Voltage Drop: The voltage delivered to the load is slightly less than the ideal volt-
age due to the voltage drop across the internal resistance. The gain in the ideal voltage source
is greater as compared to the practical voltage source because, the practical voltage source, has
internal resistance.

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