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Datasheet

S7G2 Microcontroller Group

Datasheet

Renesas Synergy™ Platform

Synergy Microcontrollers
S7 Series

All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).

www.renesas.com Rev.1.40 Aug 2018

S7G2 Microcontroller Group
Datasheet
Leading performance 240-MHz Arm® Cortex®-M4 core, up to 4-MB code flash memory, 640-KB SRAM, Graphics LCD
Controller, 2D Drawing Engine, Capacitive Touch Sensing Unit, Ethernet MAC Controller with IEEE 1588 PTP, USB 2.0
High-Speed, USB 2.0 Full-Speed, SDHI, Quad SPI, security and safety features, and advanced analog.

Features
■ Arm Cortex-M4 Core with Floating Point Unit (FPU) ■ System and Power Management
 Armv7E-M architecture with DSP instruction set  Low power modes
 Maximum operating frequency: 240 MHz  Switching regulator
 Support for 4-GB address space  Realtime Clock (RTC) with calendar and VBATT support
 On-chip debugging system: JTAG, SWD, and ETM  Event Link Controller (ELC)
 Boundary scan and Arm® Memory Protection Unit (MPU)  DMA Controller (DMAC) × 8
 Data Transfer Controller (DTC)
■ Memory  Key Interrupt Function (KINT)
 Up to 4-MB code flash memory (80 MHz zero wait states)  Power-on reset
 64-KB data flash memory (125,000 erase/write cycles)  Low Voltage Detection (LVD) with voltage settings
 Up to 640-KB SRAM
 Flash Cache (FCACHE) ■ Security and Encryption
 Memory Protection Units (MPU)  AES128/192/256
 Memory Mirror Function (MMF)  3DES/ARC4
 128-bit unique ID  SHA1/SHA224/SHA256/MD5
 GHASH
■ Connectivity  RSA/DSA/ECC
 Ethernet MAC Controller (ETHERC) × 2  True Random Number Generator (TRNG)
 Ethernet DMA Controller (EDMAC)
 Ethernet PTP Controller (EPTPC) ■ Human Machine Interface (HMI)
 USB 2.0 High-Speed Module (USBHS)  Graphics LCD Controller (GLCDC)
- On-chip transceiver  JPEG Codec
- USB battery charge version 1.2 supported  2D Drawing Engine (DRW)
 USB 2.0 Full-Speed Module (USBFS)  Capacitive Touch Sensing Unit (CTSU)
- On-chip transceiver  Parallel Data Capture Unit (PDC)
 Serial Communications Interface (SCI) with FIFO × 10 ■ Multiple Clock Sources
 Serial Peripheral Interface (SPI) × 2
 Main clock oscillator (MOSC) (8 to 24 MHz)
 I2C Bus Interface (IIC) × 3  Sub-clock oscillator (SOSC) (32.768 kHz)
 CAN module (CAN) × 2  High-speed on-chip oscillator (HOCO) (16/18/20 MHz)
 Serial Sound Interface (SSI) × 2  Middle-speed on-chip oscillator (MOCO) (8 MHz)
 SD/MMC Host Interface (SDHI) × 2  Low-speed on-chip oscillator (LOCO) (32.768 kHz)
 Quad Serial Peripheral Interface (QSPI)  IWDT-dedicated on-chip oscillator (15 kHz)
 IrDA interface  Clock trim function for HOCO/MOCO/LOCO
 Sampling Rate Converter (SRC)  Clock out support
 External memory space
- 8-bit or 16-bit bus space is selectable per area ■ General-Purpose I/O Ports
- SDRAM support  Up to 172 input/output pins
- Up to 9 CMOS input
■ Analog - Up to 163 CMOS input/output
 12-Bit A/D Converter (ADC12) with 3 sample-and-hold circuits - Up to 22 input/output 5 V tolerant
each, x2 - Up to 24 high current (20 mA)
 12-Bit D/A Converter (DAC12) × 2
 High-Speed Analog Comparator (ACMPHS) × 6 ■ Operating Voltage
 Programmable Gain Amplifier (PGA) × 6  VCC: 2.7 to 3.6 V
 Temperature Sensor (TSN) ■ Operating Temperature and Packages
■ Timers  Ta = –40°C to +85°C
 General PWM Timer 32-Bit Enhanced High Resolution - 224-pin BGA (13 mm × 13 mm, 0.8 mm pitch)
(GPT32EH) × 4 - 176-pin BGA (13 mm × 13 mm, 0.8 mm pitch)
 General PWM Timer 32-Bit Enhanced (GPT32E) × 4 - 145-pin LGA (7 mm × 7 mm, 0.5 mm pitch)
 General PWM Timer 32-Bit (GPT32) × 6  Ta = –40°C to +105°C
 Asynchronous General-Purpose Timer (AGT) × 2 - 176-pin LQFP (24 mm × 24 mm, 0.5 mm pitch)
 Watchdog Timer (WDT) - 144-pin LQFP (20 mm × 20 mm, 0.5 mm pitch)
- 100-pin LQFP (14 mm × 14 mm, 0.5 mm pitch)
■ Safety
 SRAM parity error check
 Flash area protection
 ADC self-diagnosis function
 Clock Frequency Accuracy Measurement Circuit (CAC)
 Cyclic Redundancy Check (CRC) calculator
 Data Operation Circuit (DOC)
 Port Output Enable for GPT (POEG)
 Independent Watchdog Timer (IWDT)
 GPIO readback level detection
 Register write protection
 Main oscillator stop detection
 Illegal memory access

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1. Overview
The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set
of Renesas peripherals to facilitate design scalability and efficient platform-based product development.
The MCU in this series incorporates a high-performance Arm Cortex®-M4 core running up to 240 MHz with the
following features:
 Up to 4-MB code flash memory
 640-KB SRAM
 Graphics LCD Controller (GLCDC)
 2D Drawing Engine (DRW)
 Capacitive Touch Sensing Unit (CTSU)
 Ethernet MAC Controller (ETHERC) with IEEE 1588 PTP, USBFS, USBHS, SD/MMC Host Interface
 Quad Serial Peripheral Interface (QSPI)
 Security and safety features
 Analog peripherals.

1.1 Function Outline

Table 1.1 Arm core

Feature Functional description
Arm Cortex-M4 core  Maximum operating frequency: up to 240 MHz
 Arm Cortex-M4 core:
- Revision: r0p1-01rel0
- Armv7E-M architecture profile
- Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008
 Arm Memory Protection Unit (Arm MPU):
- Armv7 Protected Memory System Architecture
- 8 protect regions
 SysTick timer:
- Driven by SYSTICCLK (LOCO) or ICLK.

Table 1.2 Memory

Feature Functional description
Code flash memory Maximum 4 MB of code flash memory. See section 55, Flash Memory in User’s Manual.
Data flash memory 64 KB of data flash memory. See section 55, Flash Memory in User’s Manual.
Option-setting memory The option-setting memory determines the state of the MCU after a reset. See section 7,
Option-Setting Memory in User’s Manual.
Memory Mirror Function (MMF) The Memory Mirror Function (MMF) can be configured to mirror the wanted application image
load address in code flash memory to the application image link address in the 23-bit unused
memory space (memory mirror space addresses). Your application code is developed and
linked to run from this MMF destination address. The application code does not need to know
the load location where it is stored in code flash memory. See section 5, Memory Mirror
Function (MMF) in User’s Manual.
SRAM On-chip high-speed SRAM providing either parity-bit or Double-bit Error Detection (DED). The
first 32 KB of SRAM0 is subject to DED. Parity check is performed for other areas. See section
53, SRAM in User’s Manual.
Standby SRAM On-chip SRAM that can retain data in Deep Software Standby mode. See section 54, Standby
SRAM in User’s Manual.

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Table 1.3 System (1 of 2)

Feature Functional description
Operating modes Two operating modes:
- Single-chip mode
- SCI or USB boot mode.
See section 3, Operating Modes in User’s Manual.
Resets 14 resets:
 RES pin reset
 Power-on reset
 Voltage monitor 0 reset
 Voltage monitor 1 reset
 Voltage monitor 2 reset
 Independent watchdog timer reset
 Watchdog timer reset
 Deep Software Standby reset
 SRAM parity error reset
 SRAM DED error reset
 Bus master MPU error reset
 Bus slave MPU error reset
 Stack pointer error reset
 Software reset.
See section 6, Resets in User’s Manual.
Low Voltage Detection (LVD) The Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin, and
the detection level can be selected using a software program. See section 8, Low Voltage
Detection (LVD) in User’s Manual.
Clocks  Main clock oscillator (MOSC)
 Sub-clock oscillator (SOSC)
 High-speed on-chip oscillator (HOCO)
 Middle-speed on-chip oscillator (MOCO)
 Low-speed on-chip oscillator (LOCO)
 PLL frequency synthesizer
 IDWT-dedicated on-chip oscillator
 Clock out support.
See section 9, Clock Generation Circuit in User’s Manual.
Clock Frequency Accuracy The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be
Measurement Circuit (CAC) measured (measurement target clock) within the time generated by the clock to be used as a
measurement reference (measurement reference clock), and determines the accuracy
depending on whether the number of pulses is within the allowable range.
When measurement is complete or the number of pulses within the time generated by the
measurement reference clock is not within the allowable range, an interrupt request is
generated. See section 10, Clock Frequency Accuracy Measurement Circuit (CAC) in User’s
Manual.
Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC
module and DMAC module. The ICU also controls NMI interrupts. See section 14, Interrupt
Controller Unit (ICU) in User’s Manual.
Key interrupt function (KINT) A key interrupt can be generated by setting the Key Return Mode register (KRM) and inputting
a rising or falling edge to the key interrupt input pins. See section 21, Key Interrupt Function
(KINT) in User’s Manual.
Low power modes Power consumption can be reduced in multiple ways, including by setting clock dividers,
controlling EBCLK output, controlling SDCLK output, stopping modules, selecting power
control mode in normal operation, and transitioning to low power modes. See section 11, Low
Power Modes in User’s Manual.
Battery backup function A battery backup function is provided for partial powering by a battery. The battery-powered
area includes the RTC, SOSC, backup memory, and switch between VCC and VBATT. See
section 12, Battery Backup Function in User’s Manual.
Register write protection The register write protection function protects important registers from being overwritten
because of software errors. See section 13, Register Write Protection in User’s Manual.
Memory Protection Unit (MPU) Three Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided
for memory protection. See section 16, Memory Protection Unit (MPU) in User’s Manual.

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Table 1.3 System (2 of 2)

Feature Functional description
Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bit down-counter that can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow.
A refresh-permitted period can be set to refresh the counter and used as the condition for
detecting when the system runs out of control. See section 27, Watchdog Timer (WDT) in
User’s Manual.
Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset
the MCU or to generate a non-maskable interrupt or interrupt for a timer underflow. Because
the timer operates with an independent, dedicated clock source, it is particularly useful in
returning the MCU to a known state as a fail safe mechanism when the system runs out of
control. The IWDT can be triggered automatically on a reset, underflow, or refresh error, or by
a refresh of the count value in the registers. See section 28, Independent Watchdog Timer
(IWDT) in User’s Manual.

Table 1.4 Event link

Feature Functional description
Event Link Controller (ELC) The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral
modules as event signals to connect them to different modules, enabling direct interaction
between the modules without CPU intervention. See section 19, Event Link Controller (ELC)
in User’s Manual.

Table 1.5 Direct memory access

Feature Functional description
Data Transfer Controller (DTC) A Data Transfer Controller (DTC) module is provided for transferring data when activated by an
interrupt request. See section 18, Data Transfer Controller (DTC) in User’s Manual.
DMA Controller (DMAC) An 8-channel DMA Controller (DMAC) module is provided for transferring data without the
CPU. When a DMA transfer request is generated, the DMAC transfers data stored at the
transfer source address to the transfer destination address. See section 17, DMA Controller
(DMAC) in User’s Manual.

Table 1.6 External bus interface

Feature Functional description
External buses  CS area (EXBIU): Connected to the external devices (external memory interface)
 SDRAM area (EXBIU): Connected to the SDRAM (external memory interface)
 QSPI area (EXBIUT2): Connected to the QSPI (external device interface).

Table 1.7 Timers (1 of 2)

Feature Functional description
General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with 14 channels. PWM waveforms can be
generated by controlling the up-counter, down-counter, or up- and down-counter. In addition,
PWM waveforms can be generated for controlling brushless DC motors. The GPT can also be
used as a general-purpose timer. See section 23, General PWM Timer (GPT) in User’s
Manual.
Port Output Enable for GPT (POEG) Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)
output pins in the output disable state. See section 22, Port Output Enable for GPT (POEG) in
User’s Manual.
Asynchronous General-Purpose The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse
Timer (AGT) output, external pulse width or period measurement, and counting of external events.
This 16-bit timer consists of a reload register and a down-counter. The reload register and the
down-counter are allocated to the same address, and can be accessed with the AGT register.
See section 25, Asynchronous General-Purpose Timer (AGT) in User’s Manual.

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Table 1.7 Timers (2 of 2)

Feature Functional description
Realtime Clock (RTC) The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count
mode, that are controlled by the register settings.
For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and
automatically adjusts dates for leap years.
For binary count mode, the RTC counts seconds and retains the information as a serial value.
Binary count mode can be used for calendars other than the Gregorian (Western) calendar.
See section 26, Realtime Clock (RTC) in User’s Manual.

Table 1.8 Communication interfaces (1 of 2)

Feature Functional description
Serial Communications Interface The Serial Communications Interface (SCI) is configurable to five asynchronous and
(SCI) synchronous serial interfaces:
 Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter
(ACIA))
 8-bit clock synchronous interface
 Simple IIC (master-only)
 Simple SPI
 Smart card interface.
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and
transmission protocol.
Each SCI has FIFO buffers to enable continuous and full-duplex communication, and the data
transfer speed can be configured independently using an on-chip baud rate generator. See
section 34, Serial Communications Interface (SCI) in User’s Manual.
IrDA Interface (IrDA) The IrDA interface sends and receives IrDA data communication waveforms in cooperation
with the SCI1 based on the IrDA (Infrared Data Association) standard 1.0. See section 35,
IrDA Interface in User’s Manual.
I2C bus Interface (IIC) The 3-channel I2C bus interface (IIC) conforms with and provides a subset of the NXP I2C
(Inter-Integrated Circuit) bus interface functions. See section 36, I2C Bus Interface (IIC) in
User’s Manual.
Serial Peripheral Interface (SPI) Two independent Serial Peripheral Interface (SPI) channels are capable of high-speed, full-
duplex synchronous serial communications with multiple processors and peripheral devices.
See section 38, Serial Peripheral Interface (SPI) in User’s Manual.
Serial Sound Interface (SSI) The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with
digital audio devices for transmitting PCM audio data over a serial bus with the MCU. The SSI
supports an audio clock frequency of up to 50 MHz, and can be operated as a slave or master
receiver, transmitter, or transceiver to suit various applications. The SSI includes 8-stage FIFO
buffers in the receiver and transmitter, and supports interrupts and DMA-driven data reception
and transmission. See section 41, Serial Sound Interface (SSI) in User’s Manual.
Quad Serial Peripheral Interface The Quad Serial Peripheral Interface (QSPI) is a memory controller for connecting a serial
(QSPI) ROM (nonvolatile memory such as a serial flash memory, serial EEPROM, or serial FeRAM)
that has an SPI-compatible interface. See section 39, Quad Serial Peripheral Interface (QSPI)
in User’s Manual.
Controller Area Network (CAN) The Controller Area Network (CAN) module provides functionality to receive and transmit data
module using a message-based protocol between multiple slaves and masters in electromagnetically-
noisy applications.
The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports
up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox
and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are
supported. See section 37, Controller Area Network (CAN) Module in User’s Manual.
USB 2.0 Full-Speed (USBFS) module The USB 2.0 Full-Speed (USBFS) module can operate as a host controller or device controller.
The module supports full-speed and low-speed (host controller only) transfer as defined in
Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and
supports all of the transfer types defined in Universal Serial Bus Specification 2.0.
The USB has buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9
can be assigned any endpoint number based on the peripheral devices used for
communication or based on your system. See section 32, USB 2.0 Full-Speed Module
(USBFS) in User’s Manual.

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Table 1.8 Communication interfaces (2 of 2)

Feature Functional description
USB 2.0 High-Speed (USBHS) The USB 2.0 High-Speed (USBHS) module can operate as a host controller or a device
module controller. As a host controller, the USBHS supports high-speed transfer, full-speed transfer,
and low-speed transfer as defined in Universal Serial Bus Specification 2.0. As a device
controller, the USBHS supports high-speed transfer and full-speed transfer as defined in
Universal Serial Bus Specification 2.0. The USBHS has an internal USB transceiver and
supports all of the transfer types defined in Universal Serial Bus Specification 2.0.
The USBHS has FIFO buffers for data transfer, providing a maximum of 10 pipes. Any
endpoint number can be assigned to pipes 1 to 9, based on the peripheral devices or your
system for communication. See section 33, USB 2.0 High-Speed Module (USBHS) in User’s
Manual.
Ethernet MAC with IEEE 1588 PTP Two-channel Ethernet MAC Controller (ETHERC) compliant with the Ethernet/IEEE802.3
(ETHERC) Media Access Control (MAC) layer protocol. Each ETHERC channel provides one channel of
the MAC layer interface, connecting the MCU to the physical layer LSI (PHY-LSI) that allows
transmission and reception of frames compliant with the Ethernet and IEEE802.3 standards.
The ETHERC is connected to the Ethernet DMA Controller (EDMAC) so data can be
transferred without using the CPU.
To handle timing and synchronization between devices, an on-chip Precision Time Protocol
(PTP) module for the Ethernet PTP Controller (EPTPC) applies the PTP defined in the IEEE
1588-2008 version 2.0 standard.
The EPTPC is composed of:
 Synchronization Frame Processing units (SYNFP0 and SYNFP1)
 A Packet Relation Controller unit (PRC-TC)
 A Statistical Time Correction Algorithm unit (STCA).
Use the EPTPC in combination with the on-chip Ethernet MAC Controller (ETHERC) and the
DMA Controller for the PTP Ethernet Controller (PTPEDMAC). See section 29, Ethernet MAC
Controller (ETHERC) in User’s Manual.
SD/MMC Host Interface (SDHI) The SDHI and MultiMediaCard (MMC) interface module provides the functionality required to
connect a variety of external memory cards to the MCU. The SDHI supports both 1-bit and 4-
bit buses for connecting memory cards that support SD, SDHC, and SDXC formats. When
developing host devices that are compliant with the SD Specifications, you must comply with
the SD Host/Ancillary Product License Agreement (SD HALA).
The MMC interface supports 1-bit, 4-bit, and 8-bit MMC buses that provide eMMC 4.51
(JEDEC Standard JESD 84-B451) device access. This interface also provides backward
compatibility and supports high-speed SDR transfer modes. See section 43, SD/MMC Host
Interface (SDHI) in User’s Manual.

Table 1.9 Analog

Feature Functional description
12-bit A/D Converter (ADC12) Up to two successive approximation 12-bit A/D Converters (ADC12) are provided. In unit 0, up
to 13 analog input channels are selectable. In unit 1, up to 12 analog input channels, the
temperature sensor output, and an internal reference voltage are selectable for conversion.
The A/D conversion accuracy is selectable from 12-bit, 10-bit, and 8-bit conversion, making it
possible to optimize the tradeoff between speed and resolution in generating a digital value.
See section 47, 12-Bit A/D Converter (ADC12) in User’s Manual.
12-bit D/A Converter (DAC12) A 12-bit D/A Converter (DAC12) converts data and includes an output amplifier. See section
48, 12-Bit D/A Converter (DAC12) in User’s Manual.
Temperature sensor (TSN) The on-chip Temperature Sensor (TSN) can determine and monitor the die temperature for
reliable operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is linear.
The output voltage is provided to the ADC12 for conversion and can also be used by the end
application. See section 49, Temperature Sensor (TSN) in User’s Manual.
High-Speed Analog Comparator The High-Speed Analog Comparator (ACMPHS) compares a test voltage with a reference
(ACMPHS) voltage and provides a digital output based on the conversion result.
Both the test and reference voltages can be provided to the comparator from internal sources
such as the DAC12 output and internal reference voltage, and an external source with or
without an internal PGA.
Such flexibility is useful in applications that require go/no-go comparisons to be performed
between analog signals without necessarily requiring A/D conversion. See section 50, High-
Speed Analog Comparator (ACMPHS) in User’s Manual.

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Table 1.10 Human machine interfaces

Feature Functional description
Capacitive Touch Sensing Unit The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the
(CTSU) touch sensor. Changes in the electrostatic capacitance are determined by the software, which
enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode
surface of the touch sensor is usually enclosed with an electrical insulator so that fingers do
not come into direct contact with the electrodes. See section 51, Capacitive Touch Sensing
Unit (CTSU) in User’s Manual.

Table 1.11 Graphics

Feature Functional description
Graphics LCD Controller (GLCDC) The Graphics LCD Controller (GLCDC) provides multiple functions and supports various data
formats and panels. Key GLCDC features include:
 GPX bus master function for accessing graphics data
 Superimposition of three planes (single color background plane, graphic 1 plane, and
graphic 2 plane)
 Support for many types of 32-bit or 16-bit per pixel graphics data and 8-bit, 4-bit, or 1-bit LUT
data format
 Digital interface signal output supporting a video image size of WVGA or greater.
See section 58, Graphics LCD Controller (GLCDC) in User’s Manual.
2D Drawing Engine (DRW) The 2D Drawing Engine (DRW) provides flexible functions that can support almost any object
geometry rather than being bound to only a few specific geometries such as lines, triangles, or
circles. The edges of every object can be independently blurred or antialiased.
Rasterization is executed at one pixel per clock on the bounding box of the object from left to
right and top to bottom. The DRW can also raster from bottom to top to optimize the
performance in certain cases. In addition, optimization methods are available to avoid
rasterization of many empty pixels of the bounding box.
The distances to the edges of the object are calculated by a set of edge equations for every
pixel of the bounding box. These edge equations can be combined to describe the entire
object.
If a pixel is inside the object, it is selected for rendering. If it is outside, it is discarded. If it is on
the edge, an alpha value can be chosen proportional to the distance of the pixel to the nearest
edge for antialiasing.
Every pixel that is selected for rendering can be textured. The resulting aRGB quadruple can
be modified by a general raster operation approach independently for each of the four
channels. The aRGB quadruples can then be blended with one of the multiple blend modes of
the DRW.
The DRW provides two inputs (texture read and framebuffer read), and one output
(framebuffer write).
The internal color format is always aRGB (8888). The color formats from the inputs are
converted to the internal format on read and a conversion back is made on write.
See section 56, 2D Drawing Engine (DRW) in User’s Manual.
JPEG Codec (JPEG) The JPEG Codec (JPEG) incorporates a JPEG codec that conforms to the JPEG baseline
compression and decompression standard. This provides high-speed compression of image
data and high-speed decoding of JPEG data. See section 57, JPEG Codec in User’s Manual.
Parallel Data Capture (PDC) unit One Parallel Data Capture (PDC) unit is provided for communicating with external I/O devices,
including image sensors, and transferring parallel data such as an image output from the
external I/O device through the DTC or DMAC to the on-chip SRAM and external address
spaces (the CS and SDRAM areas). See section 44, Parallel Data Capture Unit (PDC) in
User’s Manual.

Table 1.12 Data processing (1 of 2)

Feature Functional description
Cyclic Redundancy Check (CRC) The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the
calculator data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first
communication. Additionally, various CRC-generating polynomials are available. The snoop
function allows monitoring reads from and writes to specific addresses. This function is useful
in applications that require CRC code to be generated automatically in certain events, such as
monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See
section 40, Cyclic Redundancy Check (CRC) Calculator in User’s Manual.

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Table 1.12 Data processing (2 of 2)

Feature Functional description
Data Operation Circuit (DOC) The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. See section 52,
Data Operation Circuit (DOC) in User’s Manual.
Sampling Rate Converter (SRC) The Sampling Rate Converter (SRC) converts the sampling rate of data produced by various
audio decoders, such as the WMA, MP3, and AAC. Both 16-bit stereo and monaural data are
supported. See section 42, Sampling Rate Converter (SRC) in User’s Manual.

Table 1.13 Security

Feature Functional description
Secure Crypto Engine 7 (SCE7)  Security algorithms:
- Symmetric algorithms: AES, 3DES, and ARC4
- Asymmetric algorithms: RSA, DSA, and ECC.
 Other support features:
- TRNG (True Random Number Generator)
- Hash-value generation: SHA1, SHA224, SHA256, GHASH, and MD5
- 128-bit unique ID.

1.2 Block Diagram

Figure 1.1 shows the block diagram of the MCU superset, some individual devices within the group have a subset of the
features.

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Memory Bus Arm® Cortex®-M4 System

4 MB code flash External DSP FPU POR/LVD Clocks

CSC MOSC/SOSC
64 KB data flash
MPU Reset
SDRAM (H/M/L) OCO
640 KB SRAM
NVIC Mode control
8 KB Standby MPU PLL /USBPLL
SRAM
System timer Power control
CAC

DMA Test and DBG interface ICU Battery backup

DTC
Register write
KINT protection
DMAC × 8

Timers Communication interfaces Human machine interfaces

SCI × 10 Graphics
QSPI USBHS CTSU
GPT32EH x 4
IrDA × 1 GLCDC
GPT32 E x 4
GPT 32 x 6 ETHERC × 2
IIC × 3 SDHI × 2
with IEEE 1588 DRW

SPI × 2 CAN × 2
AGT × 2 JPEG Codec

SSI × 2 USBFS PDC

RTC

WDT/IWDT

Event link Data processing Analog

ELC ADC12 with
CRC SRC TSN
PGA × 2

Security DOC DAC12 ACMPHS × 6

SCE7

Figure 1.1 Block diagram

1.3 Part Numbering

Figure 1.2 shows product part number information, including memory capacity and package type. Table 1.14 shows a list
of products.

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S7G2 Datasheet 1. Overview

R 7 F S 7 G 2 7H 2 A 0 1 C B D # A C 0
Production identification code

Packing, Terminal material (Pb-free)

#AA: Tray/Sn (Tin) only
#AC: Tray/others

Package type
BD: BGA 224 pins
BG: BGA 176 pins
FC: LQFP 176 pins
FB: LQFP 144 pins
FP: LQFP 100 pins
LK: LGA 145 pins
Quality ID

Software ID

Operating temperature
2: -40 ° C to 85 ° C
3: -40 ° C to 105 ° C

Code flash memory size

G: 3 MB
H: 4 MB
Feature set
7: Superset

Group name
G2: S7G2 Group, Arm Cortex -M4, 240 MHz
Series name
7: High performance

Renesas Synergy ™ family

Flash memory

Renesas microcontroller unit

Renesas

Figure 1.2 Part numbering scheme

Table 1.14 Product list

Code Data
Part number Orderable part number Package flash flash SRAM Operating temperature
R7FS7G27H2A01CBD R7FS7G27H2A01CBD#AC0 PLBG0224GA-A 4 MB 64 KB 640 KB -40 to +85°C
R7FS7G27H2A01CBG R7FS7G27H2A01CBG#AC0 PLBG0176GE-A -40 to +85°C
R7FS7G27H3A01CFC R7FS7G27H3A01CFC#AA0 PLQP0176KB-A -40 to +105°C
R7FS7G27H2A01CLK R7FS7G27H2A01CLK#AC0 PTLG0145KA-A -40 to +85°C
R7FS7G27H3A01CFB R7FS7G27H3A01CFB#AA0 PLQP0144KA-B -40 to +105°C
R7FS7G27G2A01CBD R7FS7G27G2A01CBD#AC0 PLBG0224GA-A 3 MB -40 to +85°C
R7FS7G27G2A01CBG R7FS7G27G2A01CBG#AC0 PLBG0176GE-A -40 to +85°C
R7FS7G27G3A01CFC R7FS7G27G3A01CFC#AA0 PLQP0176KB-A -40 to +105°C
R7FS7G27G2A01CLK R7FS7G27G2A01CLK#AC0 PTLG0145KA-A -40 to +85°C
R7FS7G27G3A01CFB R7FS7G27G3A01CFB#AA0 PLQP0144KA-B -40 to +105°C
R7FS7G27G3A01CFP R7FS7G27G3A01CFP#AA0 PLQP0100KB-B -40 to +105°C

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S7G2 Datasheet 1. Overview

1.4 Function Comparison

Table 1.15 Functional comparison

Part numbers
R7FS7G27H2A01CBD/ R7FS7G27H2A01CBG/ R7FS7G27H3A01CFC/ R7FS7G27H2A01CLK/ R7FS7G27H3A01CFB/
Function R7FS7G27G2A01CBD R7FS7G27G2A01CBG R7FS7G27G3A01CFC R7FS7G27G2A01CLK R7FS7G27G3A01CFB R7FS7G27G3A01CFP

Pin count 224 176 176 145 144 100

Package BGA BGA LQFP LGA LQFP LQFP
Code flash memory 4/3 MB 3 MB
Data flash memory 64 KB
SRAM 640 KB
Parity 608 KB
DED 32 KB
Standby SRAM 8 KB
System CPU clock 240 MHz
Backup registers 512 bytes
ICU Yes
KINT 8
Event link ELC Yes
DMA DTC Yes
DMAC 8
BUS External bus 16-bit bus 8-bit bus
SDRAM Yes No
Timers GPT32EH 4 4 4 4 4 4
GPT32E 4 4 4 4 4 3
GPT32 6 6 6 6 6 5
AGT 2 2 2 2 2 2
RTC Yes
WDT/IWDT Yes
Communication SCI 10
IIC 3 2
SPI 2
SSI 2 1
QSPI 1 Dual-SPI 1
SDHI 2
CAN 2
USBFS Yes
USBHS Yes No
ETHERC 2 1
Analog ADC12 25 21 21 19 19 16
DAC12 2
ACMPHS 6
TSN Yes
HMI CTSU 18 12 12 18 12

KINT 8

Graphics GLCDC RGB888 RGB565

DRW Yes
JPEG Yes
PDC Yes No
Data processing CRC Yes
DOC Yes
SRC Yes
Security SCE7

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S7G2 Datasheet 1. Overview

1.5 Pin Functions

Table 1.16 Pin functions (1 of 5)

Function Signal I/O Description
Power supply VCC Input Power supply pin. Connect this pin to the system power supply. Connect it to
VSS through a 0.1-μF capacitor. Place the capacitor close to the pin.
VCC_DCDC Input Switching regulator power supply pin.
VLO I/O Switching regulator pin.
VCL0 to VCL2 Input Connect this pin to VSS through a smoothing capacitor used to stabilize the
VCL_F Input internal power supply. Place the capacitor close to the pin.
VSS Input Ground pin. Connect to the system power supply (0 V).
VBATT Input Backup power pin
Clock XTAL Output Pins for a crystal resonator. An external clock signal can be input through the
EXTAL Input EXTAL pin.
XCIN Input Input/output pins for the sub-clock oscillator. Connect a crystal resonator
XCOUT Output between XCOUT and XCIN.
EBCLK Output Outputs the external bus clock for external devices
SDCLK Output Outputs the SDRAM-dedicated clock
CLKOUT Output Clock output pin
Operating mode MD Input Pin for setting the operating mode. The signal level on this pin must not be
control changed during operation mode transition on release from the reset state.
System control RES Input Reset signal input pin. The MCU enters the reset state when this signal goes
low.
CAC CACREF Input Measurement reference clock input pin
Interrupt NMI Input Non-maskable interrupt request pin
IRQ0 to IRQ15 Input Maskable interrupt request pins
KINT KR00 to KR07 Input A key interrupt can be generated by inputting a falling edge to the key
interrupt input pins
On-chip emulator TMS I/O On-chip emulator or boundary scan pins
TDI Input
TCK Input
TDO Output
TCLK Output This pin outputs the clock for synchronization with the trace data
TDATA0 to TDATA3 Output Trace data output
SWDIO I/O Serial wire debug data input/output pin
SWCLK Input Serial wire clock pin
SWO Output Serial wire trace output pin
External bus RD Output Strobe signal indicating that reading from the external bus interface space is
interface in progress, active-low
WR Output Strobe signal indicating that writing to the external bus interface space is in
progress, in 1-write strobe mode, active-low
WR0, WR1 Output Strobe signals indicating that either group of data bus pins (D07 to D00 or
D15 to D08) is valid in writing to the external bus interface space, in byte
strobe mode, active-low
BC0, BC1 Output Strobe signals indicating that either group of data bus pins (D07 to D00 or
D15 to D08) is valid in access to the external bus interface space, in 1-write
strobe mode, active-low
WAIT Input Input pin for wait request signals in access to the external space, active-low
CS0 to CS7 Output Select signals for CS areas, active-low
A00 to A23 Output Address bus
D00 to D15 I/O Data bus

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Table 1.16 Pin functions (2 of 5)

Function Signal I/O Description
SDRAM interface CKE Output SDRAM clock enable signal
SDCS Output SDRAM chip select signal, active-low
RAS Output SDRAM low address strobe signal, active-low
CAS Output SDRAM column address strobe signal, active-low
WE Output SDRAM write enable signal, active-low
DQM0 Output SDRAM I/O data mask enable signal for DQ07 to DQ00
DQM1 Output SDRAM I/O data mask enable signal for DQ15 to DQ08
A00 to A15 Output Address bus
DQ00 to DQ15 I/O Data bus
GPT GTETRGA, Input External trigger input pins
GTETRGB,
GTETRGC,
GTETRGD
GTIOC0A to I/O Input capture, output compare, or PWM output pins.
GTIOC13A,
GTIOC0B to
GTIOC13B
GTIU Input Hall sensor input pin U
GTIV Input Hall sensor input pin V
GTIW Input Hall sensor input pin W
GTOUUP Output 3-phase PWM output for BLDC motor control (positive U phase)
GTOULO Output 3-phase PWM output for BLDC motor control (negative U phase)
GTOVUP Output 3-phase PWM output for BLDC motor control (positive V phase)
GTOVLO Output 3-phase PWM output for BLDC motor control (negative V phase)
GTOWUP Output 3-phase PWM output for BLDC motor control (positive W phase)
GTOWLO Output 3-phase PWM output for BLDC motor control (negative W phase)
AGT AGTEE0, AGTEE1 Input External event input enable signals
AGTIO0, AGTIO1 I/O External event input and pulse output pins
AGTO0, AGTO1 Output Pulse output pins
AGTOA0, AGTOA1 Output Output compare match A output pins
AGTOB0, AGTOB1 Output Output compare match B output pins
RTC RTCOUT Output Output pin for 1-Hz or 64-Hz clock
RTCIC0 to RTCIC2 Input Time capture event input pins
SCI SCK0 to SCK9 I/O Input/output pins for the clock (clock synchronous mode)
RXD0 to RXD9 Input Input pins for received data (asynchronous mode/clock synchronous mode)
TXD0 to TXD9 Output Output pins for transmitted data (asynchronous mode/clock synchronous
mode)
CTS0_RTS0 to I/O Input/output pins for controlling the start of transmission and reception
CTS9_RTS9 (asynchronous mode/clock synchronous mode), active-low
SCL0 to SCL9 I/O Input/output pins for the clock (simple IIC mode)
SDA0 to SDA9 I/O Input/output pins for the data (simple IIC mode)
SCK0 to SCK9 I/O Input/output pins for the clock (simple SPI mode)
MISO0 to MISO9 I/O Input/output pins for slave transmission of data (simple SPI mode)
MOSI0 to MOSI9 I/O Input/output pins for master transmission of data (simple SPI mode)
SS0 to SS9 Input Chip-select input pins (simple SPI mode), active-low
IIC SCL0 to SCL2 I/O Input/output pins for the clock
SDA0 to SDA2 I/O Input/output pins for data
SSI SSISCK0 I/O SSI serial bit clock pin
SSISCK1
SSIWS0 I/O Word select pins
SSIWS1
SSITXD0 Output Serial data output pins
SSIRXD0 Input Serial data input pins
SSIDATA1 I/O Serial data input/output pins
AUDIO_CLK Input External clock pin for audio (input oversampling clock)

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Table 1.16 Pin functions (3 of 5)

Function Signal I/O Description
SPI RSPCKA, RSPCKB I/O Clock input/output pin
MOSIA, MOSIB I/O Input or output pins for data output from the master
MISOA, MISOB I/O Input or output pins for data output from the slave
SSLA0, SSLB0 I/O Input or output pin for slave selection
SSLA1 to SSLA3, Output Output pins for slave selection
SSLB1 to SSLB3
QSPI QSPCLK Output QSPI clock output pin
QSSL Output QSPI slave output pin
QIO0 to QIO3 I/O Data0 to Data3
CAN CRX0, CRX1 Input Receive data
CTX0, CTX1 Output Transmit data
USBFS VCC_USB Input Power supply pins
VSS_USB Input Ground pins
USB_DP I/O D+ I/O pin of the USB on-chip transceiver. Connect this pin to the D+ pin of
the USB bus
USB_DM I/O D- I/O pin of the USB on-chip transceiver. Connect this pin to the D- pin of
the USB bus
USB_VBUS Input USB cable connection monitor pin. Connect this pin to VBUS of the USB
bus. The VBUS pin status (connected or disconnected) can be detected
when the USB module is operating as a function controller.
USB_EXICEN Output Low-power control signal for external power supply (OTG) chip
USB_VBUSEN Output VBUS (5 V) supply enable signal for external power supply chip
USB_OVRCURA, Input Connect the external overcurrent detection signals to these pins. Connect
USB_OVRCURB the VBUS comparator signals to these pins when the OTG power supply
chip is connected.
USB_ID Input Connect the MicroAB connector ID input signal to this pin during operation in
OTG mode
USBHS VCC_USBHS Input Power supply pin
VSS1_USBHS Input Ground pin
VSS2_USBHS Input Ground pin
AVCC_USBHS Input Analog power supply pin for the USBHS
AVSS_USBHS Input Analog ground pin for the USBHS. Must be shorted to the PVSS_USBHS
pin.
USBHS PVSS_USBHS Input PLL circuit ground pin for the USBHS. Must be shorted to the AVSS_USBHS
pin.
USBHS_RREF I/O USBHS reference current source pin. Connect this pin to the AVSS_USBHS
pin through a 2.2-k resistor (1%).
USBHS_DP I/O USB bus D+ data pin
USBHS_DM I/O USB bus D- data pin
USBHS_EXICEN Output Connect this pin to the OTG power supply IC
USBHS_ID Input Connect this pin to the OTG power supply IC
USBHS_VBUSEN Output VBUS power enable signal for USB
USBHS_OVRCURA, Input Overcurrent pin for USB
USBHS_OVRCURB
USBHS_VBUS Input USB cable connection monitor input pin

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Table 1.16 Pin functions (4 of 5)

Function Signal I/O Description
ETHERC REF50CK0, Input 50-MHz reference clocks. These pins input reference signals for
REF50CK1 transmission/reception timing in RMII mode.
RMII0_CRS_DV, Input Indicate carrier detection signals and valid receive data on RMII_RXD1 and
RMII1_CRS_DV RMII_RXD0 in RMII mode
RMII0_TXD0, Output 2-bit transmit data in RMII mode
RMII0_TXD1,
RMII1_TXD0,
RMII1_TXD1
RMII0_RXD0, Input 2-bit receive data in RMII mode
RMII0_RXD1,
RMII1_RXD0,
RMII1_RXD1
RMII0_TXD_EN, Output Output pins for data transmit enable signals in RMII mode
RMII1_TXD_EN
RMII0_RX_ER, Input Indicate an error occurred during reception of data in RMII mode
RMII1_RX_ER
ET0_CRS, ET1_CRS Input Carrier detection/data reception enable signals
ET0_RX_DV, Input Indicate valid receive data on ETn_ERXD3 to ETn_ERXD0 (n = 0, 1)
ET1_RX_DV
ET0_EXOUT, Output General-purpose external output pins
ET1_EXOUT
ET0_LINKSTA, Input Input link status from the PHY-LSI
ET1_LINKSTA
ET0_ETXD0 to Output 4 bits of MII transmit data
ET0_ETXD3,
ET1_ETXD0 to
ET1_ETXD3
ET0_ERXD0 to Input 4 bits of MII receive data
ET0_ERXD3,
ET1_ERXD0 to
ET1_ERXD3
ET0_TX_EN, Output Transmit enable signals. Function as signals indicating that transmit data is
ET1_TX_EN ready on ETn_ETXD3 to ETn_ETXD0 (n = 0, 1).
ET0_TX_ER, Output Transmit error pins. Function as signals notifying the PHY_LSI of an error
ET1_TX_ER during transmission.
ET0_RX_ER, Input Receive error pins. Function as signals to recognize an error during
ET1_RX_ER reception.
ET0_TX_CLK, Input Transmit clock pins. These pins input reference signals for output timing
ET1_TX_CLK from ETn_TX_EN, ETn_ETXD3 to ETn_ETXD0, and ETn_TX_ER (n = 0, 1).
ET0_RX_CLK, Input Receive clock pins. These pins input reference signals for input timing to
ET1_RX_CLK ETn_RX_DV, ETn_ERXD3 to ETn_ERXD0, and ETn_RX_ER (n = 0, 1).
ET0_COL, Input Input collision detection signals
ET1_COL
ET0_WOL, Output Receive Magic packets
ET1_WOL
ET0_MDC, Output Output reference clock signals for information transfer through ETn_MDIO
ET1_MDC (n = 0, 1)
ETHERC ET0_MDIO, I/O Input or output bidirectional signals for exchange of management data with
ET1_MDIO PHY-LSI
SDHI SD0CLK, SD1CLK Output SD clock output pins
SD0CMD, SD1CMD I/O Command output pin and response input signal pins
SD0DAT0 to I/O SD and MMC data bus pins
SD0DAT7,
SD1DAT0 to
SD1DAT7
SD0CD, SD1CD Input SD card detection pins
SD0WP, SD1WP Input SD write-protect signals

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S7G2 Datasheet 1. Overview

Table 1.16 Pin functions (5 of 5)

Function Signal I/O Description
Analog power AVCC0 Input Analog voltage supply pin. Connect this pin to VCC.
supply AVSS0 Input Analog ground pin. Connect this pin to VSS.
VREFH0 Input Analog reference voltage supply pin for the ADC12. Connect this pin to VCC
when not using the ADC12.
VREFL0 Input Analog reference ground pin for the ADC12. Connect this pin to VSS when
not using the ADC12.
VREFH Input Reference voltage input pin for the ADC12 (unit 1) and D/A converter. This is
used as the analog power supply for the respective modules. Connect this
pin to VCC if the ADC12 (unit 1) or DAC12 is not in use.
VREFL Input Reference ground pin for the ADC12 and D/A converter. This is used as the
analog ground for the respective modules. Set this pin to the same potential
as the VSS pin.
ADC12 AN000 to AN006, Input Input pins for the analog signals to be processed by the ADC12
AN016 to AN021
AN100 to AN106, Input
AN116 to AN120
ADTRG0 Input Input pins for the external trigger signals that start the A/D conversion,
ADTRG1 Input active-low
PGAVSS000/PGAVS Input Differential input pins
S100
DAC12 DA0, DA1 Output Output pins for the analog signals processed by the D/A converter
ACMPHS VCOUT Output Comparator output pin
IVREF0 to IVREF3 Input Reference voltage input pin for comparator
IVCMP0 to IVCMP2 Input Analog voltage input pins for comparator
CTSU TS00 to TS17 Input Capacitive touch detection pins (touch pins)
TSCAP - Secondary power supply pin for the touch driver
I/O ports P000 to P007 Input General-purpose input pins
P008 to P011, P014, I/O General-purpose input/output pins
P015
P100 to P115 I/O General-purpose input/output pins
P200 Input General-purpose input pin
P201 to P207, P212, I/O General-purpose input/output pins
P213
P300 to P315 I/O General-purpose input/output pins
P400 to P415 I/O General-purpose input/output pins
P500 to P515 I/O General-purpose input/output pins
P600 to P615 I/O General-purpose input/output pins
P700 to P713 I/O General-purpose input/output pins
P800 to P813 I/O General-purpose input/output pins
P900 to P915 I/O General-purpose input/output pins
PA00 to PA15 I/O General-purpose input/output pins
PB00 to PB07 I/O General-purpose input/output pins
GLCDC LCD_DATA00 to Output Data output pins for panel
LCD_DATA23
LCD_TCON0 to Output Output pins for panel timing adjustment
LCD_TCON3
LCD_CLK Output Panel clock output pin
LCD_EXTCLK Input Panel clock source input pin
PDC PIXCLK Input Image transfer clock pin
VSYNC Input Vertical synchronization signal pin
HSYNC Input Horizontal synchronization signal pin
PIXD0 to PIXD7 Input 8-bit image data pins
PCKO Output Output pin for dot clock

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S7G2 Datasheet 1. Overview

1.6 Pin Assignments

Figure 1.3 to Figure 1.8 show the pin assignments.

R 7FS 7G 2xxxA 01C B D

A B C D E F G H J K L M N P R

USBHS_ PVSS_ P 212

15 P 407 P 408 P410 P 708 VSS X C IN VC L0 P 707 P701 P 403 P 401 P511 15
DM USBHS /E X T A L

USBHS_ AVSS_ P 213

14 U S B _D P U SB_D M P409 P 411 P 415 XCOUT VBATT P 706 P700 P 402 P 514 P512 14
DP USBHS /X T A L

VCC_ VSS_ VCC_ USBHS_ AVCC_

13 P207 P 412 P 709 VSS PB 01 P 705 P405 P 400 P 513 P805 13
USB USB USBHS RREF USBHS

V SS 1_ VSS2_
12 P 202 P 203 P205 P 413 P 711 VCC PB05 PB 03 VCC P806 P 002 P 807 P000 12
USBHS USBHS

11 P 902 P 901 P315 P 204 P 414 P712 PB 07 PB 06 PB02 P 702 VSS P004 P 008 P 001 P005 11

10 VCL1 VSS VSS VCC P 313 P710 P 713 PB 04 P704 P 404 P 003 P010 P 011 P 006 P009 10

9 VLO VLO P904 P 903 P 900 P314 P 206 PB 00 P406 P 515 P 007 P014 AVSS0 V R EF L0 VREFH0 9

VCC_
8 P 200 P 2 0 1 /M D P 910 P 909 RES P 615 P 913 P703 P 809 VSS P015 VREFL AVCC0 VREFH 8
DCDC

7 P 911 P 912 P311 P 308 P 908 P907 PA 08 PA 13 PA00 P 808 VCC P508 P 510 VCC VSS 7

6 P 905 P 312 P310 P 307 P 915 P906 PA 11 PA 02 PA01 P 606 P 812 P506 P 507 P 509 VCL2 6

P 3 0 0 /T C K
5 VSS VCC P309 P 306 P 914 PA 12 PA 10 PA03 P 607 P 811 P505 P 502 P 503 P504 5
/S W C L K

4 VSS VCC P304 P 305 P 114 P608 P 609 PA 09 PA04 P 107 P 106 P804 P 501 P 803 P500 4

3 P 303 P 301 P112 P 113 P 115 P613 PA 14 VCC PA05 P 603 P 600 P105 P 104 P 810 P802 3

P 1 0 8 /T M S
2 P 302 P 1 1 0 /T D I VSS P 611 P612 PA 15 VSS PA06 P 604 P 601 VCC P 103 P 800 P801 2
/S W D IO

1 NC P 1 0 9 /T D O P111 VCC P 610 P614 P 813 VC L_F PA07 P 605 P 602 VSS P 102 P 101 P100 1

A B C D E F G H J K L M N P R

Figure 1.3 Pin assignment for 224-pin BGA (top view)

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S7G2 Datasheet 1. Overview

R7FS7G2xxxA01CBG

A B C D E F G H J K L M N P R

USBHS_ PVSS_ P212

15 P407 P409 P411 P414 VSS XCIN VCL0 P707 P703 P700 P405 P401 15
DM USBHS /EXTAL

USBHS_ AVSS_ P213

14 USB_DP USB_DM P410 P412 P415 XCOUT VBATT P706 P701 P406 P402 P512 14
DP USBHS /XTAL

VCC_ VSS_ VCC_ USBHS_ AVCC_

13 P204 P408 P413 VSS PB01 P704 P404 P400 P511 P805 13
USB USB USBHS RREF USBHS

VSS1_ VSS2_
12 P313 P202 P207 P206 P205 VCC PB00 P705 P702 P403 P513 P806 P000 12
USBHS USBHS

11 P900 P315 P314 P203 VCC P001 P004 P002 11

10 VCL1 VSS P901 VSS VSS P006 P008 P005 10

9 VLO VLO RES VCC P009 AVSS0 VREFL0 VREFH0 9

VCC_
8 P201/M D P200 P908 P010 AVCC0 VREFL VREFH 8
DCDC

7 P906 P905 P312 P907 VCC VSS P015 P014 7

6 P310 P309 P307 P311 P007 P507 P505 VCL2 6

5 P308 P305 VSS VCC P003 P503 P504 P506 5

P300/TCK
4 P306 P304 P111 VSS P613 PA09 PA 00 P607 VCC VSS VSS VCC P501 P502 4
/SW CLK

P108/TM S
3 P303 P302 P110/TDI VCC P610 VCC VSS P604 P603 P105 P102 P800 P804 P500 3
SW DIO

2 P301 P112 P114 P608 P611 P614 PA10 PA 01 P605 P601 P107 P104 P101 P802 P803 2

1 P109/TDO P113 P115 P609 P612 P615 PA08 VCL_F P606 P602 P600 P106 P103 P100 P801 1

A B C D E F G H J K L M N P R

Figure 1.4 Pin assignment for 176-pin BGA (top view)

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P108/TMS/SWDIO
P109/TDO
P110/TDI
VCL_F
PA00
PA01

PA10
PA09
PA08
P100
P101
P102
P103
P104
P105
P106
P107

P600
P601
P602
P603
P604
P605
P606
P607

P615
P614
P613
P612
P611
P610
P609
P608

P115
P114
P113
P112
P111
VCC

VCC

VCC
VSS

VSS

VSS
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
P800 133 88 P300/TCK/SWCLK
P801 134 87 P301
P802 135 86 P302
P803 136 85 P303
P804 137 84 VCC
VCC 138 83 VSS
VSS 139 82 P304
P500 140 81 P305
P501 141 80 P306
P502 142 79 P307
P503 143 78 P308
P504 144 77 P309
P505 145 76 P310
P506 146 75 P311
P507 147 74 P312
VCL2 148 73 P905
VCC 149 72 P906
VSS 150 71 P907
P015 151 70 P908
P014 152 69 P200
VREFL
VREFH
153
154 R7FS7G2xxxA01CFC 68
67
P201/MD
RES
AVCC0 155 66 VCC_DCDC
AVSS0 156 65 VLO
VREFL0 157 64 VLO
VREFH0 158 63 VSS
P010 159 62 VCL1
P009 160 61 VCC
P008 161 60 VSS
P007 162 59 P901
P006 163 58 P900
P005 164 57 P315
P004 165 56 P314
P003 166 55 P313
P002 167 54 P202
P001 168 53 P203
P000 169 52 P204
VSS 170 51 P205
VCC 171 50 P206
P806 172 49 P207
P805 173 48 VCC_USB
P513 174 47 USB_DP
P512 175 46 USB_DM
P511 176 45 VSS_USB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1
2
3
4
5
6
7
8
9

VSS

AVCC_USBHS

AVSS_USBHS
PVSS_USBHS
VSS2_USBHS

USBHS_DP
VSS1_USBHS
VCC_USBHS
VSS
P400
P401
P402
P403
P404
P405
P406
P700
P701
P702
P703
P704
P705
P706
P707
PB00
PB01

VCL0

P213/XTAL
P212/EXTAL

P415
P414
P413
P412
P411

P408
P407
VBATT

XCOUT

USBHS_RREF

USBHS_DM
XCIN

VCC

P410
P409

Figure 1.5 Pin assignment for 176-pin LQFP (top view)

R01DS0262EU0140 Rev.1.40 Page 20 of 116

Aug 6, 2018
S7G2 Datasheet 1. Overview

R7FS7G2xxxA01CLK

A B C D E F G H J K L M N

P212
13 P407 P409 P412 P708 P711 VCC XCIN VCL0 P702 P405 P402 P400 13
/EXTAL

P213
12 USB_DM USB_DP P410 P414 P710 VSS XCOUT VBATT P701 P404 P511 VCC 12
/XTAL

VCC_ VSS_
11 P207 P411 P415 P712 P705 P704 P703 P403 P401 P512 VSS 11
USB USB

10 P205 P206 P204 P408 P413 P709 P713 P700 P406 P003 P000 P002 P001 10

9 P203 P313 P202 VSS P004 P006 P009 P008 9

8 VCL1 VSS P200 VCC P005 AVSS0 VREFL0 VREFH0 8

7 VLO VLO RES P310 P007 AVCC0 VREFL VREFH 7

VCC_
6 P201/MD P312 P305 P505 P506 P015 P014 6
DCDC

5 P309 P311 P308 P303 NC P503 P504 VSS VCC 5

4 P307 P306 P304 P109/TDO P114 P608 P604 P600 P105 P500 P502 P501 VCL2 4

3 VSS VCC P301 P112 P115 P610 P614 P603 P107 P106 P104 VSS VCC 3

P300/TCK
2 P302 P111 VCC P609 P612 VSS P605 P601 VCC P800 P101 P801 2
/SWCLK

P108/TMS
1 P110/TDI P113 VSS P611 P613 VCC VCL_F P602 VSS P103 P102 P100 1
/SWDIO

A B C D E F G H J K L M N

Figure 1.6 Pin assignment for 145-pin LGA (top view)

R01DS0262EU0140 Rev.1.40 Page 21 of 116

Aug 6, 2018
S7G2 Datasheet 1. Overview

P108/TMS/SWDIO
P109/TDO
P110/TDI
VCL_F
P100
P101
P102
P103
P104
P105
P106
P107

P600
P601
P602
P603
P604
P605

P614
P613
P612
P611
P610
P609
P608

P115
P114
P113
P112
P111
VCC

VCC

VCC
VSS

VSS

VSS
108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73
P800 109 72 P300/TCK/SWCLK
P801 110 71 P301
VCC 111 70 P302
VSS 112 69 P303
P500 113 68 VCC
P501 114 67 VSS
P502 115 66 P304
P503 116 65 P305
P504 117 64 P306
P505 118 63 P307
P506 119 62 P308
VCL2 120 61 P309
VCC 121 60 P310
VSS 122 59 P311
P015 123 58 P312
P014 124 57 P200
VREFL 125 56 P201/MD
VREFH 126 R7FS7G2xxxA01CFB 55 RES
AVCC0 127 54 VCC_DCDC
AVSS0 128 53 VLO
VREFL0 129 52 VLO
VREFH0 130 51 VSS
P009 131 50 VCL1
P008 132 49 VCC
P007 133 48 VSS
P006 134 47 P313
P005 135 46 P202
P004 136 45 P203
P003 137 44 P204
P002 138 43 P205
P001 139 42 P206
P000 140 41 P207
VSS 141 40 VCC_USB
VCC 142 39 USB_DP
P512 143 38 USB_DM
P511 144 37 VSS_USB
10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36
1

XCIN

VCC
VSS
VBATT

XCOUT
P400
P401
P402
P403
P404
P405
P406
P700
P701
P702
P703
P704
P705

VCL0

P213/XTAL
P212/EXTAL

P713
P712
P711
P710
P709
P708
P415
P414
P413
P412

P409
P408
P407
P411
P410

Figure 1.7 Pin assignment for 144-pin LQFP (top view)

R01DS0262EU0140 Rev.1.40 Page 22 of 116

Aug 6, 2018
S7G2 Datasheet 1. Overview

P108/TMS/SWDIO
P109/TDO
P110/TDI
VCL_F
P100
P101
P102
P103
P104
P105
P106
P107
P600
P601
P602

P610
P609
P608
P115
P114
P113
P112
P111
VCC
VSS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P500 76 50 P300/TCK/SWCLK
P501 77 49 P301
P502 78 48 P302
P503 79 47 P303
P504 80 46 VCC
VCL2 81 45 VSS
VCC 82 44 P304
VSS 83 43 P305
P015 84 42 P306
P014 85 41 P307
VREFL 86 40 P200
VREFH 87 39 P201/MD
AVCC0
AVSS0
88
89
R7FS7G2xxxA01CFP 38
37
RES
VCC_DCDC
VREFL0 90 36 VLO
VREFH0 91 35 VLO
P008 92 34 VSS
P007 93 33 VCL1
P006 94 32 P205
P005 95 31 P206
P004 96 30 P207
P003 97 29 VCC_USB
P002 98 28 USB_DP
P001 99 27 USB_DM
P000 100 26 VSS_USB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9

XCIN

VCC
VBATT

XCOUT
VSS
P400
P401
P402
P403
P404
P405
P406

VCL0

P213/XTAL
P212/EXTAL

P708
P415
P414
P413
P412
P411
P410
P409
P408
P407

Figure 1.8 Pin assignment for 100-pin LQFP (top view)

R01DS0262EU0140 Rev.1.40 Page 23 of 116

Aug 6, 2018
S7G2 Datasheet 1. Overview

1.7 Pin Lists

Table 1.17 Pin list (1 of 10)

Pin number Extbus Timers Communication interfaces Analog HMI

CLK, Debug, CAC

Power, System,

GLCDC, PDC
External bus

SCI0,2,4,6,8

SCI1,3,5,7,9

SPI, QSPI
LQFP176

LQFP144

LQFP100

ACMPHS
Interrupt

(30 MHz)

(30 MHz)

(25 MHz)

(50 MHz)
BGA224

BGA176

LGA145

USBFS,
SDRAM
I/O port

DAC12,
USBHS

ADC12

CTSU
SDHI
CAN
AGT

RMII
GPT

GPT

RTC

SSI
MII
IIC
N13 N13 1 N13 1 1 - IRQ P400 - - - - GTI - - SCK SCK SCL - AU ET1 - - - AD - - -
0 OC 4_B 7_A 0_A DIO _TX TR
6A_ _CL _CL G1
A K K _B
P15 R15 2 L11 2 2 - IRQ P401 - - - GTE GTI - CTX CTS TXD SDA - - ET0 ET0 - - - - - -
5- TRG OC 0_B 4_R 7_A/ 0_A _M _M
DS A_B 6B_ TS4 MO DC DC
A _B/S SI7_
S4_ A/S
B DA7
_A
N14 P14 3 M13 3 3 - IRQ P402 - - AGT - - RTC CRX - RXD - - - ET0 ET0 - - - - - -
4- IO0_ IC0 0_B 7_A/ _M _M
DS B/A MIS DIO DIO
GTI O7_
O1_ A/S
B CL7
_A
N15 M12 4 K11 4 4 - - P403 - - AGT - GTI RTC - - CTS - - SSI ET1 ET1 - - - - - PIX
IO0_ OC IC1 7_R SC _M _M D7
C/A 3A_ TS7 K0_ DC DC
GTI B _A/ A
O1_ SS7
C _A
K10 M13 5 L12 5 5 - - P404 - - - - GTI RTC - - - - - SSI ET1 ET1 - - - - - PIX
OC IC2 WS _M _M D6
3B_ 0_A DIO DIO
B
M13 P15 6 L13 6 6 - - P405 - - - - GTI - - - - - - SSI ET1 RMI - - - - - PIX
OC TX _TX I1_ D5
1A_ D0_ _E TX
B A N D_
EN
J9 N14 7 J10 7 7 - - P406 - - - - GTI - - - - - - SSI ET1 RMI - - - - - PIX
OC RX _R I1_ D4
1B_ D0_ X_ TX
B A ER D1
M14 N15 8 H10 8 - - - P700 - - - - GTI - - - - - - - ET1 RMI - - - - - PIX
OC _ET I1_ D3
5A_ XD TX
B 1 D0
M15 M14 9 K12 9 - - - P701 - - - - GTI - - - - - - - ET1 RE - - - - - PIX
OC _ET F50 D2
5B_ XD CK
B 0 1
K11 L12 10 K13 10 - - - P702 - - - - GTI - - - - - - - ET1 RMI - - - - - PIX
OC _E I1_ D1
6A_ RX RX
B D1 D0
J8 M15 11 J11 11 - - - P703 - - - - GTI - - - - - - - ET1 RMI - - - - - PIX
OC _E I1_ D0
6B_ RX RX
B D0 D1
J10 L13 12 H11 12 - - - P704 - - - - - - - - - - - - ET1 RMI - - - - - HSY
_R I1_ NC
X_ RX
CL _E
K R
L13 K12 13 G11 13 - - - P705 - - - - - - - - - - - - ET1 RMI - - - - - PIX
_C I1_ CLK
RS CR
S_
DV
L14 L14 14 - - - - IRQ P706 - - - - - - - - RXD - - - - - USB - - - - -
7 3_B/ HS_
MIS OVR
O3_ CUR
B/S B
CL3
_B
L15 L15 15 - - - - IRQ P707 - - - - - - - - TXD - - - - - USB - - - - -
8 3_B/ HS_
MO OVR
SI3_ CUR
B/S A
DA3
_B
H9 J12 16 - - - - PB0 - - - - - - - - SCK - - - - - USB - - - - -
0 3_B HS_
VBU
SEN
J11 - - - - - - PB0 - - - - - - - CTS - - - - ET1 - - - - - - -
2 8_R _R
TS8 X_
_B/S DV
S8_
B

R01DS0262EU0140 Rev.1.40 Page 24 of 116

Aug 6, 2018
S7G2 Datasheet 1. Overview

Table 1.17 Pin list (2 of 10)

Pin number Extbus Timers Communication interfaces Analog HMI

CLK, Debug, CAC

Power, System,

GLCDC, PDC
External bus

SCI0,2,4,6,8

SCI1,3,5,7,9

SPI, QSPI
LQFP176

LQFP144

LQFP100

ACMPHS
Interrupt

(30 MHz)

(30 MHz)

(25 MHz)

(50 MHz)
BGA224

BGA176

LGA145

USBFS,
SDRAM
I/O port

DAC12,
USBHS

ADC12

CTSU
SDHI
CAN
AGT

RMII
GPT

GPT

RTC

SSI
MII
IIC
K12 - - - - - - PB0 - - - - - - - SCK - - - - ET1 - - - - - - -
3 8_B _C
OL
H10 - - - - - - IRQ PB0 - - - - - - - TXD - - - - ET1 - - - - - - -
12 4 8_B/ _E
MO RX
SI8_ D2
B/S
DA8
_B
K13 K13 17 - - - - PB0 - - - - - - - - CTS - - - - - USB - - - - -
1 3_R HS_
TS3 VBU
_B/ S
SS3
_B
J12 - - - - - - IRQ PB0 - - - - - - - RXD - - - - ET1 - - - - - - -
13 5 8_B/ _E
MIS RX
O8_ D3
B/S
CL8
_B
H11 - - - - - - - PB0 - - - - - - - - - - - ET1 ET1 - - - - - -
6 _W _W
OL OL
G11 - - - - - - - PB0 - - - - - - - - - - - ET1 ET1 - - - - - -
7 _LI _LI
NK NK
STA STA
K14 K14 18 J12 14 8 VBA - - - - - - - - - - - - - - - - - - - - - -
TT
K15 K15 19 J13 15 9 VCL - - - - - - - - - - - - - - - - - - - - - -
0
J15 J15 20 H13 16 10 XCI - - - - - - - - - - - - - - - - - - - - - -
N
J14 J14 21 H12 17 11 XCO - - - - - - - - - - - - - - - - - - - - - -
UT
J13 J13 22 F12 18 12 VSS - - - - - - - - - - - - - - - - - - - - - -
H14 H14 23 G12 19 13 XTA IRQ P213 - - - GTE - - - - TXD - - - - - - - AD - - -
L 2 TRG 1_A/ TR
C_A MO G1
SI1_ _A
A/S
DA1
_A
H15 H15 24 G13 20 14 EXT IRQ P212 - - AGT GTE - - - - RXD - - - - - - - - - - -
AL 3 EE1 TRG 1_A/
D_A MIS
O1_
A/S
CL1
_A
H12 H12 25 F13 21 15 VCC - - - - - - - - - - - - - - - - - - - - - -
H13 H13 26 - - - AVC - - - - - - - - - - - - - - - - - - - - - -
C_U
SBH
S
G13 G13 27 - - - USB - - - - - - - - - - - - - - - - - - - - - -
HS_
RRE
F
G14 G14 28 - - - AVS - - - - - - - - - - - - - - - - - - - - - -
S_U
SBH
S
G15 G15 29 - - - PVS - - - - - - - - - - - - - - - - - - - - - -
S_U
SBH
S
G12 G12 30 - - - VSS - - - - - - - - - - - - - - - - - - - - - -
2_U
SBH
S
F15 F15 31 - - - - - - - - - - - - - - - - - - - - USB - - - - -
HS_
DM
F14 F14 32 - - - - - - - - - - - - - - - - - - - - USB - - - - -
HS_
DP
F12 F12 33 - - - VSS - - - - - - - - - - - - - - - - - - - - - -
1_U
SBH
S
F13 F13 34 - - - VCC - - - - - - - - - - - - - - - - - - - - - -
_US
BHS
E15 E15 35 - - - VSS - - - - - - - - - - - - - - - - - - - - -

R01DS0262EU0140 Rev.1.40 Page 25 of 116

Aug 6, 2018
S7G2 Datasheet 1. Overview

Table 1.17 Pin list (3 of 10)

Pin number Extbus Timers Communication interfaces Analog HMI

CLK, Debug, CAC

Power, System,

GLCDC, PDC
External bus

SCI0,2,4,6,8

SCI1,3,5,7,9

SPI, QSPI
LQFP176

LQFP144

LQFP100

ACMPHS
Interrupt

(30 MHz)

(30 MHz)

(25 MHz)

(50 MHz)
BGA224

BGA176

LGA145

USBFS,
SDRAM
I/O port

DAC12,
USBHS

ADC12

CTSU
SDHI
CAN
AGT

RMII
GPT

GPT

RTC

SSI
MII
IIC
G10 - - G10 22 - - - P713 - - - - GTI - - - - - - - ET1 ET1 - - - - TS1 -
OC _E _E 7
2A_ XO XO
B UT UT
F11 - - F11 23 - - - P712 - - - - GTI - - - - - - - - - - - - - TS1 -
OC 6
2B_
B
E12 - - E13 24 - - - P711 - - - - - - - - CTS - - - ET0 - - - - - TS1 -
1_R _TX 5
TS1 _CL
_B/ K
SS1
_B
F10 - - E12 25 - - - P710 - - - - - - - - SCK - - - ET0 - - - - - TS1 -
1_B _TX 4
_E
R
E13 - - F10 26 - - IRQ P709 - - - - - - - - TXD - - - ET0 - - - - - TS1 -
10 1_B/ _ET 3
MO XD
SI1_ 2
B/S
DA1
_B
D15 - - D13 27 16 CAC IRQ P708 - - - - - - - - RXD - SS - ET0 - - - - - TS1 -
REF 11 1_B/ LA3 _ET 2
_B MIS _B XD
O1_ 3
B/S
CL1
_B
E14 E14 36 E11 28 17 - - P415 - - - - - - - - - - SS - ET0 RMI - - - - TS1 -
LA2 _TX I0_ 1
_B _E TX
N D_
EN
E11 D15 37 D12 29 18 - - P414 - - - - - - - - - - SS - ET0 RMI - SD0 - - TS1 -
LA1 _R I0_ WP 0
_B X_ TX
ER D1
D12 E13 38 E10 30 19 - - P413 - - - GTO - - - CTS - - SS - ET0 RMI - SD0 - - TS0 -
UUP 0_R LA0 _ET I0_ CLK 9
_B TS0 _B XD TX
_B/S 1 D0
S0_
B
D13 D14 39 C13 31 20 - - P412 - - - GTO - - - SCK - - RS - ET0 RE - SD0 - - TS0 -
ULO 0_B PC _ET F50 CM 8
_B KA XD CK D
_B 0 0
D14 C15 40 D11 32 21 - IRQ P411 - - AGT GTO GTI - - TXD CTS - MO - ET0 RMI - SD0 - - TS0 -
4 OA1 VUP OC 0_B/ 3_R SIA _E I0_ DAT 7
_B 9A_ MO TS3 _B RX RX 0
A SI0_ _A/ D1 D0
B/S SS3
DA0 _A
_B
C15 C14 41 C12 33 22 - IRQ P410 - - AGT GTO GTI - - RXD SCK - MIS - ET0 RMI - SD0 - - TS0 -
5 OB1 VLO OC 0_B/ 3_A OA _E I0_ DAT 6
_B 9B_ MIS _B RX RX 1
A O0_ D0 D1
B/S
CL0
_B
C14 B15 42 B13 34 23 - IRQ P409 - - - GTO GTI - USB - TXD - - - ET0 RMI USB - - - TS0 -
6 WU OC _EXI 3_A/ _R I0_ HS_ 5
P_B 10A CEN MO X_ RX EXIC
_A _A SI3_ CL _E EN
A/S K R
DA3
_A
B15 D13 43 D10 35 24 - IRQ P408 - - - GTO GTI - USB - RXD - - - ET0 RMI USB - - - TS0 -
7 WL OC _ID_ 3_A/ _C I0_ HS_I 4
O_B 10B A MIS RS CR D
_A O3_ S_
A/S DV
CL3
_A
A15 A15 44 A13 36 25 - - P407 - - - - - RTC USB CTS - SDA SS - ET0 ET0 - - AD - TS0 -
OUT _VB 4_R 0_B LB3 _E _E TR 3
US TS4 _A XO XO G0
_A/S UT UT
S4_
A
B13 C13 45 B11 37 26 VSS - - - - - - - - - - - - - - - - - - - - - -
_US
B
B14 B14 46 A12 38 27 - - - - - - - - USB - - - - - - - - - - - - -
_DM
A14 A14 47 B12 39 28 - - - - - - - - USB - - - - - - - - - - - - -
_DP

R01DS0262EU0140 Rev.1.40 Page 26 of 116

Aug 6, 2018
S7G2 Datasheet 1. Overview

Table 1.17 Pin list (4 of 10)

Pin number Extbus Timers Communication interfaces Analog HMI

CLK, Debug, CAC

Power, System,

GLCDC, PDC
External bus

SCI0,2,4,6,8

SCI1,3,5,7,9

SPI, QSPI
LQFP176

LQFP144

LQFP100

ACMPHS
Interrupt

(30 MHz)

(30 MHz)

(25 MHz)

(50 MHz)
BGA224

BGA176

LGA145

USBFS,
SDRAM
I/O port

DAC12,
USBHS

ADC12

CTSU
SDHI
CAN
AGT

RMII
GPT

GPT

RTC

SSI
MII
IIC
A13 B13 48 A11 40 29 VCC - - - - - - - - - - - - - - - - - - - - - -
_US
B
C13 C12 49 C11 41 30 - - P207 A17 - - - - - - - - - SS - - - - - - - TS0 -
LB2 2
_A
G9 D12 50 B10 42 31 - IRQ P206 WAIT - - GTI - - USB RXD - SDA SS SSI ET0 ET0 - SD0 - - TS0 -
0- U_A _VB 4_A/ 1_A LB1 DA _LI _LI DAT 1
DS USE MIS _A TA1 NK NK 2
N_A O4_ _A STA STA
A/S
CL4
_A
C12 E12 51 A10 43 32 CLK IRQ P205 A16 - AGT GTI GTI - USB TXD CTS SCL SS SSI ET0 ET0 - SD0 - - TSC -
OUT 1- O1 V_A OC _OV 4_A/ 9_R 1_A LB0 WS _W _W DAT AP_
_A DS 4A_ RCU MO TS9 _A 1_A OL OL 3 A
B RA_ SI4_ _A/
A- A/S SS9
DS DA4 _A
_A
D11 A13 52 C10 44 - CAC - P204 A18 - AGT GTI GTI - USB SCK SCK SCL RS SSI ET0 - - SD0 - - TS0 -
REF IO1_ W_A OC _OV 4_A 9_A 0_B PC SC _R DAT 0
_A A 4B_ RCU KB K1_ X_ 4
B RB_ _A A DV
A-
DS
B12 D11 53 A9 45 - - IRQ P203 A19 - - - GTI - CTX CTS TXD - MO - ET0 - - SD0 - - TSC -
2- OC 0_A 2_R 9_A/ SIB _C DAT AP_
DS 5A_ TS2 MO _A OL 5 B
A _A/S SI9_
S2_ A/S
A DA9
_A
A12 B12 54 C9 46 - - IRQ P202 WR1/ - - - GTI - CRX SCK RXD - MIS ET0 - - SD0 - - - LCD
3- BC1 OC 0_A 2_A 9_A/ OB _E DAT _TC
DS 5B_ MIS _A RX 6 ON3
A O9_ D2 _B
A/S
CL9
_A
E10 A12 55 B9 47 - - - P313 A20 - - - - - - - - - - - ET0 - - SD0 - - - LCD
_E DAT _TC
RX 7 ON2
D3 _B
F9 C11 56 - - - - - P314 A21 - - - - - - - - - - - - - - - - - - LCD
_TC
ON1
_B
C11 B11 57 - - - - - P315 A22 - - - - - - - - - - - - - - - - - - LCD
_TC
ON0
_B
E9 A11 58 - - - - - P900 A23 - - - - - - - - - - - - - - - - - - LCD
_CL
K_B
B11 C10 59 - - - - - P901 - - - - - - - - - - - - - - - - - - LCD
_DA
TA1
5_B
A11 - - - - - - - P902 - - - - - - - - - - - - - - - - - - - LCD
_DA
TA2
3_B
C10 D10 60 D9 48 - VSS - - - - - - - - - - - - - - - - - - - - - -
D10 D9 61 D8 49 - VCC - - - - - - - - - - - - - - - - - - - - - -
D9 - - - - - - - P903 - - - - GTI - - - - - - - - - - SD0 - - - -
OC CD
7A_
B
C9 - - - - - - - P904 - - - - GTI - - - - - - - - - - - - - - -
OC
7B_
B
A10 A10 62 A8 50 33 VCL - - - - - - - - - - - - - - - - - - - - - -
1
B10 B10 63 B8 51 34 VSS - - - - - - - - - - - - - - - - - - - - - -
A9 A9 64 A7 52 35 VLO - - - - - - - - - - - - - - - - - - - - - -
B9 B9 65 B7 53 36 VLO - - - - - - - - - - - - - - - - - - - - - -
A8 A8 66 A6 54 37 VCC - - - - - - - - - - - - - - - - - - - - - -
_DC
DC
H8 - - - - - - P913 - - - - - - - - - - - - - - - - - - - -
F8 C9 67 C7 55 38 RES - - - - - - - - - - - - - - - - - - - - -
C8 B8 68 B6 56 39 MD - P201 - - - - - - - - - - - - - - - - - - - -
B8 C8 69 C8 57 40 - NMI P200 - - - - - - - - - - - - - - - - - - - -

R01DS0262EU0140 Rev.1.40 Page 27 of 116

Aug 6, 2018
S7G2 Datasheet 1. Overview

Table 1.17 Pin list (5 of 10)

Pin number Extbus Timers Communication interfaces Analog HMI

CLK, Debug, CAC

Power, System,

GLCDC, PDC
External bus

SCI0,2,4,6,8

SCI1,3,5,7,9

SPI, QSPI
LQFP176

LQFP144

LQFP100

ACMPHS
Interrupt

(30 MHz)

(30 MHz)

(25 MHz)

(50 MHz)
BGA224

BGA176

LGA145

USBFS,
SDRAM
I/O port

DAC12,
USBHS

ADC12

CTSU
SDHI
CAN
AGT

RMII
GPT

GPT

RTC

SSI
MII
IIC
B7 - - - - - - - P912 - - - - GTI - - - - - - - - - - - - - - -
OC
8A_
B
A7 - - - - - - - P911 - - - - GTI - - - - - - - - - - - - - - -
OC
8B_
B
D8 - - - - - - - P910 - - - - - - - - - - - - - - - - - - - LCD
_DA
TA2
2_B
E8 - - - - - - - P909 - - - - - - - - - - - - - - - - - - - LCD
_DA
TA2
1_B
E7 D8 70 - - - - - P908 CS7 - - - - - - - - - - - - - - - - - - LCD
_DA
TA1
4_B
F7 D7 71 - - - - - P907 CS6 - - - - - - - - - - - - - - - - - - LCD
_DA
TA1
3_B
F6 A7 72 - - - - - P906 CS5 - - - - - - - - - - - - - - - - - - LCD
_DA
TA1
2_B
A6 B7 73 - - - - - P905 CS4 - - - - - - - - - - - - - - - - - - LCD
_DA
TA1
1_B
B6 C7 74 C6 58 - - - P312 CS3 CA - - - - - - - - - - - - - - - - - -
S
C7 D6 75 B5 59 - - - P311 CS2 RA - - - - - - - - - - - - - - - - - LCD
S _DA
TA2
3_A
A4 - - - - - VSS - - - - - - - - - - - - - - - - - - - - - -
B4 - - - - - VCC - - - - - - - - - - - - - - - - - - - - - -
C6 A6 76 D7 60 - - - P310 A15 A15 - - - - - - - - - - - - - - - - - LCD
_DA
TA2
2_A
C5 B6 77 A5 61 - - - P309 A14 A14 - - - - - - - - - - - - - - - - - LCD
_DA
TA2
1_A
D7 A5 78 C5 62 - - - P308 A13 A13 - - - - - - - - - - - - - - - - - LCD
_DA
TA2
0_A
D6 C6 79 A4 63 41 - - P307 A12 A12 - - - - - CTS - - - - - - - - - - - LCD
6_R _DA
TS6 TA1
_A/S 9_A
S6_
A
D5 A4 80 B4 64 42 - - P306 A11 A11 - - - - - SCK - - - - - - - - - - - LCD
6_A _DA
TA1
8_A
D4 B5 81 D6 65 43 - IRQ P305 A10 A10 - - - - - TXD - - - - - - - - - - - LCD
8 6_A/ _DA
MO TA1
SI6_ 7_A
A/S
DA6
_A
C4 B4 82 C4 66 44 - IRQ P304 A09 A09 - - GTI - - RXD - - - - - - - - - - - LCD
9 OC 6_A/ _DA
7A_ MIS TA1
A O6_ 6_A
A/S
CL6
_A
A5 C5 83 A3 67 45 VSS - - - - - - - - - - - - - - - - - - - - - -
B5 D5 84 B3 68 46 VCC - - - - - - - - - - - - - - - - - - - - - -
E6 - - - - - - - P915 - - - - - - - - - - - - - - - - - - - LCD
_DA
TA2
0_B
E5 - - - - - - - P914 - - - - - - - - - - - - - - - - - - - LCD
_DA
TA1
9_B
A3 A3 85 D5 69 47 - - P303 A08 A08 - - GTI - - - - - - - - - - - - - - LCD
OC _DA
7B_ TA1
A 5_A

R01DS0262EU0140 Rev.1.40 Page 28 of 116

Aug 6, 2018
S7G2 Datasheet 1. Overview

Table 1.17 Pin list (6 of 10)

Pin number Extbus Timers Communication interfaces Analog HMI

CLK, Debug, CAC

Power, System,

GLCDC, PDC
External bus

SCI0,2,4,6,8

SCI1,3,5,7,9

SPI, QSPI
LQFP176

LQFP144

LQFP100

ACMPHS
Interrupt

(30 MHz)

(30 MHz)

(25 MHz)

(50 MHz)
BGA224

BGA176

LGA145

USBFS,
SDRAM
I/O port

DAC12,
USBHS

ADC12

CTSU
SDHI
CAN
AGT

RMII
GPT

GPT

RTC

SSI
MII
IIC
A2 B3 86 A2 70 48 - IRQ P302 A07 A07 - GTO GTI - - TXD - - SS - - - - - - - - LCD
5 UUP OC 2_A/ LB3 _DA
_A 4A_ MO _B TA1
A SI2_ 4_A
A/S
DA2
_A
B3 A2 87 C3 71 49 - IRQ P301 A06 A06 - GTO GTI - - RXD - - SS - - - - - - - - LCD
6 ULO OC 2_A/ LB2 _DA
_A 4B_ MIS _B TA1
A O2_ 3_A
A/S
CL2
_A
F5 C4 88 B2 72 50 TCK/ - P300 - - - - GTI - - - - - SS - - - - - - - - -
SW OC LB1
CLK 0A_ _B
A
B2 C3 89 A1 73 51 TMS - P108 - - - - GTI - - - CTS - SS - - - - - - - - -
/SW OC 9_R LB0
DIO 0B_ TS9 _B
A _B/
SS9
_B
B1 A1 90 D4 74 52 CLK - P109 - - - GTO GTI - CTX - TXD - MO - - - - - - - - -
OUT VUP OC 1_A 9_B/ SIB
_B/T _A 1A_ MIS _B
DO/ A O9_
SW B/S
O DA9
_B
C2 D3 91 B1 75 53 TDI IRQ P110 - - - GTO GTI - CRX CTS RXD - MIS - - - - - - VCO - -
3 VLO OC 1_A 2_R 9_B/ OB UT
_A 1B_ TS2 MIS _B
A _B/S O9_
S2_ B/S
B CL9
_B
C1 D4 92 C2 76 54 - IRQ P111 A05 A05 - - GTI - - SCK SCK - RS - - - - - - - - LCD
4 OC 2_B 9_B PC _DA
3A_ KB TA1
A _B 2_A
C3 B2 93 D3 77 55 - - P112 A04 A04 - - GTI - - TXD - - - SSI - - - - - - LCD
OC 2_B/ SC _DA
3B_ MO K0_ TA1
A SI2_ B 1_A
B/S
DA2
_B
D3 B1 94 C1 78 56 - - P113 A03 A03 - - - - - RXD - - - SSI - - - - - - LCD
2_B/ WS _DA
MIS 0_B TA1
O2_ 0_A
B/S
CL2
_B
E4 C2 95 E4 79 57 - - P114 A02 A02 - - - - - - - - - SSI - - - - - - LCD
RX _DA
D0_ TA0
B 9_A
E3 C1 96 E3 80 58 - - P115 A01 A01 - - - - - - - - - SSI - - - - - - LCD
TX _DA
D0_ TA0
B 8_A
D1 E3 97 D2 81 - VCC - - - - - - - - - - - - - - - - - - - - -
D2 E4 98 D1 82 - VSS - - - - - - - - - - - - - - - - - - - - -
F4 D2 99 F4 83 59 - - P608 A00/ A00 - - - - - - - - - - - - - - - - - LCD
BC0 /DQ _DA
M1 TA0
7_A
G4 D1 100 E2 84 60 - - P609 CS1 CK - - - - - - - - - - - - - - - - - LCD
E _DA
TA0
6_A
E1 F3 101 F3 85 61 - - P610 CS0 WE - - - - - - - - - - - - - - - - - LCD
_DA
TA0
5_A
E2 E2 102 E1 86 - - - P611 SD - - - - - - - - - - - - - - - - - -
CS
F2 E1 103 F2 87 - - - P612 D08 DQ - - - - - - - - - - - - - - - - - -
08
F3 F4 104 F1 88 - - - P613 D09 DQ - - - - - - - - - - - - - - - - - -
09
F1 F2 105 G3 89 - - - P614 D10 DQ - - - - - - - - - - - - - - - - - -
10
G8 F1 106 - - - - - P615 - - - - - - - - - - - - - - - - - - - LCD
_DA
TA1
0_B

R01DS0262EU0140 Rev.1.40 Page 29 of 116

Aug 6, 2018
S7G2 Datasheet 1. Overview

Table 1.17 Pin list (7 of 10)

Pin number Extbus Timers Communication interfaces Analog HMI

CLK, Debug, CAC

Power, System,

GLCDC, PDC
External bus

SCI0,2,4,6,8

SCI1,3,5,7,9

SPI, QSPI
LQFP176

LQFP144

LQFP100

ACMPHS
Interrupt

(30 MHz)

(30 MHz)

(25 MHz)

(50 MHz)
BGA224

BGA176

LGA145

USBFS,
SDRAM
I/O port

DAC12,
USBHS

ADC12

CTSU
SDHI
CAN
AGT

RMII
GPT

GPT

RTC

SSI
MII
IIC
G7 G1 107 - - - - - PA0 - - - - - - - - - - - - - - - - - - - LCD
8 _DA
TA0
9_B
G6 - - - - - - - PA11 - - - - - - - - - - - - - - - - - - - LCD
_DA
TA1
8_B
G5 - - - - - TCL - PA1 - - - - - - - - - - - - - - - - - - -
K 2
H4 G4 108 - - - - - PA0 - - - - - - - - - - - - - - - - - - - LCD
9 _DA
TA0
8_B
H7 - - - - - TDA - PA1 - - - - - - - - - - - - - - - - - - - -
TA0 3
G3 - - - - - TDA - PA1 - - - - - - - - - - - - - - - - - - - -
TA1 4
H5 G2 109 - - - - - PA1 - - - - - - - - - - - - - - - - - - - LCD
0 _DA
TA0
7_B
G2 - - - - - TDA - PA1 - - - - GTI - - - - - - - - - - - - - - -
TA2 5 OC
9A_
B
G1 - - - - - TDA - P813 - - - - GTI - - - - - - - - - - - - - - -
TA3 OC
9B_
B
H3 G3 110 G1 90 62 VCC - - - - - - - - - - - - - - - - - - - - - -
H2 H3 111 G2 91 63 VSS - - - - - - - - - - - - - - - - - - - - - -
H1 H1 112 H1 92 64 VCL - - - - - - - - - - - - - - - - - - - - - -
_F
J1 - - - - - - PA0 - - - - GTI - - - - - - - - - - - - - - -
7 OC
10A
_B
J2 - - - - - - PA0 - - - - GTI - - - - - - - - - - - - - - -
6 OC
10B
_B
J3 - - - - - - PA0 - - - - GTI - - - CTS - - - - - - - - - - -
5 OC 7_R
11A TS7
_B _B/
SS7
_B
J4 - - - - - - PA0 - - - - GTI - - - SCK - - - - - - - - - - -
4 OC 7_B
11B
_B
J5 - - - - - IRQ PA0 - - - - - - - - RXD - - - - - - - - - - -
9 3 7_B/
MIS
O7_
B/S
CL7
_B
H6 - - - - - IRQ PA0 - - - - - - - - TXD - - - - - - - - - - -
10 2 7_B/
MO
SI7_
B/S
DA7
_B
J6 H2 113 - - - - PA0 - - - - - - - - - - - - - - - - - - - LCD
1 _DA
TA0
6_B
J7 H4 114 - - - - PA0 - - - - - - - - - - - - - - - - - - - LCD
0 _DA
TA0
5_B
K5 J4 115 - - - - P607 - - - - - - - - - - - - - - - - - - - LCD
_DA
TA0
4_B
K6 J1 116 - - - - P606 - - - - - - - - - - - - - - - - - - - LCD
_DA
TA0
3_B
K1 J2 117 H2 93 - - P605 D11 DQ - - - - - - - - - - - - - - - - - -
11
K2 J3 118 G4 94 - - P604 D12 DQ - - - - - - - - - - - - - - - - - -
12
K3 K3 119 H3 95 - - P603 D13 DQ - - - - - - - - - - - - - - - - - -
13

R01DS0262EU0140 Rev.1.40 Page 30 of 116

Aug 6, 2018
S7G2 Datasheet 1. Overview

Table 1.17 Pin list (8 of 10)

Pin number Extbus Timers Communication interfaces Analog HMI

CLK, Debug, CAC

Power, System,

GLCDC, PDC
External bus

SCI0,2,4,6,8

SCI1,3,5,7,9

SPI, QSPI
LQFP176

LQFP144

LQFP100

ACMPHS
Interrupt

(30 MHz)

(30 MHz)

(25 MHz)

(50 MHz)
BGA224

BGA176

LGA145

USBFS,
SDRAM
I/O port

DAC12,
USBHS

ADC12

CTSU
SDHI
CAN
AGT

RMII
GPT

GPT

RTC

SSI
MII
IIC
L1 K1 120 J1 96 65 - P602 EBC SD - - - - - - - - - - - - - - - - - LCD
LK CLK _DA
TA0
4_A
L2 K2 121 J2 97 66 - - P601 WR/ DQ - - - - - - - - - - - - - - - - - LCD
WR0 M0 _DA
TA0
3_A
L3 L1 122 H4 98 67 - - P600 RD - - - - - - - - - - - - - - - - - - LCD
_DA
TA0
2_A
M2 K4 123 K2 99 - VCC - - - - - - - - - - - - - - - - - - - - - -
M1 L4 124 K1 100 - VSS - - - - - - - - - - - - - - - - - - - - - -
K4 L2 125 J3 101 68 - KR0 P107 D07 DQ - - GTI - - CTS - - - - - - - - - - - LCD
7 07 OC 8_R _DA
8A_ TS8 TA0
A _A/S 1_A
S8_
A
L4 M1 126 K3 102 69 - KR0 P106 D06 DQ - - GTI - - SCK - - SS - - - - - - - - LCD
6 06 OC 8_A LA3 _DA
8B_ _A TA0
A 0_A
M3 L3 127 J4 103 70 - IRQ P105 D05 DQ - GTE - - - TXD - - SS - - - - - - - - LCD
0/K 05 TRG 8_A/ LA2 _TC
R05 A_C MO _A ON3
SI8_ _A
A/S
DA8
_A
N3 M2 128 L3 104 71 - IRQ P104 D04 DQ - GTE - - - RXD - - SS - - - - - - - - LCD
1/K 04 TRG 8_A/ LA1 _TC
R04 B_B MIS _A ON2
O8_ _A
A/S
CL8
_A
N2 N1 129 L1 105 72 - KR0 P103 D03 DQ - GTO GTI - - CTS - - SS - - - - - - - - LCD
3 03 WU OC 0_R LA0 _TC
P_A 2A_ TS0 _A ON1
A _A/S _A
S0_
A
N1 M3 130 M1 106 73 - KR0 P102 D02 DQ AGT GTO GTI - - SCK - - RS - - - - - AD - - LCD
2 02 O0 WL OC 0_A PC TR _TC
O_A 2B_ KA G0 ON0
A _A _A _A
P1 N2 131 M2 107 74 - IRQ P101 D01 DQ AGT GTE - - - TXD CTS SDA MO - - - - - - - - LCD
1/K 01 EE0 TRG 0_A/ 1_R 1_B SIA _CL
R01 B_A MO TS1 _A K_A
SI_A _A/
/SD SS1
A0_ _A
A
R1 P1 132 N1 108 75 - IRQ P100 D00 DQ AGT GTE - - - RXD SCK SCL MIS - - - - - - - - LCD
2/K 00 IO0_ TRG 0_A/ 1_A 1_B OA _EX
R00 A A_A MIS _A TCL
O0_ K_A
A/S
CL0
_A
P2 N3 133 L2 109 - - - P800 D14 DQ - - - - - - - - - - - - - - - - - -
14
R2 R1 134 N2 110 - - - P801 D15 DQ - - - - - - - - - - - - - SD1 - - - -
15 DAT
4
K7 - - - - - - - P808 - - - - - - - - - - - - - - - - - - - -
K8 - - - - - - - P809 - - - - - - - - - - - - - - - - - - - -
P3 - - - - - - - P810 - - - - - - - - - - - - - - - - - - - -
R3 P2 135 - - - - - P802 - - - - - - - - - - - - - - - SD1 - - - LCD
DAT _DA
5 TA0
2_B
P4 R2 136 - - - - - P803 - - - - - - - - - - - - - - - SD1 - - - LCD
DAT _DA
6 TA0
1_B
M4 P3 137 - - - - P804 - - - - - - - - - - - - - - - SD1 - - - LCD
DAT _DA
7 TA0
0_B
L5 - - - - - - P811 - - - - - - CTX - - - - - - - - - - - - -
0_C
L6 - - - - - - P812 - - - - - - CRX - - - - - - - - - - - - -
0_C
L7 N4 138 N3 111 - VCC - - - - - - - - - - - - - - - - - - - -
L8 M4 139 M3 112 - VSS - - - - - - - - - - - - - - - - - - - -

R01DS0262EU0140 Rev.1.40 Page 31 of 116

Aug 6, 2018
S7G2 Datasheet 1. Overview

Table 1.17 Pin list (9 of 10)

Pin number Extbus Timers Communication interfaces Analog HMI

CLK, Debug, CAC

Power, System,

GLCDC, PDC
External bus

SCI0,2,4,6,8

SCI1,3,5,7,9

SPI, QSPI
LQFP176

LQFP144

LQFP100

ACMPHS
Interrupt

(30 MHz)

(30 MHz)

(25 MHz)

(50 MHz)
BGA224

BGA176

LGA145

USBFS,
SDRAM
I/O port

DAC12,
USBHS

ADC12

CTSU
SDHI
CAN
AGT

RMII
GPT

GPT

RTC

SSI
MII
IIC
R4 R3 140 K4 113 76 - - P500 - - AGT GTI GTI - USB - - - QS - - - - SD1 AN IVR - -
OA0 U_B OC _VB PC CLK 016 EF0
11A USE LK
_A N_B
N4 P4 141 M4 114 77 - IRQ P501 - - AGT GTI GTI - USB - TXD - QS - - - - SD1 AN IVR - -
11 OB0 V_B OC _OV 5_A/ SL CM 116 EF1
11B RCU MO D
_A RA_ SI5_
B A/S
DA5
_A
N5 R4 142 L4 115 78 - IRQ P502 - - - GTI GTI - USB - RXD - QIO - - - - SD1 AN IVC - -
12 W_B OC _OV 5_A/ 0 DAT 017 MP0
12A RCU MIS 0
RB_ O5_
B A/S
CL5
_A
P5 N5 143 K5 116 79 - P503 - - - GTE GTI - USB CTS SCK - QIO - - - - SD1 AN - - -
TRG OC _EXI 6_R 5_A 1 DAT 117
C_B 12B CEN TS6 1
_B _B/S
S6_
B
R5 P5 144 L5 117 80 - P504 - - - GTE GTI - USB SCK CTS QIO - - - - SD1 AN - - -
TRG OC _ID_ 6_B 5_R 2 DAT 018
D_B 13A B TS5 2
_A/
SS5
_A
M5 P6 145 K6 118 - - IRQ P505 - - - - GTI - - RXD - - QIO - - - - SD1 AN - - -
14 OC 6_B/ 3 DAT 118
13B MIS 3
O6_
B/S
CL6
_B
M6 R5 146 L6 119 - - IRQ P506 - - - - - - - TXD - - - - - - - SD1 AN - - -
15 6_B/ CD 019
MO
SI6_
B/S
DA6
_B
N6 N6 147 - - - - - P507 - - - - - - - CTS - - - - - - SD1 AN - - -
5_R WP 119
TS5
_B/
SS5
_B
M7 - - - - - - - P508 - - - - - - - SCK - - - - - - - AN - - -
5_B 020
P6 - - - - - - - P509 - - - - - - - TXD - - - - - - - AN - - -
5_B/ 120
MO
SI5_
B/S
DA5
_B
N7 - - - - - - - P510 - - - - - - - - RXD - - - - - - - AN - - -
5_B/ 021
MIS
O5_
B/S
CL5
_B
R6 R6 148 N4 120 81 VCL - - - - - - - - - - - - - - - - - - - - - -
2
P7 M7 149 N5 121 82 VCC - - - - - - - - - - - - - - - - - - - - - -
R7 N7 150 M5 122 83 VSS - - - - - - - - - - - - - - - - - - - - - -
M8 P7 151 M6 123 84 - IRQ P015 - - - - - - - - - - - - - - - - AN DA1 - -
13 006 /IVC
/AN MP1
106
M9 R7 152 N6 124 85 - - P014 - - - - - - - - - - - - - - - - AN DA0 - -
005 /IVR
/AN EF3
105
N8 P8 153 M7 125 86 VRE - - - - - - - - - - - - - - - - - - - - - -
FL
R8 R8 154 N7 126 87 VRE - - - - - - - - - - - - - - - - - - - - - -
FH
P8 N8 155 L7 127 88 AVC - - - - - - - - - - - - - - - - - - - - - -
C0
N9 N9 156 L8 128 89 AVS - - - - - - - - - - - - - - - - - - - - - -
S0
P9 P9 157 M8 129 90 VRE - - - - - - - - - - - - - - - - - - - - - -
FL0
R9 R9 158 N8 130 91 VRE - - - - - - - - - - - - - - - - - - - - - -
FH0

R01DS0262EU0140 Rev.1.40 Page 32 of 116

Aug 6, 2018
S7G2 Datasheet 1. Overview

Table 1.17 Pin list (10 of 10)

Pin number Extbus Timers Communication interfaces Analog HMI

CLK, Debug, CAC

Power, System,

GLCDC, PDC
External bus

SCI0,2,4,6,8

SCI1,3,5,7,9

SPI, QSPI
LQFP176

LQFP144

LQFP100

ACMPHS
Interrupt

(30 MHz)

(30 MHz)

(25 MHz)

(50 MHz)
BGA224

BGA176

LGA145

USBFS,
SDRAM
I/O port

DAC12,
USBHS

ADC12

CTSU
SDHI
CAN
AGT

RMII
GPT

GPT

RTC

SSI
MII
IIC
N10 - - - - - - IRQ P011 - - - - - - - - - - - - - - - - AN - - -
15- 104
DS
M10 M8 159 - - - - IRQ P010 - - - - - - - - - - - - - - - - AN - - -
14- 103
DS
R10 M9 160 M9 131 - - IRQ P009 - - - - - - - - - - - - - - - - AN - - -
13- 004
DS
N11 P10 161 N9 132 92 - IRQ P008 - - - - - - - - - - - - - - - - AN - - -
12- 003
DS
L9 M6 162 K7 133 93 - - P007 - - - - - - - - - - - - - - - - PG - - -
AV
SS
100
P10 N10 163 L9 134 94 - IRQ P006 - - - - - - - - - - - - - - - - AN IVC - -
11- 102 MP2
DS
R11 R10 164 K8 135 95 - IRQ P005 - - - - - - - - - - - - - - - - AN IVC - -
10- 101 MP2
DS
M11 P11 165 K9 136 96 - IRQ P004 - - - - - - - - - - - - - - - - AN IVC - -
9- 100 MP2
DS
L10 M5 166 K10 137 97 - - P003 - - - - - - - - - - - - - - - - PG - - -
AV
SS
000
N12 R11 167 M10 138 98 - IRQ P002 - - - - - - - - - - - - - - - - AN IVC - -
8- 002 MP2
DS
P11 N11 168 N10 139 99 - IRQ P001 - - - - - - - - - - - - - - - - AN IVC - -
7- 001 MP2
DS
R12 R12 169 L10 140 100 - IRQ P000 - - - - - - - - - - - - - - - - AN IVC - -
6- 000 MP2
DS
L11 M10 170 N11 141 - VSS - - - - - - - - - - - - - - - - - - - - - -
L12 M11 171 N12 142 - VCC - - - - - - - - - - - - - - - - - - - - - -
M12 P12 172 - - - - - P806 - - - - - - - - - - - - - - - - - - - LCD
_EX
TCL
K_B
R13 R13 173 - - - - - P805 - - - - - - - - - - - - - - - - - - - LCD
_DA
TA1
7_B
P12 - - - - - - - P807 - - - - - - - - - - - - - - - - - - - -
P13 N12 174 - - - - - P513 - - - - - - - - - - - - ET1 - - - - - - LCD
_ET _DA
XD TA1
3 6_B
K9 - - - - - - - P515 - - - - - - - - - - - - - - - - - - - -
R14 R14 175 M11 143 - - IRQ P512 - - - - GTI - CTX TXD - SCL - - ET1 - - - - - - VSY
14 OC 1_B 4_B/ 2 _ET NC
0A_ MO XD
B SI4_ 2
B/S
DA4
_B
P14 - - - - - - P514 - - - GTE - - - - - - - - - - - - - - - -
TRG
B_C
R15 P13 176 M12 144 - - IRQ P511 - - - - GTI - CRX RXD - SDA - - ET1 - - - - - - PCK
15 OC 1_B 4_B/ 2 _TX O
0B_ MIS _E
B O4_ R
B/S
CL4
_B

Note: Some pin names have the added suffix of _A, _B, and _C. When assigning the IIC, SPI, and SSI functionality,
select the functional pins with the same suffix. The other pins can be selected regardless of the suffix.

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S7G2 Datasheet 2. Electrical Characteristics

2. Electrical Characteristics
Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:
VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, VCC_USBHS =
AVCC_USBHS = 3.0 to 3.6 V, VSS = AVSS0 = VREFL0/VREFL = VSS_USB = VSS1_USBHS = VSS2_USBHS =
PVSS_USBHS = AVSS_USBHS = 0 V, Ta = Topr
Figure 2.1 shows the timing conditions.

For example, P100

VOH = VCC × 0.7, V OL = VCC × 0.3

VIH = VCC × 0.7, VIL = VCC × 0.3
Load capacitance C = 30pF

Figure 2.1 Input or output timing measurement conditions

The measurement conditions of timing specification for each peripheral are recommended for the best peripheral
operation. However, make sure to adjust driving abilities for each pin to meet your conditions.

2.1 Absolute Maximum Ratings

Table 2.1 Absolute maximum ratings

Item Symbol Value Unit
Power supply voltage VCC, VCC_USB *2 -0.3 to +4.6 V
VBATT power supply voltage VBATT -0.3 to +4.6 V
Input voltage (except for 5V-tolerant ports*1) Vin -0.3 to VCC + 0.3 V
Input voltage (5V-tolerant ports*1) Vin -0.3 to VCC + 4.6 (max 5.8) V
Reference power supply voltage VREFH/VREFH0 -0.3 to AVCC0 + 0.3 V
Analog power supply voltage AVCC0 *2 -0.3 to +4.6 V
USBHS power supply voltage VCC_USBHS -0.3 to +4.6 V
USBHS analog power supply voltage AVCC_USBHS -0.3 to +4.6 V
Switching regulator power supply voltage VCC_DCDC -0.3 to +4.6 V
Analog input voltage (except for P000 to P007) VAN -0.3 to AVCC0 + 0.3 V
Analog input voltage (P000 to P007) when PGA differential VAN -0.3 to AVCC0 + 0.3 V
input is disabled
Analog input voltage (P000 to P002, P004 to P006) when VAN -1.1 to AVCC0 + 0.3 V
PGA differential input is enabled
Analog input voltage (P003, P007) when PGA differential VAN -0.6 to AVCC0 + 0.3 V
input is enabled
Operating temperature*3,*4 Topr -40 to +85 °C
-40 to +105
Storage temperature Tstg -55 to +125 °C

Note: See the Total Operating Time (TOT) Utility Calculator located under http://www.renesas.com. This utility
calculator is provided for educational and evaluation purposes only and is subject to the accompanying
disclaimer.

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S7G2 Datasheet 2. Electrical Characteristics

Note 1. Ports P205, P206, P400, P401, P407 to P415, P511, P512, P708 to P713, and PB01 are 5V-tolerant.
Note 2. Connect AVCC0 and VCC_USB to VCC.
Note 3. See section 2.2.1, Tj/Ta Definition.
Note 4. The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, see section
1.3, Part Numbering.
Caution: Permanent damage to the MCU might result if absolute maximum ratings are exceeded.

Table 2.2 Recommended operating conditions

Item Symbol Value Min Typ Max Unit
Power supply voltages VCC When USB/SDRAM is not used 2.7 - 3.6 V
When USB/SDRAM is used 3.0 - 3.6 V
VSS - 0 - V
USB power supply voltages VCC_USB, - VCC - V
VCC_USBHS
VSS_USB, - 0 - V
AVSS_USBHS,
PVSS_USBHS,
VSS1_USBHS,
VSS2_USBHS
Switching regulator power VCC_DCDC When switching regulator is - VCC - V
supply voltage used
When switching regulator is not - 0 - V
used
VBATT power supply voltage VBATT 2.0 3.6 V
Analog power supply voltages AVCC0 - VCC - V
AVSS0 - 0 - V

2.2 DC Characteristics

2.2.1 Tj/Ta Definition

Table 2.3 DC characteristics

Conditions: Products with operating temperature (Ta) –40 to +105°C

Item Symbol Typ Max Unit Test conditions

Permissible junction temperature Tj - 125 °C High-speed mode
Low-speed mode
105*1
Subosc-speed mode

Note: Make sure that Tj = Ta + θja × total power consumption (W), where total power consumption = (VCC – VOH) ×
ΣIOH + VOL × ΣIOL + ICCmax × VCC.
Note 1. The upper limit of operating temperature is 85°C or 105°C depending on the product. For details, see section 1.3,
Part Numbering. If the part number shows the operation temperature as 85°C, then the maximum value of Tj is
105°C, otherwise it is 125°C.

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S7G2 Datasheet 2. Electrical Characteristics

2.2.2 I/O VIH, VIL

Table 2.4 I/O VIH, VIL

Item Symbol Min Typ Max Unit
Input voltage Peripheral EXTAL (external clock input), WAIT, SPI VIH VCC × 0.8 - - V
(except for function pin
VIL - - VCC × 0.2
Schmitt
trigger input D00 to D15, VIH VCC × 0.7 - -
pins) DQ00 to DQ15
VIL - - VCC × 0.3
ETHERC VIH 2.3 - -
VIL - - VCC × 0.2
IIC (SMBus)*1 VIH 2.1 - -
VIL - - 0.8
IIC (SMBus)*2 VIH 2.1 - -
VIL - - 0.8
Schmitt Peripheral IIC (except for SMBus)*1 VIH VCC × 0.7 - - V
trigger input function pin
VIL - - VCC × 0.3
voltage
ΔVT VCC × 0.05 - -
IIC (except for SMBus)*2 VIH VCC × 0.7 - VCC + 3.6
(max 5.8)
VIL - - VCC × 0.3
ΔVT VCC × 0.05 - -
5V-tolerant ports*3*7 VIH VCC × 0.8 - VCC + 3.6
(max 5.8)
VIL - - VCC × 0.2
ΔVT VCC × 0.05 - -
RTCIC0, When using When VBATT VIH VBATT × 0.8 - VBATT + 0.3
RTCIC1, the Battery power supply
VIL - - VBATT × 0.2
RTCIC2 Backup is selected
Function ΔVT VBATT × 0.05 - -
When VCC VIH VCC x 0.8 - Higher
power supply voltage, either
is selected VCC + 0.3 or
VBATT + 0.3
VIL - - VCC × 0.2
ΔVT VCC × 0.05 - -
When not using the Battery VIH VCC × 0.8 - VCC + 0.3
Backup Function
VIL - - VCC × 0.2
ΔVT VCC × 0.05 - -
Other input pins*4 VIH VCC × 0.8 - -
VIL - - VCC × 0.2
ΔVT VCC × 0.05 - -
Ports 5V-tolerant ports*5*7 VIH VCC × 0.8 - VCC + 3.6
(max 5.8)
VIL - - VCC × 0.2
Other input pins*6 VIH VCC × 0.8 - -
VIL - - VCC × 0.2

Note 1. SCL0_B, SCL1_B, SDA1_B (total 3 pins).

Note 2. SCL0_A, SDA0_A, SDA0_B, SCL1_A, SDA1_A, SCL2, SDA2 (total 7 pins).
Note 3. RES and peripheral function pins associated with P205, P206, P400, P401, P407 to P415, P511, P512, P708 to
P713, PB01 (total 23 pins).
Note 4. All input pins except for the peripheral function pins already described in the table.
Note 5. P205, P206, P400, P401, P407 to P415, P511, P512, P708 to P713, PB01 (total 22pins).

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S7G2 Datasheet 2. Electrical Characteristics

Note 6. All input pins except for the ports already described in the table.
Note 7. When VCC is less than 2.7 V, the input voltage of 5V-tolerant ports should be less than 3.6 V, otherwise
breakdown may occur because 5V-tolerant ports are electrically controlled so as not to violate the break down
voltage.

2.2.3 I/O IOH, IOL

Table 2.5 I/O IOH, IOL (1 of 2)

Item Symbol Min Typ Max Unit
Permissible output current Ports P008 to P011, P201,P212 - IOH - -- -2.0 mA
(average value per pin)
IOL - - 2.0 mA

Ports P014, P015, P213, P400, - IOH - - -4.0 mA

P401, P511, P512
IOL - - 4.0 mA

Ports P402 to P404 Low drive*1 IOH - - -2.0 mA

IOL - - 2.0 mA

Middle drive*2 IOH - - -4.0 mA

IOL - - 4.0 mA

Ports P205, P206, P407 to P415, Low drive*1 IOH - - -2.0 mA

P602, P708 to P713, P813, PA12
to PA15, PB01 (total 24 pins) IOL - - 2.0 mA

Middle drive*2 IOH - - -4.0 mA

IOL - - 4.0 mA

High drive*3 IOH - - -20 mA

IOL - - 20 mA

Other output pins*4 Low drive*1 IOH - - -2.0 mA

IOL - - 2.0 mA

Middle drive*2 IOH - - -4.0 mA

IOL - - 4.0 mA

High drive*3 IOH - - -16 mA

IOL - - 16 mA

Permissible output current Ports P008 to P011, P201,P212 - IOH - - -4.0 mA

(max value per pin)
IOL - - 4.0 mA

Ports P014, P015, P213, P400, - IOH - - -8.0 mA

P401, P511, P512
IOL - - 8.0 mA

Ports P402 to P404 Low drive*1 IOH - - -4.0 mA

IOL - - 4.0 mA

Middle drive*2 IOH - - -8.0 mA

IOL - - 8.0 mA

Ports P205, P206, P407 to P415, Low drive*1 IOH - - -4.0 mA

P602, P708 to P713, P813,
PA12 to PA15, PB01 IOL - - 4.0 mA
(total 24 pins)
Middle drive*2 IOH - - -8.0 mA

IOL - - 8.0 mA

High drive*3 IOH - - -40 mA

IOL - - 40 mA

Other output pins*4 Low drive*1 IOH - - -4.0 mA

IOL - - 4.0 mA

Middle drive*2 IOH - - -8.0 mA

IOL - - 8.0 mA

High drive*3 IOH - - -32 mA

IOL - - 32 mA

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Table 2.5 I/O IOH, IOL (2 of 2)

Item Symbol Min Typ Max Unit
Permissible output current Maximum of all output pins ΣIOH (max) - - -80 mA
(max value total pins)
ΣIOL (max) - - 80 mA

Note 1. This is the value when low driving ability is selected in the port drive capability bit in the PmnPFS register. The
selected driving ability is retained in Deep Software Standby mode.
Note 2. This is the value when middle driving ability is selected in the port drive capability bit in the PmnPFS register. The
selected driving ability is retained in Deep Software Standby mode.
Note 3. This is the value when high driving ability is selected in the port drive capability bit in the PmnPFS register. When
the following ports are configured for high driving ability, they shift to middle driving ability during Deep Software
Standby mode: P203 to P207, P407 to P415, P602, P708 to P713, P813, PA12 to PA15, PB01.
Note 4. Except for P000 to P007, P200, which are input ports.
Caution: To protect the reliability of the MCU, the output current values should not exceed the values in the
preceding table. The average output current indicates the average value of current measured during
100 μs.

2.2.4 I/O VOH, VOL, and Other Characteristics

Table 2.6 I/O VOH, VOL, and other characteristics

Item Symbol Min Typ Max Unit Test conditions
Output voltage IIC VOL - - 0.4 V IOL = 3.0 mA

VOL - - 0.6 IOL = 6.0 mA

IIC*1 VOL - - 0.4 IOL = 15.0 mA

(ICFER.FMPE = 1)
VOL - 0.4 - IOL = 20.0 mA
(ICFER.FMPE = 1)
ETHERC VOH VCC - 0.5 - - IOH = –1.0 mA

VOL - - 0.4 IOL = 1.0 mA

Ports P205, P206, P407 to P415, VOH VCC - 1.0 - - IOH = –20 mA
P602, P708 to P713, P813, PA12 to VCC = 3.3 V
PA15, PB01 (total 24 pins)*2
VOL - - 1.0 IOL = 20 mA
VCC = 3.3 V
Other output pins VOH VCC - 0.5 - - IOH = –1.0 mA

VOL - - 0.5 IOL = 1.0 mA

Input leakage current RES |Iin| - - 5.0 μA Vin = 0 V

Vin = 5.5 V
Ports P000 to P007, P200 - - 1.0 Vin = 0 V
Vin = VCC
Three-state leakage 5V-tolerant ports |ITSI| - - 5.0 μA Vin = 0 V
current (off state) Vin = 5.5 V
Other ports (except for ports P000 - - 1.0 Vin = 0 V
to P007, P200) Vin = VCC
Input pull-up MOS current Ports P0 to PB (except for ports Ip -300 - -10 μA VCC = 2.7 to 3.6 V
P000 to P007) Vin = 0 V
Input capacitance USB_DP, USB_DM, and ports Cin - - 16 pF Vbias = 0V
P003, P007, P014, P015,P400, Vamp = 20mV
P415, P401, P511, P512 f = 1 MHz
Ta = 25°C
Other input pins - - 8

Note 1. SCL0_A, SDA0_A (total 2 pins).

Note 2. This is the value when high driving ability is selected in the Port Drive Capability bit in the PmnPFS register. Even
when high driving ability is selected, IOH and IOL shift to middle driving ability during Deep Software Standby
mode.

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S7G2 Datasheet 2. Electrical Characteristics

2.2.5 Operating and Standby Current

Table 2.7 Operating and standby current (1 of 2)

LDO mode DCDC mode
Item Symbol Min Typ Max Min Typ Max Unit Test conditions
Supply Maximum*2 ICC*7 - - 330 - - 140 mA ICLK = 240 MHz
current*1 PCLKA = 120 MHz*6
CoreMark®*4 - 45 - - 24 - PCLKB = 60 MHz
Normal All peripheral clocks - 75 - - 38 - PCLKC = 60 MHz
mode*3 enabled, while (1) code PCLKD = 120 MHz
executing from flash FCLK = 60 MHz
BCLK = 120 MHz
All peripheral clocks - 32 - - 18 -
disabled, while (1) code
High-speed mode

executing from flash*5

Sleep mode*4 *5 - 25 150 - 15 75
Increase Data flash P/E - 7 - - 7 -
during BGO
operation Code flash P/E - 10 - - 10 -

Low-speed mode*4 - 4.4 - - 3 - ICLK = 1 MHz

Subosc-speed mode*4 - 3 - - 2 - ICLK = 32.768 kHz
Software Standby mode - 2.4 110 - 1.2 55 -
Power supplied to Standby SRAM and USB - 37 255 - 37 255 μA VBAT ≠ VCC
resume detecting unit
- 37 285 - 37 285 VBAT = VCC
Power not Power-on reset circuit low- - 25 50 - 25 50 VBAT ≠ VCC
supplied to power function disabled
SRAM or - 25 80 - 25 80 VBAT = VCC
USB resume
Deep Software Standby mode

Power-on reset circuit low- - 16 35 - 16 35 VBAT ≠ VCC

detecting power function enabled
unit - 16 65 - 16 65 VBAT = VCC
Increase When the low-speed on-chip - 9 - - 9 - -
when the oscillator (LOCO) is in use
RTC and
AGT are When a crystal oscillator for - 1.0 - - 1.0 - -
operating low clock loads is in use
When a crystal oscillator for - 3.0 - - 3.0 - -
standard clock loads is in
use
RTC operating while When a crystal - 0.9 - - 0.9 - VBATT = 2.0 V,
VCC is off (with the oscillator for low clock VCC = 0 V
battery backup loads is in use
function, only the RTC - 1.6 - - 1.6 - VBATT = 3.3 V,
and sub-clock VCC = 0 V
oscillator operate) When a crystal - 1.7 - - 1.7 - VBATT = 2.0 V,
oscillator for standard VCC = 0 V
clock loads is in use
- 3.3 - - 3.3 - VBATT = 3.3 V,
VCC = 0 V
Analog During 12-bit A/D conversion AICC - 0.8 1.1 - 0.8 1.1 mA -
power
supply During 12-bit A/D conversion with S/H amp - 2.3 3.3 - 2.3 3.3 mA -
current PGA (1ch) - 1 3 - 1 3 mA -
ACMPHS (1unit) 100 150 100 150 µA -
Temperature sensor - 0.1 0.2 - 0.1 0.2 mA -
During D/A conversion Without AMP output - 0.1 0.2 - 0.1 0.2 mA -
(per unit)
With AMP output - 0.5 0.8 - 0.5 0.8 mA -
Waiting for A/D, D/A conversion (all units) - 0.9 1.6 - 0.9 1.6 mA -
ADC12, DAC12 in standby modes (all units)*8 - 2 6 - 2 6 µA -
Reference During 12-bit A/D conversion (unit 0) AIREFH0 - 70 120 - 70 120 μA -
power
supply Waiting for 12-bit A/D conversion (unit 0) - 0.07 0.4 - 0.07 0.4 μA -
current ADC12 in standby modes (unit 0) - 0.07 0.2 - 0.07 0.2 µA -
(VREFH0)

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S7G2 Datasheet 2. Electrical Characteristics

Table 2.7 Operating and standby current (2 of 2)

LDO mode DCDC mode
Item Symbol Min Typ Max Min Typ Max Unit Test conditions
Reference During 12-bit A/D conversion (unit 1) AIREFH - 70 120 - 70 120 µA -
power
supply During D/A conversion Without AMP output - 0.24 0.4 - 0.24 0.4 mA -
current (per unit)
With AMP ouput - 0.1 0.2 - 0.1 0.2 mA -
(VREFH)
Waiting for 12-bit A/D (unit 1), D/A (all units) - 0.07 0.4 - 0.07 0.4 µA -
conversion
ADC12 unit 1 in standby modes - 0.07 0.2 - 0.07 0.2 µA -
USB Low speed USB ICCUSBLS - 3.5 6.5 - 3.5 6.5 mA VCC_USB
operating
current USBHS - 10.5 13.5 - 10.5 13.5 mA VCC_USBHS =
AVCC_USBHS
(PHYSET.HSEB = 0)
USBHS - 2.8 3.6 - 2.8 3.6 mA VCC_USBHS =
AVCC_USBHS
(PHYSET.HSEB = 1)
Full speed USB ICCUSBFS - 4.0 10.0 - 4.0 10.0 mA VCC_USB
USBHS - 14 22 - 14 22 mA VCC_USBHS =
AVCC_USBHS
(PHYSET.HSEB = 0)
USBHS - 6.5 13.0 - 6.5 13.0 mA VCC_USBHS =
AVCC_USBHS
(PHYSET.HSEB = 1)
High speed USBHS ICCUSBHS - 50 65 - 50 65 mA VCC_USBHS =
AVCC_USBHS
Standby mode (direct USBHS ICCUSBSBY - 0.5 3.0 - 0.5 3.0 μA VCC_USBHS =
power down) AVCC_USBHS
Note 1. Supply current values are with all output pins unloaded and all input pull-up MOS transistors in the off state.
Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation.
Note 3. This does not include the BGO operation.
Note 4. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.
Note 5. FCLK, BCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to be divided by 64 (3.75 MHz).
Note 6. When using ETHERC, PCLKA frequency is:
12.5MHz ≤ PCLKA ≤ 120MHz
Note 7. ICC depends on f(ICLK) and is calculated as follows:
- High-speed mode (Maximum)
- LDO mode: ICC max = 0.90 [mA/MHz] x f [MHz] + 114 [mA]
- DCDC mode: ICC max = 0.35 [mA/MHz] x f [MHz] + 57 [mA]
- High-speed mode (Normal mode/all peripheral clocks disabled)
- LDO mode: ICC typ = 0.10 [mA/MHz] x f [MHz] + 6.9 [mA]
- DCDC mode: ICC typ = 0.06 [mA/MHz] x f [MHz] + 4.4 [mA]
- Low-speed mode (ICLK 1 MHz max)
- LDO mode: ICC typ = 0.10 [mA/MHz] x f [MHz] + 4.3 [mA]
- DCDC mode: ICC typ = 0.06 [mA/MHz] x f [MHz] + 3.0 [mA]
- Sleep mode
- LDO mode: ICC max = 0.15 [mA/MHz] x f [MHz] + 114 [mA]
- DCDC mode: ICC max = 0.07 [mA/MHz] x f [MHz] + 57 [mA]
Note 8. When the MSTPCRD.MSTPD16 (ADC120 Module Stop bit) and MSTPCRD. MSTPD15 (ADC121 Module Stop
bit) are in the module-stop state.

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S7G2 Datasheet 2. Electrical Characteristics

2.2.6 VCC Rise and Fall Gradient and Ripple Frequency

Table 2.8 Rise and fall gradient characteristics

Item Symbol Min Typ Max Unit Test conditions
VCC rising gradient SrVCC 0.0084 - 20 ms/V -
VCC falling gradient*1 SfVCC 0.0084 - - ms/V -

Note 1. This applies when VBATT is used.

Table 2.9 Rise and fall gradient and ripple frequency characteristics
The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (3.6 V) and lower limit
(2.7 V). When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.

Item Symbol Min Typ Max Unit Test conditions

Allowable ripple frequency fr (VCC) - - 10 kHz Figure 2.2
Vr (VCC) ≤ VCC × 0.2
- - 1 MHz Figure 2.2
Vr (VCC) ≤ VCC × 0.08
- - 10 MHz Figure 2.2
Vr (VCC) ≤ VCC × 0.06
Allowable voltage change rising dt/dVCC 1.0 - - ms/V When VCC change exceeds VCC ±10%
and falling gradient

1/fr(VCC)

VCC Vr( VCC)

Figure 2.2 Ripple waveform

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S7G2 Datasheet 2. Electrical Characteristics

2.3 AC Characteristics
2.3.1 Frequency

Table 2.10 Operation frequency value in high-speed mode

Item Symbol Min Typ Max Unit
Operation frequency System clock (ICLK*2) f - - 240 MHz
Peripheral module clock (PCLKA)*2 - - 120
Peripheral module clock (PCLKB)*2 - - 60
Peripheral module clock (PCLKC)*2 -*3 - 60
Peripheral module clock (PCLKD)*2 - - 120
Flash interface clock (FCLK)*2 -*1 - 60
External bus clock (BCLK)*2 - - 120
EBCLK pin output - - 60
SDCLK pin output VCC ≥ 3.0 V - - 120

Note 1. FCLK must run at a frequency of at least 4 MHz when programming or erasing the flash memory.
Note 2. See section 9, Clock Generation Circuit in User’s Manual for the relationship between the ICLK, PCLKA, PCLKB,
PCLKC, PCLKD, FCLK, and BCLK frequencies.
Note 3. When the ADC12 is used, the PCLKC frequency must be at least 1 MHz.

Table 2.11 Operation frequency value in low-speed mode

Item Symbol Min Typ Max Unit
Operation frequency System clock (ICLK)*2 f - - 1 MHz
Peripheral module clock (PCLKA)*2 - - 1
Peripheral module clock (PCLKB)*2 - - 1
Peripheral module clock (PCLKC)*2,*3 -*3 - 1
Peripheral module clock (PCLKD)*2 - - 1
Flash interface clock (FCLK)*1, *2 - - 1
External bus clock (BCLK) - - 1
EBCLK pin output - - 1

Note 1. Programming or erasing the flash memory is disabled in low-speed mode.

Note 2. See section 9, Clock Generation Circuit in User’s Manual for the relationship between the ICLK, PCLKA, PCLKB,
PCLKC, PCLKD, FCLK, and BCLK frequencies.
Note 3. When the ADC12 is used, the PCLKC frequency must be set to at least 1 MHz.

Table 2.12 Operation frequency value in Subosc-speed mode

Item Symbol Min Typ Max Unit
Operation frequency System clock (ICLK)*2 f 29.4 - 36.1 kHz
Peripheral module clock (PCLKA)*2 - - 36.1
Peripheral module clock (PCLKB)*2 - - 36.1
Peripheral module clock (PCLKC)*2,*3 - - 36.1
Peripheral module clock (PCLKD)*2 - - 36.1
Flash interface clock (FCLK)*1, *2 29.4 - 36.1
External bus clock (BCLK)*2 - - 36.1
EBCLK pin output - - 36.1

Note 1. Programming or erasing the flash memory is disable in Subosc-speed mode.

Note 2. See section 9, Clock Generation Circuit in User’s Manual for the relationship between the ICLK, PCLKA, PCLKB,
PCLKC, PCLKD, FCLK, and BCLK frequencies.
Note 3. The ADC12 cannot be used.

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2.3.2 Clock Timing

Table 2.13 Clock timing except for sub-clock oscillator

Item Symbol Min Typ Max Unit Test conditions
EBCLK pin output cycle time tBcyc 16.6 - - ns Figure 2.3
EBCLK pin output high pulse width tCH 3.3 - - ns
EBCLK pin output low pulse width tCL 3.3 - - ns
EBCLK pin output rise time tCr - - 5.0 ns
EBCLK pin output fall time tCf - - 5.0 ns
SDCLK pin output cycle time tSDcyc 8.33 - - ns
SDCLK pin output high pulse width tCH 1.0 - - ns
SDCLK pin output low pulse width tCL 1.0 - - ns
SDCLK pin output rise time tCr - - 3.0 ns
SDCLK pin output fall time tCf - - 3.0 ns
EXTAL external clock input cycle time tEXcyc 41.66 - - ns Figure 2.4
EXTAL external clock input high pulse width tEXH 15.83 - - ns
EXTAL external clock input low pulse width tEXL 15.83 - - ns
EXTAL external clock rise time tEXr - - 5.0 ns
EXTAL external clock fall time tEXf - - 5.0 ns
Main clock oscillator frequency fMAIN 8 - 24 MHz -
Main clock oscillation stabilization wait time tMAINOSCWT - - -*1 ms Figure 2.5
(crystal) *1
LOCO clock oscillation frequency fLOCO 29.4912 32.768 36.0448 kHz -
LOCO clock oscillation stabilization wait time tLOCOWT - - 60.4 μs Figure 2.6
ILOCO clock oscillation frequency fILOCO 13.5 15 16.5 kHz -
MOCO clock oscillation frequency FMOCO 7.2 8 8.8 MHz -
MOCO clock oscillation stabilization wait time tMOCOWT - - 15.0 μs -
HOCO clock oscillator Without FLL fHOCO16 15.61 16 16.39 MHz –20 ≤ Ta ≤ 105°C
oscillation frequency
fHOCO18 17.56 18 18.44
fHOCO20 19.52 20 20.48
fHOCO16 15.52 16 16.48 –40 ≤ Ta ≤ –20°C
fHOCO18 17.46 18 18.54
fHOCO20 19.40 20 20.60
With FLL fHOCO16 15.91 16 16.09 SOSC frequency is
32.768kHz ± 50ppm
fHOCO18 17.90 18 18.10
fHOCO20 19.89 20 20.11
HOCO clock oscillation stabilization wait time *2 tHOCOWT - - 64.7 μs -

FLL stabilization wait time tFLLWT - - 3 ms -

PLL clock frequency fPLL 120 - 240 MHz -

PLL clock oscillation tPLLWT - - 174.9 μs Figure 2.7

stabilization wait time

Note 1. When setting up the main clock oscillator, ask the oscillator manufacturer for an oscillation evaluation and use the
results as the recommended oscillation stabilization time. Set the MOSCWTCR register to a value equal to or
greater than the recommended value.
After changing the setting in the MOSCCR.MOSTP bit to start main clock operation, read the OSCSF.MOSCSF
flag to confirm that it is 1, and then start using the main clock oscillator.
Note 2. This is the time from release from reset state until the HOCO oscillation frequency (fHOCO) reaches the range
for guaranteed operation.

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Table 2.14 Clock timing for the sub-clock oscillator

Item Symbol Min Typ Max Unit Test conditions
Sub-clock frequency fSUB - 32.768 - kHz -
Sub-clock oscillation stabilization wait time tSUBOSCWT - - -*1 s Figure 2.8

Note 1. When setting up the sub-clock oscillator, ask the oscillator manufacturer for an oscillation evaluation and use the
results as the recommended oscillation stabilization time. After changing the setting in the SOSCCR.SOSTP bit
to start sub-clock operation, only start using the sub-clock oscillator after the sub-clock oscillation stabilization
time elapses with an adequate margin. Two times the oscillation wait time is recommended.

tBcyc , tSDcyc
tCH
tCf

EBCLK pin output, SDCLK pin output

tCr
tCL

Figure 2.3 EBCLK and SDCLK output timing

tEXcyc
tEXH tEXL

EXTAL external clock input VCC × 0.5

tEXr tEXf

Figure 2.4 EXTAL external clock input timing

MOSCCR.MOSTP

Main clock oscillator output

tMAINOSCWT

Main clock

Figure 2.5 Main clock oscillation start timing

LOCOCR.LCSTP

On-chip oscillator output

tLOCOWT

LOCO clock

Figure 2.6 LOCO clock oscillation start timing

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S7G2 Datasheet 2. Electrical Characteristics

PLLCR.PLLSTP

PLL circuit output

tPLLWT

OSCSF.PLLSF

PLL clock

Figure 2.7 PLL clock oscillation start timing

Note: Only operate the PLL is operated after main clock oscillation has stabilized.

SOSCCR.SOSTP

Sub-clock oscillator output

tSUBOSCCWT
Sub-clock

Figure 2.8 Sub-clock oscillation start timing

2.3.3 Reset Timing

Table 2.15 Reset timing

Test
Item Symbol Min Typ Max Unit conditions
RES pulse width Power-on LDO mode tRESWP 1 - - ms Figure 2.9
DCDC mode 1.5 - - ms
Deep Software Standby mode tRESWD 0.6 - - ms Figure 2.10
Software Standby mode, Subosc-speed tRESWS 0.3 - - ms
mode
All other tRESW 200 - - μs
Wait time after RES cancellation tRESWT - - 33.4 μs Figure 2.9
Wait time after internal reset cancellation tRESW2 - - 390 μs -
(IWDT reset, WDT reset, software reset, SRAM parity error
reset, SRAM DED error reset, bus master MPU error reset, bus
slave MPU error reset, stack pointer error reset)

VCC

RES

tRESWP
Internal reset signal
(active-low)

tRESWT

Figure 2.9 Power-on reset timing

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tRESWD, tRESWS, tRESW

RES

Internal reset signal

(active-low)

tRESWT

Figure 2.10 Reset input timing

2.3.4 Wakeup Timing and Duration

Table 2.16 Timing of recovery from low power modes and duration
Item Symbol Min Typ Max Unit Test conditions
Recovery time Crystal System clock source is main tSBYMC - - 2.8 ms Figure 2.11
from Software resonator clock oscillator*2 The division ratio of
Standby mode*1 connected all oscillators is 1.
System clock source is PLL tSBYPC - - 3.2 ms
to main
with main clock oscillator*3
clock
oscillator
External System clock source is main tSBYEX - - 280 μs
clock input clock oscillator*4
to main
System clock source is PLL tSBYPE - - 700 μs
clock
with main clock oscillator*5
oscillator
System clock source is sub-clock tSBYSC - - 1.3 ms
oscillator*8
System clock source is LOCO*8 tSBYLO - - 1.4 ms
System clock source is HOCO clock tSBYHO - - 300 µs
oscillator*6
System clock source is MOCO clock tSBYMO - - 300 µs
oscillator*7
Recovery time from Deep Software Standby mode tDSBY - - 1.0 ms Figure 2.12
Wait time after cancellation of Deep Software Standby mode tDSBYWT 31 - 32 tcyc
Recovery time High-speed mode when system clock tSNZ - - 68 μs Figure 2.13
from Software source is HOCO (20 MHz)
Standby mode to
High-speed mode when system clock tSNZ - - 14*9 μs
Snooze mode
source is MOCO (8 MHz)
Normal mode System clock source is main clock tNML -*11 - - tcycmosc Figure 2.11
duration*10 oscillator
System clock source is PLL with main
clock oscillator

Note 1. The recovery time is determined by the system clock source. When multiple oscillators are active, the recovery
time can be determined with the following equation:
Total recovery time = recovery time for an oscillator as the system clock source + the longest oscillation
stabilization time of any oscillators requiring longer stabilization times than the system clock source + 2 LOCO
cycles (when LOCO is operating) + 3 SOSC cycles (when Subosc is oscillating and MSTPC0 = 0 (CAC module
stop)).
Note 2. When the frequency of the crystal is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to
05h). For other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following
equation:
tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 05h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT
(MOSCWTCR = 05h))
Note 3. When the frequency of PLL is 240 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to
05h). For other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following

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S7G2 Datasheet 2. Electrical Characteristics

equation:
tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 05h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT
(MOSCWTCR = 05h))
Note 4. When the frequency of the external clock is 24 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR)
is set to 00h). For other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the
following equation:
tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 00h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT
(MOSCWTCR = 00h))
Note 5. When the frequency of PLL is 240 MHz (Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to
00h). For other settings (MOSCWTCR is set to Xh), the recovery time can be determined with the following
equation:
tSBYMC (MOSCWTCR = Xh) = tSBYMC (MOSCWTCR = 00h) + (tMAINOSCWT (MOSCWTCR = Xh) - tMAINOSCWT
(MOSCWTCR = 00h))
Note 6. The HOCO frequency is 20 MHz.
Note 7. The MOCO frequency is 8 MHz.
Note 8. In Subosc-speed mode, the sub-clock oscillator or LOCO continues oscillating in Software Standby mode.
Note 9. When the SNZCR.RXDREQEN bit is set to 0, 86 μs is added as the power supply recovery time.
Note 10. This defines the duration of Normal mode after a transition from Snooze to Normal mode.
The following cases are valid uses of the main clock oscillator:
- The crystal resonator is connected to main clock oscillator
- The external clock is input to main clock oscillator.
The following cases are excluded:
- The main clock resonator is not connected to the system clock source
- Transition is made from Software Standby to Normal mode.
Note 11. The same value as set in MOSCWTCR.MSTS[3:0]. Duration of Normal mode must be longer than the main clock
oscillator wait time.
MOSCWTCR: Main Clock Oscillator Wait Control Register
tcycmosc: Main clock oscillator frequency cycle.

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S7G2 Datasheet 2. Electrical Characteristics

Oscillator
(system clock )
tSBYOSCWT tSBYSEQ
Oscillator
(not the system clock )

ICLK

IRQ
Software Standby mode

t SBYMC, tSBYEX, t SBYPC, t SBYPE,

t SBYPH, t SBYSC, tSBYHO, tSBYLO
When stabilization of the system clock oscillator is slower

Oscillator
(system clock )
tSBYOSCWT tSBYSEQ
Oscillator
(not the system clock )

t SBYOSCWT
ICLK

IRQ

Software Standby mode

tSBYMC , t SBYEX, tSBYPC , tSBYPE,

tSBYPH , tSBYSC , tSBYHO, tSBYLO
When stabilization of an oscillator other than the system clock is slower

Main clock oscillator

(system clock )

ICLK

t SBYMC , tSBYEX, tSBYPC,

t NML
t SBYPE
Software Standby mode Snooze Normal mode Software Standby mode
Duration of Normal mode
Figure 2.11 Software Standby mode cancellation timing and duration

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Oscillator

IRQ

Deep Software Standby

reset
(active-low)

Internal reset
(active-low)

Deep Software Standby mode

tDSBY
tDSBYWT

Reset exception handling start

Figure 2.12 Deep Software Standby mode cancellation timing

Oscillator

ICLK(except DTC, SRAM)

ICLK(to DTC, SRAM) *1

PCLK

IRQ

Software Standby mode Snooze mode

tSNZ

Note1: When SNZCR.SNZDTCEN is set to 1, ICLK is supplied to DTC and SRAM.

Figure 2.13 Recovery timing from Software Standby mode to Snooze mode

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2.3.5 NMI and IRQ Noise Filter

Table 2.17 NMI and IRQ noise filter

Item Symbol Min Typ Max Unit Test conditions
NMI pulse width tNMIW 200 - - ns NMI digital filter disabled tPcyc × 2 ≤ 200 ns
tPcyc × 2*1 - - tPcyc × 2 > 200 ns
200 - - NMI digital filter enabled tNMICK × 3 ≤ 200 ns
tNMICK × 3.5*2 - - tNMICK × 3 > 200 ns
IRQ pulse width tIRQW 200 - - ns IRQ digital filter disabled tPcyc × 2 ≤ 200 ns
tPcyc × 2*1 - - tPcyc × 2 > 200 ns
200 - - IRQ digital filter enabled tIRQCK × 3 ≤ 200 ns
tIRQCK × 3.5*3 - - tIRQCK × 3 > 200 ns

Note: 200 ns minimum in Software Standby mode.

Note 1. tPcyc indicates the PCLKB cycle.
Note 2. tNMICK indicates the cycle of the NMI digital filter sampling clock.
Note 3. tIRQCK indicates the cycle of the IRQi digital filter sampling clock.

NMI

tNMIW

Figure 2.14 NMI interrupt input timing

IRQ

tIRQW

Figure 2.15 IRQ interrupt input timing

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S7G2 Datasheet 2. Electrical Characteristics

2.3.6 Bus Timing

Table 2.18 Bus timing

Condition 1: When using the CS area controller (CSC).
BCLK = 8 to 60 MHz
VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0,
VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF
EBCLK: High drive output is selected in the port drive capability bit in the PmnPFS register.
Others: Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Condition 2: When using the SDRAM area controller (SDRAMC).

BCLK = SDCLK = 8 to 120 MHz
VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, VREFH/VREFH0 = 3.0 V to AVCC0,
VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF
High drive output is selected in the port drive capability bit in the PmnPFS register.

Condition 3: When using the SDRAM area controller (SDRAMC) and CS area controller (CSC) simultaneously.
BCLK = SDCLK = 8 to 60 MHz
VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, VREFH/VREFH0 = 3.0 V to AVCC0,
VCC_USBHS = AVCC_USBHS = 3.0 to 3.6 V
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF
High drive output is selected in the port drive capability bit in the PmnPFS register.
Item Symbol Min Max Unit Test conditions
Address delay tAD - 12.5 ns Figure 2.16 to
Figure 2.19
Byte control delay tBCD - 12.5 ns
CS delay tCSD - 12.5 ns
RD delay tRSD - 12.5 ns
Read data setup time tRDS 12.5 - ns
Read data hold time tRDH 0 - ns
WR/WRn delay tWRD - 12.5 ns
Write data delay tWDD - 12.5 ns
Write data hold time tWDH 0 - ns
WAIT setup time tWTS 12.5 - ns Figure 2.20
WAIT hold time tWTH 0 - ns
Address delay 2 (SDRAM) tAD2 0.8 6.8 ns Figure 2.21 to
Figure 2.27
CS delay 2 (SDRAM) tCSD2 0.8 6.8 ns
DQM delay (SDRAM) tDQMD 0.8 6.8 ns
CKE delay (SDRAM) tCKED 0.8 6.8 ns
Read data setup time 2 (SDRAM) tRDS2 2.9 - ns
Read data hold time 2 (SDRAM) tRDH2 1.5 - ns
Write data delay 2 (SDRAM) tWDD2 - 6.8 ns
Write data hold time 2 (SDRAM) tWDH2 0.8 - ns
WE delay (SDRAM) tWED 0.8 6.8 ns
RAS delay (SDRAM) tRASD 0.8 6.8 ns
CAS delay (SDRAM) tCASD 0.8 6.8 ns

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CSRWAIT: 2

RDON:1
CSROFF: 2
CSON: 0

TW1 TW2 Tend Tn1 Tn2

EBCLK

Byte strobe mode

tAD tAD

A23 to A00

1-write strobe mode

tAD tAD

A23 to A01

tBCD tBCD

BC1, BC0

Common to both byte strobe mode

and 1-write strobe mode
tCSD tCSD

CS7 to CS0

tRSD tRSD

RD (read)

tRDS tRDH

D15 to D00 (read)

Figure 2.16 External bus timing for normal read cycle with bus clock synchronized

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S7G2 Datasheet 2. Electrical Characteristics

CSWWAIT: 2

WRON: 1
WDON: 1*1
CSWOFF: 2

CSON:0 WDOFF: 1*1

TW1 TW2 Tend Tn1 Tn2

EBCLK

Byte strobe mode

tAD tAD

A23 to A00

1-write strobe mode

tAD tAD

A23 to A01

tBCD tBCD

BC1, BC0

Common to both byte strobe mode

and 1-write strobe mode
tCSD tCSD

CS7 to CS0

tWRD tWRD

WR1, WR0, WR (write)

tWDD
tWDH

D15 to D00 (write)

Note 1. Always specify WDON and WDOFF as at least one EBCLK cycle.

Figure 2.17 External bus timing for normal write cycle with bus clock synchronized

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S7G2 Datasheet 2. Electrical Characteristics

CSRWAIT:2 CSPRWAIT:2 CSPRWAIT:2 CSPRWAIT:2

RDON:1 RDON:1 RDON:1 RDON:1 CSROFF:2

CSON:0
TW1 TW2 Tend Tpw1 Tpw2 Tend Tpw1 Tpw2 Tend Tpw1 Tpw2 Tend Tn1 Tn2

EBCLK

Byte strobe mode

tAD tAD tAD tAD tAD

A23 to A00

1-write strobe mode tAD tAD tAD tAD tAD

A23 to A01

tBCD tBCD
BC1, BC0

Common to both byte strobe mode

and 1-write strobe mode tCSD
tCSD
CS7 to CS0
tRSD tRSD tRSD tRSD tRSD tRSD tRSD tRSD

RD (Read)

tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH

D15 to D00 (Read)

Figure 2.18 External bus timing for page read cycle with bus clock synchronized

CSWWAIT:2 CSPWWAIT:2 CSPWWAIT:2 CSWOFF:2

WRON:1
WRON:1 WRON:1
WDON:1*1 WDOFF:1*1 WDOFF:1*1 WDOFF:1*1
WDON:1*1 WDON:1*1
CSON:0 TW1 TW2 Tend Tdw1 Tpw1 Tpw2 Tend Tdw1 Tpw1 Tpw2 Tend Tn1 Tn2

EBCLK

Byte strobe mode

tAD tAD tAD tAD

A23 to A00

1-write strobe mode tAD tAD tAD tAD

A23 to A01

tBCD tBCD
BC1, BC0

Common to both byte strobe mode

and 1-write strobe mode
tCSD tCSD
CS7 to CS0

tWRD tWRD tWRD tWRD tWRD tWRD

WR1, WR0, WR (write)

tWDD tWDD tWDD

tWDH tWDH tWDH
D15 to D00 (write)

Note 1. Always specify WDON and WDOFF as at least one EBCLK cycle.

Figure 2.19 External bus timing for page write cycle with bus clock synchronized

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S7G2 Datasheet 2. Electrical Characteristics

CSRWAIT:3
CSWWAIT:3

T W1 TW2 T W3 (Tend) T end Tn1 T n2

EBCLK

A23 to A00

CS7 to CS0

RD (read)

WR (write)

External wait

tWTS tWTH tWTS tWTH

WAIT

Figure 2.20 External bus timing for external wait control

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S7G2 Datasheet 2. Electrical Characteristics

SDRAM command ACT RD PRA

SDCLK

tAD2 tAD2 tAD2 tAD2

A15 to A00 Row

address Column address

tAD2 tAD2 tAD2 tAD2

AP*1 PRA
command
tCSD2 tCSD2 tCSD2 tCSD2 tCSD2 tCSD2

SDCS
tRASD tRASD tRASD tRASD

RAS
tCASD tCASD

CAS
tWED tWED

WE

(High)
CKE

tDQMD

DQMn

tRDS2 tRDH2

DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.21 SDRAM single read timing

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S7G2 Datasheet 2. Electrical Characteristics

SDRAM command ACT WR PRA

SDCLK

tAD2 tAD2 tAD2 tAD2

A15 to A00 Row

address Column address

tAD2 tAD2 tAD2 tAD2

AP*1 PRA
command
tCSD2 tCSD2 tCSD2 tCSD2 tCSD2 tCSD2

SDCS
tRASD tRASD tRASD tRASD

RAS
tCASD tCASD

CAS
tWED tWED tWED tWED

WE

(High)
CKE

tDQMD

DQMn
tWDD2 tWDH2

DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.22 SDRAM single write timing

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S7G2 Datasheet 2. Electrical Characteristics

ACT RD RD RD RD PRA

SDCLK

tAD2 tAD2 tAD2 tAD2 tAD2 tAD2 tAD2 tAD2

Row C0
A15 to A00 address (column address)
C1 C2 C3

tAD2 tAD2 tAD2 tAD2 tAD2

AP*1 PRA
command

tCSD2 tCSD2 tCSD2 tCSD2 tCSD2

SDCS

tRASD tRASD tRASD tRASD tRASD

RAS
tCASD tCASD tCASD

CAS
tWED tWED

WE

(High)

CKE

tDQMD tDQMD

DQMn
tRDS2 tRDH2 tRDS2 tRDH2

DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.23 SDRAM multiple read timing

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S7G2 Datasheet 2. Electrical Characteristics

ACT WR WR WR WR PRA

SDCLK

tAD2 tAD2 tAD2 tAD2 tAD2 tAD2 tAD2 tAD2

Row C0
A15 to A00 address (column address)
C1 C2 C3

tAD2 tAD2 tAD2 tAD2 tAD2

AP*1 PRA
command

tCSD2 tCSD2 tCSD2 tCSD2 tCSD2

SDCS

tRASD tRASD tRASD tRASD tRASD

RAS
tCASD tCASD tCASD

CAS
tWED tWED

WE

(High)

CKE

tDQMD tDQMD

DQMn
tWDD2 tWDH2 tWDD2 tWDH2

DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.24 SDRAM multiple write timing

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SDRAM command ACT RD RD RD RD PRA ACT RD RD RD RD PRA

SDCLK

t AD2 t AD2 t AD2 t AD2 t AD2 t AD2 t AD2 t AD2 t AD2 t AD2 t AD2 t AD2 t AD2 t AD2

A15 to A00 Row

address
C0
(column address 0) C1 C2 C3 R1 C4 C5 C6 C7

t AD2 t AD2 t AD2 t AD2 t AD2 t AD2 t AD2 t AD2

AP*1 PRA
command
PRA
command

t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 t CSD2

SDCS

t RASD t RASD t RASD t RASD t RASD t RASD t RASD t RASD

RAS
t CASD t CASD t CASD t CASD

CAS
t WED t WED t WED t WED

WE

(High)

CKE
tDQMD

DQMn

t RDS2 t RDH2 t RDS2 t RDH2 t RDS2 t RDH2 t RDS2 t RDH2

DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.25 SDRAM multiple read line stride timing

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S7G2 Datasheet 2. Electrical Characteristics

MRS
SDRAM command
SDCLK

t AD2 t AD2

A15 to A00

t AD2 t AD2

AP*1

t CSD2 t CSD2

SDCS
t RASD t RASD

RAS
t CASD t CASD

CAS
t WED t WED

WE

(High)

CKE

DQMn

(Hi-Z)

DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.26 SDRAM mode register set timing

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S7G2 Datasheet 2. Electrical Characteristics

SDRAM command Ts (RFA) (RFS) (RFX) (RFA)

SDCLK

t AD2 t AD2

A15 to A00

t AD2 t AD2

AP*1

t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 t CSD2

SDCS

t RASD t RASD t RASD t RASD t RASD t RASD t RASD

RAS
t CASD t CASD t CASD t CASD t CASD t CASD t CASD

CAS

(High)

WE
t CKED t CKED

CKE

t DQMD t DQMD

DQMn

(Hi-Z)
DQ15 to DQ00

Note 1. Address pins are for output of the precharge-select command (Precharge-sel) for the SDRAM.

Figure 2.27 SDRAM self-refresh timing

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S7G2 Datasheet 2. Electrical Characteristics

2.3.7 I/O Ports, POEG, GPT32, AGT, KINT, and ADC12 Trigger Timing

Table 2.19 I/O ports, POEG, GPT32, AGT, KINT, and ADC12 trigger timing
GPT32 Conditions:
Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: GTIOC6A_A, GTIOC6B_A,
GTIOC3A_B, GTIOC3B_B, GTIOC0A_B, GTIOC0B_B, GTIOC9A_B, GTIOC9B_B.
High drive output is selected in the port drive capability bit in the PmnPFS register for all other pins.

AGT Conditions:
Middle drive output is selected in the port drive capability bit in the PmnPFS register.
Test
Item Symbol Min Max Unit conditions
I/O ports Input data pulse width tPRW 1.5 - tPcyc Figure 2.28
POEG POEG input trigger pulse width tPOEW 3 - tPcyc Figure 2.29
GPT32 Input capture pulse width Single edge tGTICW 1.5 - tPDcyc Figure 2.30
Dual edge 2.5 -
GTIOCxY_Z output skew Middle drive buffer tGTISK*2 - 4 ns Figure 2.31
(x = 0 to 7, Y= A or B , Z = A or B)
High drive buffer - 4
GTIOCxY_Z output skew Middle drive buffer - 4
(x = 8 to 13, Y = A or B, Z = A or B)
High drive buffer - 4
GTIOCxY_Z output skew Middle drive buffer - 6
(x = 0 to 13, Y = A or B, Z = A or B)
High drive buffer - 6
OPS output skew tGTOSK - 5 ns Figure 2.32
GTOUUP_x, GTOULO_x, GTOVUP_x, *2
GTOVLO_x, GTOWUP_x, GTOWLO_x
(x = A or B)
GPT(PWM GTIOCxY_Z output skew tHRSK*3 - 2.0 ns Figure 2.33
Delay (x = 0 to 3, Y = A or B, Z = A)
Generation
Circuit)
AGT AGTIO, AGTEE input cycle tACYC*1 100 - ns Figure 2.34
AGTIO, AGTEE input high width, low width tACKWH, 40 - ns
tACKWL
AGTIO, AGTO, AGTOA, AGTOB output cycle tACYC2 62.5 - ns
ADC12 ADC12 trigger input pulse width tTRGW 1.5 - tPcyc Figure 2.35

KINT KRn (n = 00 to 07) pulse width tKR 250 - ns Figure 2.36

Note 1. tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle.

Note 2. This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation
is not guaranteed.
Note 3. The load is 30 pF.
Note 4. Constraints on AGTIO input: tPcyc × 2 (tPcyc: PCLKB cycle) < tACYC.

Port

tPRW
Figure 2.28 I/O ports input timing

POEG input trigger

tPOEW

Figure 2.29 POEG input trigger timing

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S7G2 Datasheet 2. Electrical Characteristics

Input capture

tGTICW

Figure 2.30 GPT32 input capture timing

PCLKD

Output delay

GPT32 output

tGTISK

Figure 2.31 GPT32 output delay skew

PCLKD

Output delay

GPT32 output

tGTOSK

Figure 2.32 GPT32 output delay skew for OPS

PCLKD

Output delay

GPT32 output
(PWM delay
generation circuit)

tHRSK

Figure 2.33 GPT32 (PWM Delay Generation Circuit) output delay skew

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S7G2 Datasheet 2. Electrical Characteristics

tACYC

tACKWL tACKWH

AGTIO, AGTEE
(input)

tACYC2

AGTIO, AGTO,
AGTOA, AGTOB
(output)

Figure 2.34 AGT input/output timing

ADTRG0,
ADTRG1
tTRGW

Figure 2.35 ADC12 trigger input timing

KR00 to KR07

tKR

Figure 2.36 Key interrupt input timing

2.3.8 PWM Delay Generation Circuit Timing

Table 2.20 PWM Delay Generation Circuit timing

Item Min Typ Max Unit Test conditions
Operation frequency 80 - 120 MHz -
Resolution - 260 - ps PCLKD = 120 MHz
DNL*1 - ±2.0 - LSB -

Note 1. This value normalizes the differences between lines in 1-LSB resolution.

2.3.9 CAC Timing

Table 2.21 CAC timing

Test
Item Symbol Min Typ Max Unit conditions
CAC CACREF input pulse width tPBcyc ≤ tcac*2 tCACREF 4.5 × tcac + 3 × tPBcyc - - ns -
tPBcyc > tcac*2 5 × tcac + 6.5 × tPBcyc - - ns

Note 1. tPBcyc: PCLKB cycle.

Note 2. tcac: CAC count clock source cycle.

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S7G2 Datasheet 2. Electrical Characteristics

2.3.10 SCI Timing

Table 2.22 SCI timing (1)

Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: SCK0 to SCK9
(except for SCK4_B, SCK7_A).
For other pins, middle drive output is selected in the port drive capability bit in the PmnPFS register.
Test
Item Symbol Min Max Unit*1 conditions
SCI Input clock cycle Asynchronous tScyc 4 - tPcyc Figure 2.37
Clock 6 -
synchronous
Input clock pulse width tSCKW 0.4 0.6 tScyc
Input clock rise time tSCKr - 5 ns
Input clock fall time tSCKf - 5 ns
Output clock cycle Asynchronous tScyc 6 - tPcyc
Clock 4 -
synchronous
Output clock pulse width tSCKW 0.4 0.6 tScyc
Output clock rise time tSCKr - 5 ns
Output clock fall time tSCKf - 5 ns
Transmit data delay Clock tTXD - 25 ns Figure 2.38
synchronous
Receive data setup time Clock tRXS 15 - ns
synchronous
Receive data hold time Clock tRXH 5 - ns
synchronous

Note 1. tPcyc: PCLKA cycle.

tSCKW tSCKr tSCKf

SCKn
(n = 0 to 9)

tScyc

Figure 2.37 SCK clock input/output timing

SCKn

tTXD

TxDn

tRXS tRXH

RxDn

n = 0 to 9

Figure 2.38 SCI input/output timing in clock synchronous mode

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S7G2 Datasheet 2. Electrical Characteristics

Table 2.23 SCI timing (2)

Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: SCK0 to SCK9
(except for SCK4_B, SCK7_A).
For the SCK4_B and SCK7_A pins, middle drive output is selected in the port drive capability bit in the PmnPFS register.
For the MISO1_A pins, low drive output is selected in the port drive capability bit in the PmnPFS register.
For other pins, middle drive output is selected in the port drive capability bit in the PmnPFS register.
Test
Item Symbol Min Max Unit conditions
Simple SCK clock cycle output tSPcyc 4 (PCLKA ≤ 60 MHz) 65536 tPcyc Figure 2.39
SPI (master) 8 (PCLKA > 60 MHz)
SCK clock cycle input (slave) - 6 (PCLKA ≤ 60 MHz) 65536
12 (PCLKA > 60 MHz)
SCK clock high pulse width tSPCKWH 0.4 0.6 tSPcyc
SCK clock low pulse width tSPCKWL 0.4 0.6 tSPcyc
SCK clock rise and fall time tSPCKr, tSPCKf - 20 ns
Data input setup time tSU 33.3 - ns Figure 2.40 to
Figure 2.43
Data input hold time tH 33.3 - ns
SS input setup time tLEAD 1 - tSPcyc
SS input hold time tLAG 1 - tSPcyc
Data output delay tOD - 33.3 ns
Data output hold time tOH –10 - ns
Data rise and fall time tDr, tDf - 16.6 ns
SS input rise and fall time tSSLr, tSSLf - 16.6 ns
Slave access time tSA - 4 (PCLKA ≤ 60 MHz) tPcyc Figure 2.43
8 (PCLKA > 60 MHz)
Slave output release time tREL - 5 (PCLKA ≤ 60 MHz) tPcyc
10 (PCLKA > 60 MHz)

Note: MISO1_A is not supported in these specifications.

tSPCKWH tSPCKr tSPCKf

VOH VOH VOH VOH

SCKn
master select VOL VOL VOL
output
tSPCKWL
tSPcyc

tSPCKWH tSPCKr tSPCKf

VIH VIH VIH VIH

SCKn
slave select input VIL VIL VIL
tSPCKWL
(n = 0 to 9) tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC

Figure 2.39 SCI simple SPI mode clock timing

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S7G2 Datasheet 2. Electrical Characteristics

SCKn
CKPOL = 0
output

SCKn
CKPOL = 1
output
tSU tH

MISOn
MSB IN DATA LSB IN MSB IN
input

tDr, tDf tOH tOD

MOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output

(n = 0 to 9)

Figure 2.40 SCI simple SPI mode timing for master when CKPH = 1

SCKn
CKPOL = 1
output

SCKn
CKPOL = 0
output
tSU tH

MISOn
MSB IN DATA LSB IN MSB IN
input

tOH tOD tDr, tDf

MOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output

(n = 0 to 9)

Figure 2.41 SCI simple SPI mode timing for master when CKPH = 0

tTD
SSn
input
tLEAD tLAG

SCKn
CKPOL = 0
input

SCKn
CKPOL = 1
input
tSA tOH tOD tREL

MISOn
MSB OUT DATA LSB OUT MSB IN MSB OUT
output

tSU tH tDr, tDf

MOSIn
MSB IN DATA LSB IN MSB IN
input

(n = 0 to 9)

Figure 2.42 SCI simple SPI mode timing for slave when CKPH = 1

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S7G2 Datasheet 2. Electrical Characteristics

tTD

SSn
input
tLEAD t LAG

SCKn
CKPOL = 1
input

SCKn
CKPOL = 0
input
t SA tOH tOD tREL

MISOn LSB OUT

(Last data) MSB OUT DATA LSB OUT MSB OUT
output

tSU tH tDr, tDf

MOSIn
MSB IN DATA LSB IN MSB IN
input

(n = 0 to 9)

Figure 2.43 SCI simple SPI mode timing for slave when CKPH = 0

Table 2.24 SCI timing (3)

Conditions: For the SCL1_A pins, low drive output is selected in the port drive capability bit in the PmnPFS register.
For other pins, middle drive output is selected in the port drive capability bit in the PmnPFS register.
Item Symbol Min Max Unit Test conditions
Simple IIC SDA input rise time tSr - 1000 ns Figure 2.44
(Standard mode)
SDA input fall time tSf - 300 ns
SDA input spike pulse removal time tSP 0 4 × tIICcyc ns
Data input setup time tSDAS 250 - ns
Data input hold time tSDAH 0 - ns
SCL, SDA capacitive load Cb*1 - 400 pF
Simple IIC SDA input rise time tSr - 300 ns Figure 2.44
(Fast mode)
SDA input fall time tSf - 300 ns
SDA input spike pulse removal time tSP 0 4 × tIICcyc ns
Data input setup time tSDAS 100 - ns
Data input hold time tSDAH 0 - ns
SCL, SDA capacitive load Cb*1 - 400 pF

Note: SCL1_A output is not supported in these specifications.

tIICcyc: IIC internal reference clock (IICφ) cycle.
Note 1. Cb indicates the total capacity of the bus line.

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S7G2 Datasheet 2. Electrical Characteristics

VIH
SDAn
VIL

tSr tSf
tSP

SCLn

P*1 S*1 Sr*1 P*1

(n = 0 to 9)
tSDAH tSDAS

Note 1. S, P, and Sr indicate the following: Test conditions:

S: Start condition VIH = VCC × 0.7, VIL = VCC × 0.3
P: Stop condition VOL = 0.6 V, IOL = 6 mA
Sr: Restart condition

Figure 2.44 SCI simple IIC mode timing

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S7G2 Datasheet 2. Electrical Characteristics

2.3.11 SPI Timing

Table 2.25 SPI timing

Conditions:
(1) Middle drive output is selected with the port drive capability bit in the PmnPFS register.
(2) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the SPI interface,
the AC portion of the electrical characteristics is measured for each group.
Item Symbol Min Max Unit*1 Test conditions
SPI RSPCK clock cycle Master tSPcyc 2 (PCLKA  60 MHz) 4096 tPcyc Figure 2.45
4 (PCLKA > 60 MHz) C = 30 pF
Slave 6 4096
RSPCK clock high Master tSPCKWH (tSPcyc – tSPCKr – tSPCKf) / 2 – 3 - ns
pulse width
Slave 3 × tPcyc -
RSPCK clock low pulse Master tSPCKWL (tSPcyc – tSPCKr – tSPCKf) / 2 – 3 - ns
width
Slave 3 × tPcyc -
RSPCK clock rise and Master tSPCKr, - 5 ns
fall time tSPCKf
Slave - 1 µs
Data input setup time Master tSU 4 - ns Figure 2.46 to
Figure 2.51
Slave 5 -
C = 30 pF
Data input hold time Master tHF*4 0 - ns -
Master tH tPcyc -
Slave tH 20 - -
SSL setup time Master tLEAD N × tSPcyc - 10*2 N× ns -
tSPcyc +
100 *2
Slave 6 x tPcyc - ns -
SSL hold time Master tLAG N × tSPcyc - 10 *3 N× ns -
tSPcyc +
100 *3
Slave 6 x tPcyc - ns -
Data output delay Master tOD - 6.3 ns Figure 2.46 to
Figure 2.51
Slave - 20
C = 30PF
Data output hold time Master tOH 0 - ns
Slave 0 -
Successive Master tTD tSPcyc + 2 × tPcyc 8× ns
transmission delay tSPcyc +
2 × tPcyc
Slave 6 × tPcyc
MOSI and MISO rise Output tDr, tDf - 5 ns
and fall time
Input - 1 μs
SSL rise and fall time Output tSSLr, - 5 ns
tSSLf
Input - 1 μs
Slave access time tSA - 2 x tPcyc ns Figure 2.50 and
+ 28 Figure 2.51
C = 30PF
Slave output release time tREL - 2 x tPcyc
+ 28

Note 1. tPcyc: PCLKA cycle.

Note 2. N is set to an integer from 1 to 8 by the SPCKD register.
Note 3. N is set to an integer from 1 to 8 by the SSLND register.
Note 4. PCLKA division ratio set to 1/2.

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S7G2 Datasheet 2. Electrical Characteristics

tSPCKWH tSPCKr tSPCKf

SPI
VOH VOH VOH VOH
RSPCKn
master select VOL VOL VOL
output
tSPCKWL
tSPcyc

tSPCKWH tSPCKr tSPCKf

VIH VIH VIH VIH

RSPCKn
slave select input VIL VIL VIL
tSPCKWL
n = A or B tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 2.45 SPI clock timing

SPI
tTD
SSLn0 to
SSLn3
output
tLEAD tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output

RSPCKn
CPOL = 1
output
tSU tH

MISOn
MSB IN DATA LSB IN MSB IN
input

tDr, tDf tOH tOD

MOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output

n = A or B

Figure 2.46 SPI timing for master when CPHA = 0

SPI tTD

SSLn0 to
SSLn3
output tLEAD tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output

RSPCKn
CPOL = 1
output
tSU tHF tHF

MISOn MSB IN DATA LSB IN MSB IN

input

tDr, tDf tOH tOD

MOSIn MSB OUT DATA LSB OUT IDLE MSB OUT

output

n = A or B
Figure 2.47 SPI timing for master when CPHA = 0 and the bit rate is set to PCLKA/2

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S7G2 Datasheet 2. Electrical Characteristics

SPI
tTD
SSLn0 to
SSLn3
output
t LEAD t LAG
t SSLr, tSSLf
RSPCKn
CPOL = 0
output

RSPCKn
CPOL = 1
output
t SU tH

MISOn
MSB IN DATA LSB IN MSB IN
input

t OH t OD t Dr, tDf

MOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output

n = A or B

Figure 2.48 SPI timing for master when CPHA = 1

SPI
tTD
SSLn0 to
SSLn3
output
tLEAD tLAG
tSSLr, tSSLf
RSPCKn
CPOL = 0
output

RSPCKn
CPOL = 1
output
tSU tHF tH

MISOn
MSB IN DATA LSB IN MSB IN
input

tOH tOD tDr, tDf

MOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output

n = A or B

Figure 2.49 SPI timing for master when CPHA = 1 and the bit rate is set to PCLKA/2

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S7G2 Datasheet 2. Electrical Characteristics

SPI
t TD
SSLn0
input
t LEAD tLAG

RSPCKn
CPOL = 0
input

RSPCKn
CPOL = 1
input
t SA t OH tO D t R EL

MISOn
M SB OUT DATA LSB O UT M SB IN M SB OUT
output

t SU tH t D r, t D f

M O SIn
MSB IN DATA LSB IN MSB IN
input

n = A or B

Figure 2.50 SPI timing for slave when CPHA = 0

SPI
t TD

SSLn0
input
tLEAD tLAG

RSPCKn
CPOL = 0
input

RSPCKn
CPOL = 1
input
tSA tOH tOD tREL

MISOn LSB OUT

(Last data) MSB OUT DATA LSB OUT MSB OUT
output

tSU tH t Dr, t Df

MOSIn
MSB IN DATA LSB IN MSB IN
input

n = A or B

Figure 2.51 SPI timing for slave when CPHA = 1

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S7G2 Datasheet 2. Electrical Characteristics

2.3.12 QSPI Timing

Table 2.26 QSPI timing

Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register.
Item Symbol Min Max Unit*1 Test conditions
QSPI QSPCK clock cycle tQScyc 2 48 tPcyc Figure 2.52
QSPCK clock high pulse width tQSWH tQScyc × 0.4 - ns
QSPCK clock low pulse width tQSWL tQScyc × 0.4 - ns
Data input setup time tSu 11 - ns Figure 2.53
Data input hold time tIH 0 - ns
QSSL setup time tLEAD (N+0.5) x (N+0.5) x ns
tQscyc - 5 *2 tQscyc +100 *2
QSSL hold time tLAG (N+0.5) x (N+0.5) x ns
tQscyc - 5 *3 tQscyc +100 *3
Data output delay tOD - 4 ns
Data output hold time tOH –3.3 - ns
Successive transmission delay tTD 1 16 tQScyc

Note 1. tPcyc: PCLKA cycle.

Note 2. N is set to 0 or 1 in SFMSLD.
Note 3. N is set to 0 or 1 in SFMSHD.

tQSWH tQSWL

QSPCLK output

tQScyc

Figure 2.52 QSPI clock timing

tTD

QSSL
output
tLEAD tLAG

QSPCLK
output

tSU tH

QIO0-3
MSB IN DATA LSB IN
input

tOH tOD

QIO0-3
MSB OUT DATA LSB OUT IDLE
output

Figure 2.53 Transmit and receive timing

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S7G2 Datasheet 2. Electrical Characteristics

2.3.13 IIC Timing

Table 2.27 IIC timing (1) (1 of 2)

Conditions:
(1) Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: SDA0_B, SCL0_B,
SDA1_A, SCL1_A, SDA1_B, SCL1_B. The following pins do not require setting: SCL0_A, SDA0_A, SCL2, SDA2.
(2) Use pins that have a letter appended to their names, for example “_A” or “_B”, to indicate group membership. For the IIC interface,
the AC portion of the electrical characteristics is measured for each group.
Test
Item Symbol Min*1 Max Unit conditions
IIC SCL input cycle time tSCL 6 (12) × tIICcyc + 1300 - ns Figure 2.54
(Standard mode,
SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 - ns
SMBus)
ICFER.FMPE = 0 SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 - ns
SCL, SDA input rise time tSr - 1000 ns
SCL, SDA input fall time tSf - 300 ns
SCL, SDA input spike pulse removal tSP 0 1 (4) × tIICcyc ns
time
SDA input bus free time when tBUF 3 (6) × tIICcyc + 300 - ns
wakeup function is disabled
SDA input bus free time when tBUF 3 (6) × tIICcyc + 4 × - ns
wakeup function is enabled tPcyc + 300
START condition input hold time tSTAH tIICcyc + 300 - ns
when wakeup function is disabled
START condition input hold time tSTAH 1 (5) × tIICcyc + tPcyc + - ns
when wakeup function is enabled 300
Repeated START condition input tSTAS 1000 - ns
setup time
STOP condition input setup time tSTOS 1000 - ns
Data input setup time tSDAS tIICcyc + 50 - ns
Data input hold time tSDAH 0 - ns
SCL, SDA capacitive load Cb - 400 pF

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S7G2 Datasheet 2. Electrical Characteristics

Table 2.27 IIC timing (1) (2 of 2)

Conditions:
(1) Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: SDA0_B, SCL0_B,
SDA1_A, SCL1_A, SDA1_B, SCL1_B. The following pins do not require setting: SCL0_A, SDA0_A, SCL2, SDA2.
(2) Use pins that have a letter appended to their names, for example “_A” or “_B”, to indicate group membership. For the IIC interface,
the AC portion of the electrical characteristics is measured for each group.
Test
Item Symbol Min*1 Max Unit conditions
IIC SCL input cycle time tSCL 6 (12) × tIICcyc + 600 - ns Figure 2.54
(Fast mode)
SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 - ns
SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 - ns
SCL, SDA input rise time tSr 20 × (external pullup 300 ns
voltage/5.5V)*2
SCL, SDA input fall time tSf 20 × (external pullup 300 ns
voltage/5.5V)*2
SCL, SDA input spike pulse removal tSP 0 1 (4) × tIICcyc ns
time
SDA input bus free time when tBUF 3 (6) × tIICcyc + 300 - ns
wakeup function is disabled
SDA input bus free time when tBUF 3 (6) × tIICcyc + 4 × tPcyc - ns
wakeup function is enabled + 300
START condition input hold time tSTAH tIICcyc + 300 - ns
when wakeup function is disabled
START condition input hold time tSTAH 1(5) × tIICcyc + tPcyc + - ns
when wakeup function is enabled 300
Repeated START condition input tSTAS 300 - ns
setup time
STOP condition input setup time tSTOS 300 - ns
Data input setup time tSDAS tIICcyc + 50 - ns
Data input hold time tSDAH 0 - ns
SCL, SDA capacitive load Cb - 400 pF
Note: tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle.
Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE
set to 1.
Note 2. Only supported for SCL0_A, SDA0_A, SCL2, and SDA2.

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S7G2 Datasheet 2. Electrical Characteristics

Table 2.28 IIC timing (2)

Conditions:
(1) Setting of the SCL0_A, SDA0_A pins is not required with the port drive capability bit in the PmnPFS register.
Test
Item Symbol Min*1,*2 Max Unit conditions
IIC SCL input cycle time tSCL 6 (12) × tIICcyc + 240 - ns Figure 2.54
(Fast-mode+)
SCL input high pulse width tSCLH 3 (6) × tIICcyc + 120 - ns
ICFER.FMPE = 1
SCL input low pulse width tSCLL 3 (6) × tIICcyc + 120 - ns
SCL, SDA input rise time tSr - 120 ns
SCL, SDA input fall time tSf - 120 ns
SCL, SDA input spike pulse removal tSP 0 1 (4) × tIICcyc ns
time
SDA input bus free time when tBUF 3 (6) × tIICcyc + 120 - ns
wakeup function is disabled
SDA input bus free time when tBUF 3(6) × tIICcyc + 4 × tPcyc - ns
wakeup function is enabled + 120
Start condition input hold time when tSTAH tIICcyc + 120 - ns
wakeup function is disabled
START condition input hold time tSTAH 1(5) × tIICcyc + tPcyc + - ns
when wakeup function is enabled 120
Restart condition input setup time tSTAS 120 - ns
Stop condition input setup time tSTOS 120 - ns
Data input setup time tSDAS tIICcyc + 30 - ns
Data input hold time tSDAH 0 - ns
SCL, SDA capacitive load Cb - 550 pF

Note: tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle.
Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE
set to 1.
Note 2. Cb indicates the total capacity of the bus line.

V IH
SDA0 to SDA2
V IL

t BUF
t SC LH
t STAH tS TAS tS P t STO S

SCL0 to SCL2

P* 1 S* 1 Sr* 1 P* 1
t SC LL
t Sf t Sr t SD AS
t SCL
t SDAH
Test conditions :
Note 1. S, P, and Sr indicate the following :
V IH = VCC × 0.7, V IL = VCC × 0.3
S: Start condition
P: Stop condition V OL = 0.6 V, I OL = 6 mA (ICFER .FMPE = 0)
Sr: Restart condition V OL = 0.4 V, I OL = 15 mA (ICFER .FMPE = 1)

Figure 2.54 I2C bus interface input/output timing

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S7G2 Datasheet 2. Electrical Characteristics

2.3.14 SSI Timing

Table 2.29 SSI timing

Conditions:
(1) Middle drive output is selected with the port drive capability bit in the PmnPFS register.
(2) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the SSI interface,
the AC portion of the electrical characteristics is measured for each group.
Test
Item Symbol Min Max Unit conditions
SSI AUDIO_CLK input frequency tAUDIO - 50 MHz -
Output clock period tO 150 64000 ns Figure 2.55
Input clock period tI 150 64000 ns
Clock high pulse width tHC 60 - ns
Clock low pulse width tLC 60 - ns
Clock rise time tRC - 25 ns
Data delay tDTR –5 25 ns Figure 2.56,
Figure 2.57
Set-up time tSR 25 - ns
Hold time tHTR 25 - ns
SSIDATA output delay from WS change time TDTRW - 25 ns Figure 2.58

tHC tRC

tLC
SSISCKn

tI, tO

Figure 2.55 SSI clock input/output timing

SSISCKn
(Input or Output)

SSIWSn, SSIDATAn
(Input)

tSR tHTR

SSIWSn, SSIDATAn
(Output)

tDTR

Figure 2.56 SSI data transmit and receive timing when SSICR.SCKP = 0

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S7G2 Datasheet 2. Electrical Characteristics

SSISCKn
(Input or Output)

SSIWSn, SSIDATAn
(Input)

tSR tHTR

SSIWSn, SSIDATAn
(Output)

tDTR

Figure 2.57 SSI data transmit and receive timing when SSICR.SCKP = 1

SSIWSn (input)

SSIDATAn (output)

tDTRW

MSB bit output delay after SSIWSn change for Slave

transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0]=DWL[2:0]

Figure 2.58 SSI data output delay after SSIWSn change

2.3.15 SD/MMC Host Interface Timing

Table 2.30 SD/MMC Host Interface signal timing

Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register.
Clock duty ratio is 50%.
Item Symbol Min Max Unit Test conditions
SDCLK clock cycle TSDCYC 20 - ns Figure 2.59
SDCLK clock high pulse width TSDWH 6.5 - ns
SDCLK clock low pulse width TSDWL 6.5 - ns
SDCLK clock rise time TSDLH - 3 ns
SDCLK clock fall time TSDHL - 3 ns
SDCMD/SDDAT output data delay TSDODLY –6 5 ns
SDCMD/SDDAT input data setup TSDIS 4 - ns
SDCMD/SDDAT input data hold TSDIH 2 - ns

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S7G2 Datasheet 2. Electrical Characteristics

TSDCYC
TSDWL TSDWH
SDnCLK
(output) TSDLH
TSDHL TSDODLY(max) TSDODLY(min)
SDnCMD/SDnDATm
(output)
TSDIS TSDIH
SDnCMD/SDnDATm
(input)

n = 0, 1
m = 0 to 7

Figure 2.59 SD/MMC Host Interface signal timing

2.3.16 ETHERC Timing

Table 2.31 ETHERC timing

Conditions: ETHERC (RMII): Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins:
ET0_MDC, ET0_MDIO, ET1_MDC, and ET1_MDIO
For other pins, high drive output is selected in the port drive capability bit in the PmnPFS register.
ETHERC (MII): Middle drive output is selected in the port drive capability bit in the PmnPFS register
n = 0, 1.
Test
Item Symbol Min Max Unit conditions
ETHERC REF50CKn cycle time Tck 20 - ns Figure 2.60 to
(RMII) Figure 2.63
REF50CKn frequency, typical 50 MHz - - 50 + 100 ppm MHz
REF50CKn duty - 35 65 %
REF50CKn rise/fall time Tckr/ckf 0.5 3.5 ns
RMIIn_xxxx*1 output delay Tco 2.5 12.0 ns
RMIIn_xxxx*2 setup time Tsu 3 - ns
RMIIn_xxxx*2 hold time Thd 1 - ns
RMIIn_xxxx*1, *2 rise/fall time Tr/Tf 0.4 4 ns
ETn_WOL output delay tWOLd 1 23.5 ns Figure 2.64
ETHERC ETn_TX_CLK cycle time tTcyc 40 - ns -
(MII)
ETn_TX_EN output delay tTENd 1 20 ns Figure 2.65
ETn_ETXD0 to ET_ETXD3 output delay tMTDd 1 20 ns
ETn_CRS setup time tCRSs 10 - ns
ETn_CRS hold time tCRSh 10 - ns
ETn_COL setup time tCOLs 10 - ns Figure 2.66
ETn_COL hold time tCOLh 10 - ns
ETn_RX_CLK cycle time tTRcyc 40 - ns -
ETn_RX_DV setup time tRDVs 10 - ns Figure 2.67
ETn_RX_DV hold time tRDVh 10 - ns
ETn_ERXD0 to ET_ERXD3 setup time tMRDs 10 - ns
ETn_ERXD0 to ET_ERXD3 hold time tMRDh 10 - ns
ETn_RX_ER setup time tRERs 10 - ns Figure 2.68
ETn_RX_ER hold time tRESh 10 - ns
ETn_WOL output delay tWOLd 1 23.5 ns Figure 2.69

Note 1. RMIIn_TXD_EN, RMIIn_TXD1, RMIIn_TXD0.

Note 2. RMIIn_CRS_DV, RMIIn_RXD1, RMIIn_RXD0, RMIIn_RX_ER.

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S7G2 Datasheet 2. Electrical Characteristics

Tck

90% Tckr
REF50CKn 50%
Tckf
10%

Tco Tsu Thd

Tr Tf
90%
Change Change
RMIIn_xxxx *1 50% in signal Signal Change in
Signal in signal
signal level
level level
10%

n = 0, 1

Note 1. RMIIn_TXD_EN, RMIIn_TXD1, RMIIn_TXD0, RMIIn_CRS_DV, RMIIn_RXD1, RMIIn_RXD0,

RMIIn_RX_ER

Figure 2.60 REF50CKn and RMII signal timing (n = 0 and 1)

TCK

R EF50C K n

TCO

RM IIn_TX D _E N

T CO

R M IIn_TXD 1,
Pream ble SF D DAT A C RC
R M IIn_TXD 0

n = 0, 1

Figure 2.61 RMII transmission timing

REF50CKn

Tsu Thd

RMIIn_CRS_DV
Thd
Tsu

RMIIn_RXD1,
Pream ble DATA CRC
RMIIn_RXD0

SFD
RM IIn_RX_ER
L

n = 0, 1

Figure 2.62 RMII reception timing in normal operation

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S7G2 Datasheet 2. Electrical Characteristics

REF50CKn

RMIIn_CRS_DV

RMIIn_RXD1,
Preamble SFD DATA xxxx
RMIIn_RXD0
Thd
Tsu

RMIIn_RX_ER

Figure 2.63 RMII reception timing when an error occurs

REF50CK

tWOLd

ET_WOL

Figure 2.64 WOL output timing for RMII

ETn_TX_CLK
t TENd

ETn_TX_EN
tMTDd

ETn_ETXD[3:0] Preamble SFD DATA CRC

ETn_TX_ER
t CRSs t CRSh

ETn_CRS

ETn_COL

n = 0, 1

Figure 2.65 MII transmission timing in normal operation

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ETn_TX_CLK

ETn_TX_EN

ETn_ETXD[3:0] Pream ble JAM

ETn_TX_ER

ETn_CRS t COLs t COLh

ETn_COL

n = 0, 1

Figure 2.66 MII transmission timing when a conflict occurs

ETn_RX_CLK

t RDVs t RDVh

ETn_RX_DV
tMRDh
tM RDs

ETn_ERXD[3:0] Preamble SFD DATA CRC

ETn_RX_ER

n = 0, 1

Figure 2.67 MII reception timing in normal operation

E T n_R X _C LK

E T n _R X _ D V

E T n _E R X D [3:0] P rea m b le SFD DATA xxxx

tR ER h
tR E R s

E T n _R X _ E R

n = 0, 1

Figure 2.68 MII reception timing when an error occurs

ETn_R X_CLK

tW O Ld

ETn_W O L

n = 0, 1

Figure 2.69 WOL output timing for MII

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S7G2 Datasheet 2. Electrical Characteristics

2.3.17 PDC Timing

Table 2.32 PDC timing

Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register.
Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF
Test
Item Symbol Min Max Unit conditions
PDC PIXCLK input cycle time tPIXcyc 37 - ns Figure 2.70
PIXCLK input high pulse width tPIXH 10 - ns
PIXCLK input low pulse width tPIXL 10 - ns
PIXCLK rise time tPIXr - 5 ns
PIXCLK fall time tPIXf - 5 ns
PCKO output cycle time tPCKcyc 2 × tPBcyc - ns Figure 2.71
PCKO output high pulse width tPCKH (tPCKcyc – tPCKr – tPCKf)/2 – 3 - ns
PCKO output low pulse width tPCKL (tPCKcyc – tPCKr – tPCKf)/2 – 3 - ns
PCKO rise time tPCKr - 5 ns
PCKO fall time tPCKf - 5 ns
VSYNV/HSYNC input setup time tSYNCS 10 - ns Figure 2.72
VSYNV/HSYNC input hold time tSYNCH 5 - ns
PIXD input setup time tPIXDS 10 - ns
PIXD input hold time tPIXDH 5 - ns

Note 1. tPBcyc: PCLKB cycle.

tPIXcyc

tPIXH tPIXf

PIXCLK input

tPIXr
tPIXL

Figure 2.70 PDC input clock timing

tPCKcyc

tPCKH tPCKf

PCKO pin output

tPCKr
tPCKL

Figure 2.71 PDC output clock timing

PIXCLK

tSYNCS tSYNCH

VSYNC

tSYNCS tSYNCH
HSYNC

tPIXDS tPIXDH
PIXD7 to PIXD0

Figure 2.72 PDC AC timing

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S7G2 Datasheet 2. Electrical Characteristics

2.3.18 Graphics LCD Controller Timing

Table 2.33 Graphics LCD Controller timing

Conditions:
LCD_CLK: High drive output is selected in the port drive capability bit in the PmnPFS register.
LCD_DATA: Middle drive output is selected in the port drive capability bit in the PmnPFS register.
Item Symbol Min Typ Max Unit Test conditions
LCD_EXTCLK input clock frequency tEcyc - - 60*1 MHz Figure 2.73
LCD_EXTCLK input clock low pulse width tWL 0.45 - 0.55 tEcyc
LCD_EXTCLK input clock high pulse width tWH 0.45 - 0.55
LCD_CLK output clock frequency tLcyc - - 60*1 MHz Figure 2.74
LCD_CLK output clock low pulse width tLOL 0.4 - 0.6 tLcyc Figure 2.74
LCD_CLK output clock high pulse width tLOH 0.4 - 0.6 tLcyc Figure 2.74
LCD data output delay timing _A or _B combinations*2 tDD –3.5 - 4 ns Figure 2.75
_A and _B combinations*3 –5.0 - 5.5

Note 1. Parallel RGB888, 666,565: Maximum 54 MHz

Serial RGB888: Maximum 60 MHz (4x speed)
Note 2. Use pins that have a letter appended to their names, for instance, “_A” or “_B”, to indicate
Note 3. Pins of group“_A” and “_B” combinations are used.

tDcyc, tEcyc
tWH tWL

VIH VIH
1/2 Vcc
VIL VIL
LCD_EXTCLK

Figure 2.73 LCD_EXTCLK clock input timing

tLcyc

tLOL tLOH

LCD_CLK

tLOF tLOR

Figure 2.74 LCD_CLK clock output timing

LCD_CLK

tDD

Output on
falling edge
LCD_DATA00 to
LCD_DATA23, tDD
LCD_TCON0 to
LCD_TCON3 Output on
rising edge

Figure 2.75 Display output timing

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S7G2 Datasheet 2. Electrical Characteristics

2.4 USB Characteristics

2.4.1 USBHS Timing

Table 2.34 USBHS low-speed characteristics for host only (USBHS_DP and USBHS_DM pin characteristics)
Conditions: USBHS_RREF = 2.2 kΩ ± 1%, USBMCLK = 20/24 MHz, UCLK = 48 MHz
Item Symbol Min Typ Max Unit Test conditions
Input Input high voltage VIH 2.0 - - V - -
characteristics
Input low voltage VIL - - 0.8 V - -
Differential input sensitivity VDI 0.2 - - V | USBHS_DP - -
USBHS_DM |
Differential common-mode VCM 0.8 - 2.5 V - -
range
Output Output high voltage VOH 2.8 - 3.6 V IOH = –200 μA -
characteristics
Output low voltage VOL 0.0 - 0.3 V IOL= 2 mA -
Cross-over voltage VCRS 1.3 - 2.0 V - Figure 2.76,
Figure 2.77
Rise time tLR 75 - 300 ns -
Fall time tLF 75 - 300 ns -
Rise/fall time ratio tLR / tLF 80 - 125 % tLR / tLF -
Pull-up, USBHS_DP and USBHS_DM Rpd 14.25 - 24.80 kΩ -
Pull-down pull-down resistors (host)
characteristics

USBHS_DP, VCRS 90% 90%

USBHS_DM 10% 10%

tr tf

Figure 2.76 USBHS_DP and USBHS_DM output timing in low-speed mode

Observation
USBHS_DP point

200 pF to
600 pF 3.6 V

1.5 K
USBHS_DM

200 pF to
600 pF

Figure 2.77 Test circuit in low-speed mode

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S7G2 Datasheet 2. Electrical Characteristics

Table 2.35 USBHS full-speed characteristics (USBHS_DP and USBHS_DM pin characteristics)
Conditions: USBHS_RREF = 2.2 kΩ ± 1%, USBMCLK = 20/24 MHz, UCLK = 48 MHz
Item Symbol Min Typ Max Unit Test conditions
Input Input high voltage VIH 2.0 - - V - -
characteristics
Input low voltage VIL - - 0.8 V - -
Differential input sensitivity VDI 0.2 - - V | USBHS_DP - -
USBHS_DM |
Differential common-mode VCM 0.8 - 2.5 V - -
range
Output Output high voltage VOH 2.8 - 3.6 V IOH = –200 μA -
characteristics
Output low voltage VOL 0.0 - 0.3 V IOL= 2 mA -
Cross-over voltage VCRS 1.3 - 2.0 V - Figure 2.78,
Figure 2.79
Rise time tLR 4 - 20 ns -
Fall time tLF 4 - 20 ns -
Rise/fall time ratio tLR / tLF 90 - 111.11 % tFR / tFF -
Output resistance ZDRV 40.5 - 49.5 Ω Rs Not used
(PHYSET.REPSEL[1:0] = 01b
and PHYSET. HSEB = 0)
DC USBHS_DM pull-up resistor Rpu 0.900 - 1.575 kΩ During idle state
characteristics (device)
1.425 - 3.090 kΩ During transmission and
reception
USBHS_DP/USBHS_DM Rpd 14.25 - 24.80 kΩ -
pull-down resistor (host)

USBHS_DP, VCRS 90% 90%

USBHS_DM 10% 10%

tFR tFF

Figure 2.78 USBHS_DP and USBHS_DM output timing in full-speed mode

Observation
point
USBHS_DP

50 pF

USBHS_DM

50 pF

Figure 2.79 Test circuit in full-speed mode

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S7G2 Datasheet 2. Electrical Characteristics

Table 2.36 USBHS high-speed characteristics (USBHS_DP and USBHS_DM pin characteristics)
Conditions: USBHS_RREF = 2.2 kΩ ± 1%, USBMCLK = 20/24 MHz
Item Symbol Min Typ Max Unit Test conditions
Input Squelch detect sensitivity VHSSQ 100 - 150 mV Figure 2.80
characteristics
Disconnect detect sensitivity VHSDSC 525 - 625 mV Figure 2.81
Common-mode voltage VHSCM –50 - 500 mV -
Output Idle state VHSOI –10.0 - 10 mV -
characteristics
Output high voltage VHSOH 360 - 440 mV
Output low voltage VHSOL –10.0 - 10 mV
Chirp J output voltage (difference) VCHIRPJ 700 - 1100 mV
Chirp K output voltage (difference) VCHIRPK –900 - –500 mV
AC Rise time tHSR 500 - - ps Figure 2.82
characteristics
Fall time tHSF 500 - - ps
Output resistance ZHSDRV 40.5 - 49.5 Ω -

USBHS_DP, VHSSQ
USBHS_DM

Figure 2.80 USBHS_DP and USBHS_DM squelch detect sensitivity in high-speed mode

USBHS_DP, VHSDSC
USBHS_DM

Figure 2.81 USBHS_DP and USBHS_DM disconnect detect sensitivity in high-speed mode

USBHS_DP, 90% 90%

USBHS_DM 10% 10%

tHSR tHSF

Figure 2.82 USBHS_DP and USBHS_DM output timing in high-speed mode

Observation
USBHS_DP point

45 

USBHS_DM

45 

Figure 2.83 Test circuit in high-speed mode

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S7G2 Datasheet 2. Electrical Characteristics

Table 2.37 USBHS high-speed characteristics (USBHS_DP and USBHS_DM pin characteristics)
Conditions: USBHS_RREF = 2.2 kΩ ± 1%, USBMCLK = 20/24 MHz
Item Symbol Min Max Unit Test conditions
Battery Charging D+ sink current IDP_SINK 25 175 μA -
Specification
D– sink current IDM_SINK 25 175 μA -
DCD source current IDP_SRC 7 13 μA -
Data detection voltage VDAT_REF 0.25 0.4 V -
D+ source voltage VDP_SRC 0.5 0.7 V Output current = 250 μA
D– source voltage VDM_SRC 0.5 0.7 V Output current = 250 μA

2.4.2 USBFS Timing

Table 2.38 USBFS low-speed characteristics for host only (USB_DP and USB_DM pin characteristics)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, VCC_USBHS = AVCC_USBHS = 3.0
to 3.6 V, UCLK = 48 MHz
Item Symbol Min Typ Max Unit Test conditions
Input Input high voltage VIH 2.0 - - V -
characteristics
Input low voltage VIL - - 0.8 V -
Differential input sensitivity VDI 0.2 - - V | USB_DP - USB_DM |
Differential common-mode VCM 0.8 - 2.5 V -
range
Output Output high voltage VOH 2.8 - 3.6 V IOH = –200 μA
characteristics
Output low voltage VOL 0.0 - 0.3 V IOL= 2 mA
Cross-over voltage VCRS 1.3 - 2.0 V Figure 2.84
Rise time tLR 75 - 300 ns
Fall time tLF 75 - 300 ns
Rise/fall time ratio tLR / tLF 80 - 125 % tLR/ tLF
Pull-up and pull- USB_DP and USB_DM pull- Rpd 14.25 - 24.80 kΩ -
down down resistance in host
characteristics controller mode

USB_DP, VCRS 90% 90%

USB_DM 10% 10%

tLR tLF

Figure 2.84 USB_DP and USB_DM output timing in low-speed mode

Observation
point
USB_DP

200 pF to
600 pF 3.6 V
27 
1.5 K
USB_DM

200 pF to
600 pF

Figure 2.85 Test circuit in low-speed mode

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S7G2 Datasheet 2. Electrical Characteristics

Table 2.39 USBFS full-speed characteristics (USB_DP and USB_DM pin characteristics)
Conditions: VCC = AVCC0 = VCC_USB = VBATT = 3.0 to 3.6 V, 2.7 ≤ VREFH0/VREFH ≤ AVCC0, VCC_USBHS = AVCC_USBHS = 3.0
to 3.6 V, UCLK = 48 MHz
Item Symbol Min Typ Max Unit Test conditions
Input Input high voltage VIH 2.0 - - V -
characteristics
Input low voltage VIL - - 0.8 V -
Differential input sensitivity VDI 0.2 - - V | USB_DP - USB_DM |
Differential common-mode VCM 0.8 - 2.5 V -
range
Output Output high voltage VOH 2.8 - 3.6 V IOH = –200 μA
characteristics
Output low voltage VOL 0.0 - 0.3 V IOL= 2 mA
Cross-over voltage VCRS 1.3 - 2.0 V Figure 2.86
Rise time tLR 4 - 20 ns
Fall time tLF 4 - 20 ns
Rise/fall time ratio tLR / tLF 90 - 111.11 % tFR/ tFF
Output resistance ZDRV 28 - 44 Ω USBFS: Rs = 27 Ω included
Pull-up and pull- DM pull-up resistance in Rpu 0.900 - 1.575 kΩ During idle state
down device controller mode
1.425 - 3.090 kΩ During transmission and
characteristics
reception
USB_DP and USB_DM pull- Rpd 14.25 - 24.80 kΩ -
down resistance in host
controller mode

USB_DP, VCRS 90% 90%

USB_DM 10% 10%

tFR tFF

Figure 2.86 USB_DP and USB_DM output timing in full-speed mode

Observation
point
USB_DP

50 pF
27 

USB_DM

50 pF

Figure 2.87 Test circuit in full-speed mode

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S7G2 Datasheet 2. Electrical Characteristics

2.5 ADC12 Characteristics

Table 2.40 A/D conversion characteristics for unit 0

Conditions: PCLKC = 1 to 60 MHz
Item Min Typ Max Unit Test conditions
Frequency 1 - 60 MHz -

Analog input capacitance - - 30 pF -

Quantization error - ±0.5 - LSB -

Resolution - - 12 Bits -

Channel-dedicated Conversion time*1 Permissible signal 1.06 - - μs  Sampling of channel-

sample-and-hold (operation at source impedance (0.4 + 0.25)*2 dedicated sample-and-hold
circuits in use PCLKC = 60 MHz) Max. = 1 kΩ circuits in 24 states
(AN000 to AN002)  Sampling in 15 states
Offset error - ±1.5 ±3.5 LSB AN000 to AN002 = 0.25 V

Full-scale error - ±1.5 ±3.5 LSB AN000 to AN002 =

VREFH0- 0.25 V
Absolute accuracy - ±2.5 ±5.5 LSB -

DNL differential nonlinearity error - ±1.0 ±2.0 LSB -

INL integral nonlinearity error - ±1.5 ±3.0 LSB -

Holding characteristics of sample-and hold - - 20 μs -

circuits
Dynamic range 0.25 - VREFH V -
0 –0.25
Channel-dedicated Conversion time*1 Permissible signal 0.88 (0.667)*2 - - μs Sampling in 40 states
sample-and-hold (operation at source impedance
circuits not in use PCLKC = 60 MHz) Max. = 1 kΩ
(AN000 to AN002)
Offset error - ±1.0 ±2.5 LSB -

Full-scale error - ±1.0 ±2.5 LSB -

Absolute accuracy - ±2.0 ±4.5 LSB -

DNL differential nonlinearity error - ±0.5 ±1.5 LSB -

INL integral nonlinearity error - ±1.0 ±2.5 LSB -

High-precision Conversion time*1 Permissible signal 0.48 (0.267)*2 - - μs Sampling in 16 states

channels (operation at source impedance
(AN003 to AN006) PCLKC = 60 MHz) Max. = 1 kΩ
Max. = 300Ω 0.40 (0.183)*2 - - μs Sampling in 11 states
VCC = AVCC0 = 3.0 to 3.6 V
3.0 V ≤ VREFH0 ≤ AVCC0
Offset error - ±1.0 ±2.5 LSB -

Full-scale error - ±1.0 ±2.5 LSB -

Absolute accuracy - ±2.0 ±4.5 LSB -

DNL differential nonlinearity error - ±0.5 ±1.5 LSB -

INL integral nonlinearity error - ±1.0 ±2.5 LSB -

Normal-precision Conversion time*1 Permissible signal 0.88 (0.667)*2 - - μs Sampling in 40 states

channels (Operation at source impedance
(AN016 to AN021) PCLKC = 60 MHz) Max. = 1 kΩ
Offset error - ±1.0 ±5.5 LSB -

Full-scale error - ±1.0 ±5.5 LSB -

Absolute accuracy - ±2.0 ±7.5 LSB -

DNL differential nonlinearity error - ±0.5 ±4.5 LSB -

INL integral nonlinearity error - ±1.0 ±5.5 LSB -

Note: These specification values apply when there is no access to the external bus during A/D conversion. If access
occurs during A/D conversion, values might not fall within the indicated ranges.
Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for
the test conditions.
Note 2. Values in parentheses indicate the sampling time.

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S7G2 Datasheet 2. Electrical Characteristics

Table 2.41 A/D conversion characteristics for unit 1

Conditions: PCLKC = 1 to 60 MHz
Item Min Typ Max Unit Test conditions
Frequency 1 - 60 MHz -

Analog input capacitance - - 30 pF -

Quantization error - ±0.5 - LSB -

Resolution - - 12 Bits -

Channel-dedicated Conversion time*1 Permissible signal 1.06 - - μs  Sampling of channel-

sample-and-hold (operation at source impedance (0.4 + 0.25)*2 dedicated sample-and-hold
circuits in use PCLKC = 60 MHz) Max. = 1 kΩ circuits in 24 states
(AN100 to AN102)  Sampling in 15 states
Offset error - ±1.5 ±3.5 LSB AN100 to AN102 = 0.25 V

Full-scale error - ±1.5 ±3.5 LSB AN100 to AN102 =

VREFH - 0.25 V
Absolute accuracy - ±2.5 ±5.5 LSB -

DNL differential nonlinearity error - ±1.0 ±2.0 LSB -

INL integral nonlinearity error - ±1.5 ±3.0 LSB -

Holding characteristics of sample-and hold - - 20 μs -

circuits
Dynamic range 0.25 - VREFH V -
– 0.25
Channel-dedicated Conversion time*1 Permissible signal 0.88 - - μs Sampling in 40 states
sample-and-hold (Operation at source impedance (0.667)*2
circuits not in use PCLKC = 60 MHz) Max. = 1 kΩ
(AN100 to AN102)
Offset error - ±1.0 ±2.5 LSB -

Full-scale error - ±1.0 ±2.5 LSB -

Absolute accuracy - ±2.0 ±4.5 LSB -

DNL differential nonlinearity error - ±0.5 ±1.5 LSB -

INL integral nonlinearity error - ±1.0 ±2.5 LSB -

High-precision Conversion time*1 Permissible signal 0.48 - - μs Sampling in 16 states

channels (Operation at source impedance (0.267)*2
(AN103 to AN106) PCLKC = 60 MHz) Max. = 1 kΩ
Max. = 300Ω 0.40 - - μs Sampling in 11 states
(0.183)*2 VCC = AVCC0 = 3.0 to 3.6 V
3.0 V ≤ VREFH ≤ AVCC0
Offset error - ±1.0 ±2.5 LSB -

Full-scale error - ±1.0 ±2.5 LSB -

Absolute accuracy - ±2.0 ±4.5 LSB -

DNL differential nonlinearity error - ±0.5 ±1.5 LSB -

INL integral nonlinearity error - ±1.0 ±2.5 LSB -

Normal-precision Conversion time*1 Permissible signal 0.88 - - μs Sampling in 40 states

channels (Operation at source impedance (0.667)*2
(AN116 to AN120) PCLKC = 60 MHz) Max. = 1 kΩ
Offset error - ±1.0 ±5.5 LSB -

Full-scale error - ±1.0 ±5.5 LSB -

Absolute accuracy - ±2.0 ±7.5 LSB -

DNL differential nonlinearity error - ±0.5 ±4.5 LSB -

INL integral nonlinearity error - ±1.0 ±5.5 LSB -

Note: These specification values apply when there is no access to the external bus during A/D conversion. If access
occurs during A/D conversion, values might not fall within the indicated ranges.
Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for
the test conditions.
Note 2. Values in parentheses indicate the sampling time.

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S7G2 Datasheet 2. Electrical Characteristics

Table 2.42 A/D internal reference voltage characteristics

Item Min Typ Max Unit Test conditions
A/D internal reference voltage 1.20 1.25 1.30 V -
Sampling time 4.15 - - μs -

FFFh
Full-scale error

Integral nonlinearity
error (INL)
A/D converter
output code Ideal line of actual A/D
Actual A/D conversion conversion characteristic
characteristic

Ideal A/D conversion

characteristic Differential nonlinearity error (DNL)
1-LSB width for ideal A/D
conversion characteristic

Differential nonlinearity error (DNL)

1-LSB width for ideal A/D

conversion characteristic

Absolute accuracy

000h Offset error

0 Analog input voltage VREFH0
(full-scale)

Figure 2.88 Illustration of ADC12 characteristic terms

Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the
actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog
input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D
conversion characteristics, is used as an analog input voltage. For example, if 12-bit resolution is used and the reference
voltage VREFH0 = 3.072 V, then 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the analog
input voltages. If the analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D conversion
result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical A/D
conversion characteristics.
Integral nonlinearity error (INL)
Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale
errors are zeroed, and the actual output code.
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between the 1-LSB width based on the ideal A/D conversion
characteristics and the width of the actual output code.
Offset error
Offset error is the difference between the transition point of the ideal first output code and the actual first output code.
Full-scale error
Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.

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S7G2 Datasheet 2. Electrical Characteristics

2.6 DAC12 Characteristics

Table 2.43 D/A conversion characteristics

Item Min Typ Max Unit Test conditions
Resolution - - 12 Bits -
Without output amplifier
Absolute accuracy - - ±24 LSB Resistive load 2 MΩ
INL - ±2.0 ±8.0 LSB Resistive load 2 MΩ
DNL ±1.0 ±2.0 LSB -
Output impedance - 7.5 - kΩ -
Conversion time - - 3.0 μs Capacitive load 20 pF
Output voltage range 0 - VREFH V -
With output amplifier
INL - ±2.0 ±4.0 LSB -
DNL - ±1.0 ±2.0 LSB -
Conversion time - - 4.0 μs -
Resistive load 5 - - kΩ -
Capacitive load - - 50 pF -
Output voltage range 0.2 - VREFH – 0.2 V -

2.7 TSN Characteristics

Table 2.44 TSN characteristics

Item Symbol Min Typ Max Unit Test conditions
Relative accuracy - - ±1.0 - °C -
Temperature slope - - 4.1 - mV/°C -
Output voltage (at 25°C) - - 1.24 - V -
Temperature sensor start time tSTART - - 30 μs -
Sampling time - 4.15 - - μs -

2.8 OSC Stop Detect Characteristics

Table 2.45 Oscillation stop detection circuit characteristics

Item Symbol Min Typ Max Unit Test conditions
Detection time tdr - - 1 ms Figure 2.89

Main clock
tdr
OSTDSR.OSTDF

MOCO clock

ICLK

Figure 2.89 Oscillation stop detection timing

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S7G2 Datasheet 2. Electrical Characteristics

2.9 POR and LVD Characteristics

Table 2.46 Power-on reset circuit and voltage detection circuit characteristics
Item Symbol Min Typ Max Unit Test conditions
Voltage detection Power-on reset Module-stop function VPOR 2.5 2.6 2.7 V Figure 2.90
level (POR) disabled*1
Module-stop function 2.0 2.35 2.7
enabled*2
Voltage detection circuit (LVD0) Vdet0_1 2.84 2.94 3.04 Figure 2.91
Vdet0_2 2.77 2.87 2.97
Vdet0_3 2.70 2.80 2.90
Voltage detection circuit (LVD1) Vdet1_1 2.89 2.99 3.09 Figure 2.92
Vdet1_2 2.82 2.92 3.02
Vdet1_3 2.75 2.85 2.95
Voltage detection circuit (LVD2) Vdet2_1 2.89 2.99 3.09 Figure 2.93
Vdet2_2 2.82 2.92 3.02
Vdet2_3 2.75 2.85 2.95
Internal reset time Power-on reset time tPOR - 4.6 - ms Figure 2.90
LVD0 reset time tLVD0 - 0.70 - Figure 2.91
LVD1 reset time tLVD1 - 0.57 - Figure 2.92
LVD2 reset time tLVD2 - 0.57 - Figure 2.93
Minimum VCC down time tVOFF 200 - - μs Figure 2.90,
Figure 2.91
Response delay tdet - - 200 μs Figure 2.90 to
Figure 2.93
LVD operation stabilization time (after LVD is enabled) Td(E-A) - - 10 μs Figure 2.92,
Figure 2.93
Hysteresis width (LVD1 and LVD2) VLVH - 80 - mV

Note 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection
levels VPOR, Vdet1, and Vdet2 for POR and LVD.
Note 2. The low-power function is disabled and DEEPCUT[1:0] = 00b or 01b.
Note 3. The low-power function is enabled and DEEPCUT[1:0] = 11b.

tVOFF

VPOR
VCC

Internal reset signal

(active-low)

tdet tPOR tdet tdet tPOR

Figure 2.90 Power-on reset timing

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S7G2 Datasheet 2. Electrical Characteristics

tVOFF

VCC Vdet0

Internal reset signal

(active-low)
tdet tdet tLVD0

Figure 2.91 Voltage detection circuit timing (Vdet0)

tVOFF

VCC Vdet1 VLVH

LVCMPCR.LVD1E

Td(E-A)
LVD1
Comparator output

LVD1CR0.CMPE

LVD1SR.MON
Internal reset signal
(active-low)
When LVD1CR0.RN = 0

tdet tdet tLVD1

When LVD1CR0.RN = 1

tLVD1

Figure 2.92 Voltage detection circuit timing (Vdet1)

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S7G2 Datasheet 2. Electrical Characteristics

tVOFF

VCC Vdet2 VLVH

LVCMPCR.LVD2E

Td(E-A)
LVD2
Comparator output

LVD2CR0.CMPE

LVD2SR.MON
Internal reset signal
(active-low)
When LVD2CR0.RN = 0

tdet tdet tLVD2

When LVD2CR0.RN = 1

tLVD2

Figure 2.93 Voltage detection circuit timing (Vdet2)

2.10 VBATT Characteristics

Table 2.47 Battery backup function characteristics

Conditions: VCC = AVCC0 = VCC_USB = 2.7 to 3.6 V, 2.7 V  VREFH0/VRFEH  AVCC0, VBATT = 2.0 to 3.6 V
Item Symbol Min Typ Max Unit Test conditions
Voltage level for switching to battery backup VDETBATT 2.50 2.60 2.70 V Figure 2.94
Lower-limit VBATT voltage for power supply VBATTSW 2.70 - - V
switching caused by VCC voltage drop
VCC-off period for starting power supply switching tVOFFBATT 200 - - μs

Note: The VCC-off period for starting power supply switching indicates the period in which VCC is below the minimum
value of the voltage level for switching to battery backup (VDETBATT).

tVOFFBATT

VDETBATT
VCC

VBATT VBATTSW

Backup power
VCC supply VBATT supply VCC supply
area
Figure 2.94 Battery backup function characteristics

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S7G2 Datasheet 2. Electrical Characteristics

2.11 CTSU Characteristics

Table 2.48 CTSU characteristics

Item Symbol Min Typ Max Unit Test conditions
External capacitance connected to TSCAP pin Ctscap 9 10 11 nF -
TS pin capacitive load Cbase - - 50 pF -
Permissible output high current ΣIoH - - -40 mA When the mutual
capacitance method
is applied

2.12 Comparator Characteristics

Table 2.49 ACMPHS characteristics

Item Symbol Min Typ Max Unit Test conditions
Reference voltage range VREF 0 - AVCC0 V -
Input voltage range VI 0 - AVCC0 V -
Internal reference voltage - 1.20 1.25 1.30 V -
Output delay*1 Td - 50 100 ns VI = VREF ± 100 mV

Note 1. This value is the internal propagation delay.

2.13 PGA Characteristics

Table 2.50 PGA characteristics in single mode (1 of 2)

Item Symbol Min Typ Max Unit
PGAVSS input voltage range PGAVSS 0 - 0 V
AIN0 (G = 2.000) 0.050 × AVCC0 - 0.45 × AVCC0 V
AIN1 (G = 2.500) 0.047 × AVCC0 - 0.360 × AVCC0 V
AIN2 (G = 2.667) 0.046 × AVCC0 - 0.337 × AVCC0 V
AIN3 (G = 2.857) 0.046 × AVCC0 - 0.32 × AVCC0 V
AIN4 (G = 3.077) 0.045 × AVCC0 - 0.292 × AVCC0 V
AIN5 (G = 3.333) 0.044 × AVCC0 - 0.265 × AVCC0 V
AIN6 (G = 3.636) 0.042 × AVCC0 - 0.247 × AVCC0 V
AIN7 (G = 4.000) 0.040 × AVCC0 - 0.212 × AVCC0 V
AIN8 (G = 4.444) 0.036 × AVCC0 - 0.191 × AVCC0 V
AIN9 (G = 5.000) 0.033 × AVCC0 - 0.17 × AVCC0 V
AIN10 (G = 5.714) 0.031 × AVCC0 - 0.148 × AVCC0 V
AIN11 (G = 6.667) 0.029 × AVCC0 - 0.127 × AVCC0 V
AIN12 (G = 8.000) 0.027 × AVCC0 - 0.09 × AVCC0 V
AIN13 (G = 10.000) 0.025 × AVCC0 - 0.08 × AVCC0 V
AIN14 (G = 13.333) 0.023 × AVCC0 - 0.06 × AVCC0 V

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S7G2 Datasheet 2. Electrical Characteristics

Table 2.50 PGA characteristics in single mode (2 of 2)

Item Symbol Min Typ Max Unit
Gain error Gerr0 (G = 2.000) –1.0 - 1.0 %
Gerr1 (G = 2.500) –1.0 - 1.0 %
Gerr2 (G = 2.667) –1.0 - 1.0 %
Gerr3 (G = 2.857) –1.0 - 1.0 %
Gerr4 (G = 3.077) –1.0 - 1.0 %
Gerr5 (G = 3.333) –1.5 - 1.5 %
Gerr6 (G = 3.636) –1.5 - 1.5 %
Gerr7 (G = 4.000) –1.5 - 1.5 %
Gerr8 (G = 4.444) –2.0 - 2.0 %
Gerr9 (G = 5.000) –2.0 - 2.0 %
Gerr10 (G = 5.714) –2.0 - 2.0 %
Gerr11 (G = 6.667) –2.0 - 2.0 %
Gerr12 (G = 8.000) –2.0 - 2.0 %
Gerr13 (G = 10.000) –2.0 - 2.0 %
Gerr14 (G = 13.333) –2.0 - 2.0 %
Offset error Voff –8 - 8 mV

Table 2.51 PGA characteristics in differential mode

Item Symbol Min Typ Max Unit
PGAVSS input voltage range PGAVSS –0.3 - 0.3 V
Differential input voltage range (G = 1.500) AIN-PGAVSS –0.5 - 0.5 V
Input voltage range (G = 2.333) –0.4 - 0.4 V
Input voltage range (G = 4.000) –0.2 - 0.2 V
Input voltage range (G = 5.667) –0.15 - 0.15 V
Gain error G = 1.500 Gerr –2.5 - 2.5 %
G = 2.333 –2 - 2
G = 4.000 –1 - 1
G = 5.667 –1 - 1

2.14 Flash Memory Characteristics

2.14.1 Code Flash Memory Characteristics

Table 2.52 Code flash memory characteristics (1 of 2)

Conditions: Program or erase: FCLK = 4 to 60 MHz
Read: FCLK ≤ 60 MHz
FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 60 MHz
Item Symbol Min Typ Max Min Typ Max Unit
Programming time 256-byte tP256 - 0.9 13.2 - 0.4 6 ms
NPEC  100 times
8-KB tP8K - 29 176 - 13 80 ms
32-KB tP32K - 116 704 - 52 320 ms
Programming time 256-byte tP256 - 1.1 15.8 - 0.5 7.2 ms
NPEC > 100 times
8-KB tP8K - 35 212 - 16 96 ms
32-KB tP32K - 140 848 - 64 384 ms
Erasure time 8-KB tE8K - 71 216 - 39 120 ms
NPEC  100 times
32-KB tE32K - 254 864 - 141 480 ms

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S7G2 Datasheet 2. Electrical Characteristics

Table 2.52 Code flash memory characteristics (2 of 2)

Conditions: Program or erase: FCLK = 4 to 60 MHz
Read: FCLK ≤ 60 MHz
FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 60 MHz
Item Symbol Min Typ Max Min Typ Max Unit
Erasure time 8-KB tE8K - 85 260 - 47 144 ms
NPEC > 100 times
32-KB tE32K - 304 1040 - 169 576 ms
Reprogramming/erasure cycle*1 NPEC 1000*2 - - 1000*2 - - Times
Suspend delay during programming tSPD - - 264 - - 120 μs
First suspend delay during erasure in tSESD1 - - 216 - - 120 μs
suspend priority mode
Second suspend delay during erasure in tSESD2 - - 1.7 - - 1.7 ms
suspend priority mode
Suspend delay during erasure in erasure tSEED - - 1.7 - - 1.7 ms
priority mode
Forced stop command tFD - - 32 - - 20 μs
Data hold time*3*4 tDRP 20 - - 20 - - Years
Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times
(n = 1,000), erasing can be performed n times for each block. For example, when 256-byte programming is
performed 32 times for different addresses in 8-KB blocks, and then the entire block is erased, the
reprogram/erase cycle is counted as one. However, programming the same address several times as one
erasure is not enabled. (Overwriting is prohibited.)
Note 2. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed
range is from 1 to the minimum value.
Note 3. This indicates the characteristics when reprogramming is performed within the specified range, including the
minimum value.
Note 4. This result is obtained from reliability testing.

Suspension during programming

FCU
Program Suspend
command
t SPD

FSTATR0.FRDY Ready Not Ready Ready

Programming pulse Programming

Suspension during erasure in suspend priority mode

FCU
Erase Suspend Resume Suspend
command
tSESD1 tSESD2

FSTATR0.FRDY Ready Not Ready Ready Not Ready

Erasure
Erasing Erasing
pulse

Suspension during erasure in erasure priority mode

FCU
Erase Suspend
command
tSEED

FSTATR0.FRDY Ready Not Ready Ready

Erasure
Erasing
pulse

Forced Stop
FACI
Forced Stop
command
tFD

FSTATR.FRDY Not Ready Ready

Figure 2.95 Suspension and forced stop timing for flash memory programming and erasure

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S7G2 Datasheet 2. Electrical Characteristics

2.14.2 Data Flash Memory Characteristics

Table 2.53 Data flash memory characteristics

Conditions: Program or erase: FCLK = 4 to 60 MHz
Read: FCLK ≤ 60 MHz
FCLK = 4 MHz 20 MHz ≤ FCLK ≤ 60 MHz
Item Symbol Min Typ Max Min Typ Max Unit
Programming time 4-byte tDP4 - 0.36 3.8 - 0.16 1.7 ms
Erasure time 64-byte tDE64 - 3.1 18 - 1.7 10 ms
Blank check time 4-byte tDBC4 - - 84 - - 30 μs
Reprogramming/erasure cycle*1 NDPEC 125000*2 - - 125000*2 - - -
Suspend delay during programming tDSPD - - 264 - - 120 μs
First suspend delay during erasure in tDSESD1 - - 216 - - 120 μs
suspend priority mode
Second suspend delay during erasure in tDSESD2 - - 300 - - 300 μs
suspend priority mode
Suspend delay during erasing in erasure tDSEED - - 300 - - 300 μs
priority mode
Forced stop command tFD - - 32 - - 20 μs
Data hold time*3 *4 tDDRP 20 - - 20 - - Year

Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times
(n = 125,000), erasing can be performed n times for each block. For example, when 4-byte programming is
performed 16 times for different addresses in 64-byte blocks, and then the entire block is erased, the
reprogram/erase cycle is counted as one. However, programming the same address several times as one
erasure is not enabled. (Overwriting is prohibited.)
Note 2. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed
range is from 1 to the minimum value.
Note 3. This indicates the characteristics when reprogramming is performed within the specified range, including the
minimum value.
Note 4. This result is obtained from reliability testing.

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S7G2 Datasheet 2. Electrical Characteristics

2.15 Boundary Scan

Table 2.54 Boundary scan characteristics

Test
Item Symbol Min Typ Max Unit conditions
TCK clock cycle time tTCKcyc 100 - - ns Figure 2.96
TCK clock high pulse width tTCKH 45 - - ns
TCK clock low pulse width tTCKL 45 - - ns
TCK clock rise time tTCKr - - 5 ns
TCK clock fall time tTCKf - - 5 ns
TMS setup time tTMSS 20 - - ns Figure 2.97
TMS hold time tTMSH 20 - - ns
TDI setup time tTDIS 20 - - ns
TDI hold time tTDIH 20 - - ns
TDO data delay tTDOD - - 40 ns
Boundary scan circuit startup time*1 TBSSTUP tRESWP - - - Figure 2.98

Note 1. Boundary scan does not function until the power-on reset becomes negative.

tTCKcyc
tTCKH

TCK tTCKf

tTCKr
tTCKL

Figure 2.96 Boundary scan TCK timing

TCK

tTMSS tTMSH

TMS

tTDIS tTDIH

TDI

tTDOD

TDO

Figure 2.97 Boundary scan input/output timing

VCC

RES

tBSSTUP Boundary scan

(= tRESWP) execute

Figure 2.98 Boundary scan circuit startup timing

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S7G2 Datasheet 2. Electrical Characteristics

2.16 Joint Test Action Group (JTAG)

Table 2.55 JTAG

Test
Item Symbol Min Typ Max Unit conditions
TCK clock cycle time tTCKcyc 40 - - ns Figure 2.96
TCK clock high pulse width tTCKH 15 - - ns
TCK clock low pulse width tTCKL 15 - - ns
TCK clock rise time tTCKr - - 5 ns
TCK clock fall time tTCKf - - 5 ns
TMS setup time tTMSS 8 - - ns Figure 2.97
TMS hold time tTMSH 8 - - ns
TDI setup time tTDIS 8 - - ns
TDI hold time tTDIH 8 - - ns
TDO data delay time tTDOD - - 28 ns

tTCKcyc
tTCKH

TCK tTCKf
tTCKr
tTCKL

Figure 2.99 JTAG TCK timing

TCK

tTMSS tTMSH

TMS

tTDIS tTDIH

TDI

tTDOD

TDO

Figure 2.100 JTAG input/output timing

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S7G2 Datasheet 2. Electrical Characteristics

2.17 Serial Wire Debug (SWD)

Table 2.56 SWD

Test
Item Symbol Min Typ Max Unit conditions
SWCLK clock cycle time tSWCKcyc 40 - - ns Figure 2.101
SWCLK clock high pulse width tSWCKH 15 - - ns
SWCLK clock low pulse width tSWCKL 15 - - ns
SWCLK clock rise time tSWCKr - - 5 ns
SWCLK clock fall time tSWCKf - - 5 ns
SWDIO setup time tSWDS 8 - - ns Figure 2.102
SWDIO hold time tSWDH 8 - - ns
SWDIO data delay time tSWDD 2 - 28 ns

tSWCKcyc
tSWCKH
SWCLK

tSWCKL

Figure 2.101 SWD SWCLK timing

SWCLK

tSWDS tSWDH
SWDIO
(Input)

tSWDD
SWDIO
(Output)

tSWDD
SWDIO
(Output)

tSWDD
SWDIO
(Output)

Figure 2.102 SWD input/output timing

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S7G2 Datasheet 2. Electrical Characteristics

2.18 Embedded Trace Macro Interface (ETM)

Table 2.57 ETM

Test
Item Symbol Min Typ Max Unit conditions
TCLK clock cycle time tTCLKcyc 16.6 - - ns Figure 2.103
TCLK clock high pulse width tTCLKH 5.8 - - ns
TCLK clock low pulse width tTCLKL 5.8 - - ns
TCLK clock rise time tTCLKr - - 2.5 ns
TCLK clock fall time tTCLKf - - 2.5 ns
TDATA0-3 output setup time tTRDS 1.6 - - ns Figure 2.104
TDATA0-3 output hold time tTRDH 1.6 - - ns

tTCLKcyc
tTCLKH
TCLK tTCLKf
tTCLKr
tTCLKL

Figure 2.103 ETM TCLK timing

TCLK

tTRDS tTRDH tTRDS tTRDH

TDATA0-3

Figure 2.104 ETM output timing

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S7G2 Datasheet Appendix 1. Package Dimensions

Appendix 1. Package Dimensions

For information on the latest version of the package dimensions or mountings, go to “Packages” on the Renesas
Electronics Corporation website.

JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g]
P-LFBGA224-13x13-0.80 PLBG0224GA-A 224FHE 0.4

Unit: mm

B E
A
INDEX AREA

y1 S

S
A
A1

y CZ

(ZE) e

R
e

P
N
M Reference Dimensions in millimeters
Symbol
L Min Nom Max
K D 12.9 13.0 13.1
J
E 12.9 13.0 13.1
H
G A   1.40
F A1 0.30 0.35 0.40
E e  0.80 
D
b 0.40 0.45 0.50
C
(ZD)

B x1   0.15
A x2   0.08

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
y   0.10
y1   0.20
n x ݊b x1 S A B
n  224 
x2 S
ZD  0.90 
ZE  0.90 

© 2016 Renesas Electronics Corporation. All rights reserved.

Figure 1.1 224-pin BGA

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S7G2 Datasheet Appendix 1. Package Dimensions

JEITA Package Code RENESAS Code Previous Code MASS (TYP.)

P-LFBGA176-13x13-0.80 PLBG0176GE-A 176FHS-A 0.45 g

D
w S A w S B

x4
v
y1 S
S
A
A1

y S

e ZD
A Dimension in Millimeters
Reference
Symbol
Min Nom Max
D 13.0
R
e

P E 13.0
N
v 0.15
M
L w 0.20
B
K
J
A 1.40
H A1 0.35 0.40 0.45
G
F e 0.80
E b 0.45 0.50 0.55
D
x 0.08
ZE

C
B
y 0.10
A
y1 0.2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SD
b SE
xM S A B
ZD 0.90
ZE 0.90

Figure 1.2 176-pin BGA

R01DS0262EU0140 Rev.1.40 Page 108 of 116

Aug 6, 2018
S7G2 Datasheet Appendix 1. Package Dimensions

JEITA Package Code RENESAS Code Previous Code MASS[Typ.]

P-LFQFP176-24x24-0.50 PLQP0176KB-A 176P6Q-A/FP-176E/FP-176EV 1.8g

HD
*1
D

132 89

133 88

NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
b1

c1

c
HE
E
*2
Reference Dimension in Millimeters
Terminal cross section
Symbol
Min Nom Max
D 23.9 24.0 24.1
E 23.9 24.0 24.1
A2 1.4
HD 25.8 26.0 26.2
176
HE 25.8 26.0 26.2
ZE

45
A 1.7
A1 0.05 0.1 0.15
1 44
bp 0.15 0.20 0.25

A2
Index mark
A

c
ZD F b1 0.18
S c 0.09 0.145 0.20

θ
c1
A1
0.125
L
θ 0° 8°
L1
y S *3
bp
e 0.5
e
x M x 0.08
Detail F y 0.10
ZD 1.25
ZE 1.25
L 0.35 0.5 0.65
L1 1.0

Figure 1.3 176-pin LQFP

JEITA Package Code RENESAS Code Previous Code MASS[Typ.]

P-TFLGA145-7x7-0.50 PTLG0145KA-A 145F0G 0.1g

φb1
φ M S AB
w S B

φb
D φ M S AB
w S A
ZD e
A
A

N
e

M
L
K
J
H B
E

G
F
E
D
C
B
A
ZE

1 2 3 4 5 6 7 8 9 10 11 12 13 Reference Dimension in Millimeters

x4 y S Symbol
v
Min Nom Max
Index mark D 7.0
S
(Laser mark)
E 7.0
v 0.15
w 0.20
A 1.05
e 0.5
b 0.21 0.25 0.29
b1 0.29 0.34 0.39
x 0.08
y 0.08
ZD 0.5
ZE 0.5

Figure 1.4 145-pin LGA

R01DS0262EU0140 Rev.1.40 Page 109 of 116

Aug 6, 2018
S7G2 Datasheet Appendix 1. Package Dimensions

JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g]
P-LFQFP144-20x20-0.50 PLQP0144KA-B — 1.2

HD Unit: mm
*1 D

108 73

109 72

HE
E
144 *2
37

1 36 NOTE 4
NOTE)
Index area
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
NOTE 3
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
F LOCATED WITHIN THE HATCHED AREA.
S 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.

Reference Dimensions in millimeters

*3 Symbol
e bp Min Nom Max
y S M
D 19.9 20.0 20.1
E 19.9 20.0 20.1
A2  1.4 
HD 21.8 22.0 22.2
HE 21.8 22.0 22.2
A   1.7
0.25
A2

A1 0.05  0.15
A

bp 0.17 0.20 0.27

T

c 0.09  0.20
A1

Lp
T 0q 3.5q 8q
L1 e  0.5 
x   0.08
Detail F
y   0.10
Lp 0.45 0.6 0.75
L1  1.0 

© 2016 Renesas Electronics Corporation. All rights reserved.

Figure 1.5 144-pin LQFP

R01DS0262EU0140 Rev.1.40 Page 110 of 116

Aug 6, 2018
S7G2 Datasheet Appendix 1. Package Dimensions

JEITA Package Code RENESAS Code Previous Code MASS (Typ) [g]
P-LFQFP100-14x14-0.50 PLQP0100KB-B — 0.6

HD
Unit: mm
*1 D

75 51

76 50

HE
E
*2

100
26

1 25 NOTE 4
Index area NOTE)
NOTE 3 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
F
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
S
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.

Reference Dimensions in millimeters

y S Symbol
*3 Min Nom Max
e bp
M
D 13.9 14.0 14.1
E 13.9 14.0 14.1
A2  1.4 
HD 15.8 16.0 16.2
HE 15.8 16.0 16.2
0.25

A   1.7
A2
A

A1 0.05  0.15
T

bp 0.15 0.20 0.27

A1

c 0.09  0.20
Lp
T 0q 3.5q 8q
L1
e  0.5 
Detail F
x   0.08
y   0.08
Lp 0.45 0.6 0.75
L1  1.0 

© 2015 Renesas Electronics Corporation. All rights reserved.

Figure 1.6 100-pin LQFP

R01DS0262EU0140 Rev.1.40 Page 111 of 116

Aug 6, 2018
 Revision History S7G2 Microcontroller Group Datasheet

Rev. Date Summary

1.00 Feb 23, 2016 1st release
1.30 Jan 3, 2018 Updated for 1.30
1.40 Aug, 2018 Updated for 1.40

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Colophon

S7G2 Microcontroller Group Datasheet

Publication Date: Rev.1.40 Aug 6, 2018

Published by: Renesas Electronics Corporation

 Address List
General Precautions
1. Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and
quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used.
This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be
stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit
boards with mounted semiconductor devices.

2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are
indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished
product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time
when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset
by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches
the level at which resetting is specified.

3. Input of signal during power-off state

Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results
from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in
the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-
off state as described in your product documentation.

4. Handling of unused pins

Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins
of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state,
extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally,
and malfunctions occur due to the false recognition of the pin state as an input signal become possible.

5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the
clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated
with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full
stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or
by an external oscillator while program execution is in progress, wait until the target clock signal is stable.

6. Voltage application waveform at input pin

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device
stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to
prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the
input level passes through the area between VIL (Max.) and VIH (Min.).

7. Prohibition of access to reserved addresses

Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of
functions. Do not access these addresses as the correct operation of the LSI is not guaranteed.

8. Differences between products

Before changing from one product to another, for example to a product with a different part number, confirm that the
change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the
same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and
other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins,
immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a
system-evaluation test for the given product.
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© 2018 Renesas Electronics Corporation. All rights reserved.

Colophon 7.1
Back cover

Renesas Synergy™ Platform

S7G2 Microcontroller Group

R01DS0262EU0140