Ripple Carry Adder
Ripple Carry Adder
AIM:
To design and simulate Ripple Carry Adder circuit using Xilinx ISE simulation
software and verify its truth table.
BLOCK DIAGRAM:
THEORY:
RIPPLE CARRY ADDER:
A structure of multiple full adders is cascaded in a manner to give the results of the addition
of an n bit binary sequence. This adder includes cascaded full adders in its structure, so the
carry will be generated at every full adder stage in a ripple-carry adder circuit. These carry
output at each full adder stage is forwarded to its next full adder and there applied as a carry
input to it. This process continues up to its last full adder stage. So, each carry output bit is
rippled to the next stage of a full adder. For this reason, it is named as “RIPPLE CARRY
ADDER”. The most important feature of it is to add the input bit sequences whether the
sequence is 4 bit or 5 bit or any.
TRUTH TABLE:
PROGRAM:
module half_adder(a,b,sum,carry);
input a,b;
output sum,carry;
xor(sum,a,b);
and(carry,a,b);
endmodule
module full_adder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire w1,w2,w3;
half_adder ha1(a,b,w1,w2);
half_adder ha2(c,w1,sum,w3);
or(carry,w2,w3);
endmodule
module rippleadder (a, b, cin, sum, cout);
input [3:0]a,b;
input cin;
output [3:0]sum;
output cout;
wire[2:0] c;
full_adder a1(a[0],b[0],cin,sum[0],c[0]);
full_adder a2(a[1],b[1],c[0],sum[1],c[1]);
full_adder a3(a[2],b[2],c[1],sum[2],c[2]);
full_adder a4(a[3],b[3],c[2],sum[3],cout);
endmodule
VIVA QUESTIONS:
1) What is a ripple carry adder?
2) Explain the main disadvantage of a ripple carry adder in terms of propagation delay.
3) What are some common methods to improve the performance of a ripple carry adder
in digital circuit design?
4) What is the significance of the carry-in and carry-out signals in a ripple carry adder?
RESULT: