Verilog

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S module

Modale
Dnd mo dule

Modole 2

Gual. a copu oe 1 nduk im amothen mo dule - instantst


Ways ta pacily a mocdul
Trwnal logic Structure - Stiuctuval rephetentatan
* Bekavional hepsesentation
What net ?
Sanulate CRegires fp, et bemch test harress)

Use aa syntheses tool to ma it tato harduare


* (ip), Osalloscepe(P)
(ASIC °ot FPGiA) -Signal gen
VLSI Desiqn qce
Systam Fumc daston
3) ogic design
Ct-Phy.
descgm
Manual Autamatio Peeyt denfaton
6), Dasn veu
Fabication
Phyica dog
Pantonang, floos flng placament
Routing mwg analy u
Stauc
Signad antrty CKs tatk andy
Verilog laguag Featu ses

K
Po0gan

LIFO

Vernlag Modue M2
Module gets nfoted
FA
M2 Inttantiatad
M2 A M3
M3
MI

module name( Cintof fpor)


duclarctios
local net dsclarations
Parallel stathonent
end module
A BC
bA Slimple AND undon
FA module sinpland F,y)
input x,4
out pat
emd module

Behavioural dusiplion
a) Sungle AND qate
yscode
b) Vsing NAND qt folowed by

txecute )
jverdog halçadder tb. vwp halfadder tb.v
vwp halfodder .tb. wp
gtlwowe
Assiqn stotemert ) Combinatienal (mosty)
’ Behaioural descoiption
assiqn
Vetloa voriables type
Net CConturuosly drivon) (tonneton blur elomit
handw re
Camt Stoxe valuog
scd to tmodel connecti ors ntarta dfa
vetor
wine s r dme
A
FA . assig Sbar = vs

Registes
Retains lat value assiqned o it
7nert Storag elementi
combiational Ciscite álso

et
wie tri
Wamd
Wwan
f-t, ate
B

Andammata utput

wamd f
wine f
Tnitializatior 1

4 A| nconne dod meta ane set o z"


HU egit en value sct to

anteqe Cloop countog)


CGlontnig pt tie
time ( Sumulatu on

Vectoya
maltiple bit quanta ty
MSB LSB

Aragaf bt

Sumo,Sm)

* Tg [1:0] date
* Sections a! a vecto

6-bit opcata 5 bit ach


2Tg oporants
3|---, 2% 25 2)0 16 IS I| I0
OP CODE
IR
pcode =ikf4)

Sun. TR[s:2) +IRJ20:16]


Multi- Damensonat Avvays
integun onati7o7[s o7
>dim matrK
8 ,l6G
vgitenbank [sJ
32 bit alue.

Memoseres
7eg mem.bit o:QO44] 7 ak - bit words
K Contart
Jfeitying Contat Valvos
Sized / un sized fomn
<Size'< base zcnuaben
o101
4'bolol binany
12hB3c I/ (R bit her a
1000
I) la bit hera
25

* Parametens

Parameter HI 25
Program wheneves
In the pogvam
eplacel by Q5.
Redefned kegio gote
2 bit. AND, oR, NA R

out
+ Busf
tl
out
y ct =l , out=n - o,out

|butly o
and #5
m5 (f, Ae)
dolayBumulaton
for
timascale
Amit tirne

4 Ttaniain Enplit ArsDciation


poitonal aocation
(Sane ordn)
Value can be
wire
tiggndsorag coll)
Cedg oll)
lato Clurel biggd
Variable
net
* * vgutn
June
Vernlog opevators
t7 Arth met c o

Uncy
+A
Binary
A+B
-B A -B
-(AtB) A *B
A/B
A %B
Arg (ecpovemtiatir)

NOT
ag
AND Ex-OR
OR Ex -^N0R

+ Reduction op
word a-<
Unary NAND
Rducton op NOR
EXOK
EX -NOR

wire [3o]z ;

rigtt shifE
anithmetic khut
rigit
shitt
Ine«t O.

Avithmetic Shikt
as complrnont qstan.
shigt igt : 2

shikt no.

* Conditional op:
condepr
Concatnation

assign f- ja, bt bts

Matchs with dont cane


( values)
(Exad mttch )
7Opuratir Preadene.
D2Agm process
Structural
Behavioal (Haxduore linpl menlalion)
(logic)
VTranslaor

Evample 16-to- Mulhiplxer


see t
lines

Select
AND nd
2t0) OR gtes
mux 4o ux2o
mulbto|

Evonpl 2. I6- Bit Addex


Gronoration of Statar fhgs
Slqn tveor Ve ?
ALU ’Was there a cay?
s odd
ones maesult even
Pay
Owpo Resot nt.

A dadw
FA
C)

P (rel viduos)
begcn
auable fot
dilfet Syntheis(
sinlhtion! cam lor
We
dolays Bprcgy
eg) igndl (Clock end
oegun
temn
es never to: atStats
Blogk Alwp
end
begun
mutiple
Once Rus
t=o attarts 2nitinl statemut Songle
Block Tut,al
blac)Cphocolurat
comt 4 *klaok alwayt 6).
neverL
t-o) bg
test -
atdnly ock
* blaindial
bloks procedur
al lackinfit9d
g Non ofkinols
Statornonts Poocedaral BehawONal
/ &,
ascigo Dataflour
Shyles St
ption DeSCi Verilog
Sequentual statement
Blokng (-)
... end
(o) f... else

Seg. 8tatement
seatmat
else sfat

else dontCare

().case casez all x


Case (< p ) Casex dontCal

Vawiations

default t
end case
la) while (erp )
Begy. initiat
Rtat; teninate iteratoT
Var)

hou many tunes


dse a ma
ele othes Slatiment with guen
Won t be erecule

Other Co nstruct
) # timevalea)
time unit ’ tunesale

Black Gusponds untl ront epluyKOn tgges


Vent can be
f a sgnal vale
Chang of a

signal
keveral f those Sepavatel by or'bi
lst f
Comha
’ thamsition

Variable
rmot th
diag
subt adde *
sabt ful *
ubt hal *
adden full *
hay
adden
imventer
v
veilog nckBs simpleTmplment
po lo
variables all
cl) (posedg
c) b,
(a,
Qin)

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