Verilog
Verilog
Verilog
Modale
Dnd mo dule
Modole 2
K
Po0gan
LIFO
Vernlag Modue M2
Module gets nfoted
FA
M2 Inttantiatad
M2 A M3
M3
MI
Behavioural dusiplion
a) Sungle AND qate
yscode
b) Vsing NAND qt folowed by
txecute )
jverdog halçadder tb. vwp halfadder tb.v
vwp halfodder .tb. wp
gtlwowe
Assiqn stotemert ) Combinatienal (mosty)
’ Behaioural descoiption
assiqn
Vetloa voriables type
Net CConturuosly drivon) (tonneton blur elomit
handw re
Camt Stoxe valuog
scd to tmodel connecti ors ntarta dfa
vetor
wine s r dme
A
FA . assig Sbar = vs
Registes
Retains lat value assiqned o it
7nert Storag elementi
combiational Ciscite álso
et
wie tri
Wamd
Wwan
f-t, ate
B
Andammata utput
wamd f
wine f
Tnitializatior 1
Vectoya
maltiple bit quanta ty
MSB LSB
Aragaf bt
Sumo,Sm)
* Tg [1:0] date
* Sections a! a vecto
Memoseres
7eg mem.bit o:QO44] 7 ak - bit words
K Contart
Jfeitying Contat Valvos
Sized / un sized fomn
<Size'< base zcnuaben
o101
4'bolol binany
12hB3c I/ (R bit her a
1000
I) la bit hera
25
* Parametens
Parameter HI 25
Program wheneves
In the pogvam
eplacel by Q5.
Redefned kegio gote
2 bit. AND, oR, NA R
out
+ Busf
tl
out
y ct =l , out=n - o,out
|butly o
and #5
m5 (f, Ae)
dolayBumulaton
for
timascale
Amit tirne
Uncy
+A
Binary
A+B
-B A -B
-(AtB) A *B
A/B
A %B
Arg (ecpovemtiatir)
NOT
ag
AND Ex-OR
OR Ex -^N0R
+ Reduction op
word a-<
Unary NAND
Rducton op NOR
EXOK
EX -NOR
wire [3o]z ;
rigtt shifE
anithmetic khut
rigit
shitt
Ine«t O.
Avithmetic Shikt
as complrnont qstan.
shigt igt : 2
shikt no.
* Conditional op:
condepr
Concatnation
Select
AND nd
2t0) OR gtes
mux 4o ux2o
mulbto|
A dadw
FA
C)
P (rel viduos)
begcn
auable fot
dilfet Syntheis(
sinlhtion! cam lor
We
dolays Bprcgy
eg) igndl (Clock end
oegun
temn
es never to: atStats
Blogk Alwp
end
begun
mutiple
Once Rus
t=o attarts 2nitinl statemut Songle
Block Tut,al
blac)Cphocolurat
comt 4 *klaok alwayt 6).
neverL
t-o) bg
test -
atdnly ock
* blaindial
bloks procedur
al lackinfit9d
g Non ofkinols
Statornonts Poocedaral BehawONal
/ &,
ascigo Dataflour
Shyles St
ption DeSCi Verilog
Sequentual statement
Blokng (-)
... end
(o) f... else
Seg. 8tatement
seatmat
else sfat
else dontCare
Vawiations
default t
end case
la) while (erp )
Begy. initiat
Rtat; teninate iteratoT
Var)
Other Co nstruct
) # timevalea)
time unit ’ tunesale
signal
keveral f those Sepavatel by or'bi
lst f
Comha
’ thamsition
Variable
rmot th
diag
subt adde *
sabt ful *
ubt hal *
adden full *
hay
adden
imventer
v
veilog nckBs simpleTmplment
po lo
variables all
cl) (posedg
c) b,
(a,
Qin)