UA9638

SLLS112D – APRIL 1994 – REVISED MARCH 2024

uA9638C Dual High-Speed Differential Line Driver

1 Features 3 Description
• Meets or exceeds ANSI standard EIA/TIA-422-B The uA9638 is a dual high-speed differential line
• Operates from a single 5V power supply driver designed to meet ANSI Standard EIA/TIA-422-
• Drives loads as low as 50Ω up to 15Mbps B. The inputs are TTL and CMOS compatible and
• TTL- and CMOS-input compatibility have input clamp diodes. Schottky-diode-clamped
• Output short-circuit protection transistors are used to minimize propagation delay
• Interchangeable with DS9638 time. This device operates from a single 5V power
supply and is supplied in an 8-pin package.
2 Applications
The uA9638 provides the current needed to drive low-
• Factory automation
impedance loads at high speeds. Typically used with
• ATM and cash counters
twisted-pair cabling and differential receiver(s), base-
• Smart grid
band data transmission can be accomplished up to
• AC and servo motor drives
and exceeding 15Mbps in properly designed systems.
The uA9637A dual line receiver is commonly used as
the receiver. For even faster switching speeds in the
same pin configuration, see the SN75ALS191.
The uA9638 is characterized for operation from 0°C to
70°C.
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
SOIC (D, 8) 4.9mm × 6mm
uA9638
PDIP (P, 8) 9.81mm × 9.43mm

(1) For more information, see Section 10.

(2) The package size (length × width) is a nominal value and
includes pins, where applicable.

Logic Symbol† Logic Diagram

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UA9638
SLLS112D – APRIL 1994 – REVISED MARCH 2024 www.ti.com

Table of Contents
1 Features............................................................................1 6 Parameter Measurement Information............................ 6
2 Applications..................................................................... 1 7 Device Functional Modes............................................... 7
3 Description.......................................................................1 8 Device and Documentation Support..............................8
4 Pin Configuration and Functions...................................3 8.1 Support Resources..................................................... 8
5 Specifications.................................................................. 4 8.2 Trademarks................................................................. 8
5.1 Absolute Maximum Ratings........................................ 4 8.3 Electrostatic Discharge Caution..................................8
5.2 Dissipation Rating Table............................................. 4 8.4 Glossary......................................................................8
5.3 Recommended Operating Conditions.........................4 9 Revision History.............................................................. 8
5.4 Thermal Information....................................................4 10 Mechanical, Packaging, and Orderable
5.5 Electrical Characteristics.............................................5 Information...................................................................... 8
5.6 Switching Characteristics............................................5

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4 Pin Configuration and Functions

Figure 4-1. D (SOIC) or P (PDIP) Package

(Top View)

Table 4-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NAME NO.
VCC 1 P 5V Supply Positive Terminal Connection
1A 2 I Single Ended Data Input for Channel 1
2A 3 I Single Ended Data Input for Channel 2
GND 4 GND Device Ground
2Z 5 O Inverting Output of Differential Driver for Channel 2
2Y 6 O Non-Inverting Output of Differential Driver for Channel 2
1Z 7 O Inverting Output of Differential Driver for Channel 1
1Y 8 O Non-Inverting Output of Differential Driver for Channel 1

(1) Signal Types: I = Input, O = Output, I/O = Input or Output, P = Power, GND = GND.

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage range −0.5 7 V
VI Input voltage range −0.5 7 V
Continuous total power dissipation See Dissipation Rating Table
TA Operating free-air temperature range 0 70 °C
Tstg Storage temperature range −65 150 °C
Lead temperature 1,6 mm (1/16 inch) from 10 seconds 260 °C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1:
Voltage values except differential output voltages are with respect to network GND.

5.2 Dissipation Rating Table

DERATING FACTOR ABOVE TA
PACKAGE TA = 25 °C POWER RATING TA = 70 °C POWER RATING
= 25°C
D 725 mW 5.8 mW/°C 464 mW
P 1000 mW 8.0 mW/°C 640 mW

5.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
High-level input voltage, VIH 2 V
Low-level input voltage, VIL 0.8 V
High-level output current, IOH −50 mA
Low-level output current, IOL 50 mA
Operating free-air temperature, TA 0 70 °C

5.4 Thermal Information

D P
THERMAL METRIC(1) (SOIC) (PDIP) UNIT
8-Pins
R θJA Junction-to-ambient thermal resistance 116.7 84.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 56.3 65.4 °C/W
R θJB Junction-to-board thermal resistance 63.4 62.1 °C/W
ψ JT Junction-to-top characterization parameter 8.8 31.3 °C/W
ψ JB Junction-to-board characterization parameter 62.6 60.4 °C/W
R θJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.

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5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIK Input clamp voltage VCC = 4.75V, II = -18mA -1 -1.2 V
VCC = 4.75V, IOH = -10mA 2.5 3.5
VOH High-level output voltage VIH = 2V, V
VIL = 0.8V IOH = -40mA 2
VCC = 4.75V, IOL =
VOL Low-level output voltage VIH = 2V, VIL = 0.8V, 0.5 V
40mA
Magnitude of differential output
|VOD1| VCC = 5.25V, IO = 0 2VOD2 V
voltage
Magnitude of differential output
|VOD2| 2 V
voltage
Change in magnitude of
Δ|VOD| (2) VCC = 4.75V to 5.25V, See Figure ±0.4 V
differential output voltage RL = 100Ω
6-1
VOC Common-mode output voltage(3) 3 V
Change in magnitude of
Δ|VOC| (2) ±0.4 V
common-mode output voltage
VO = 6V 0.1 100
IO Output current with power off VCC = 0 VO = - 0.25V -0.1 -100 μA
VO = - 0.25V to 6V ± 100
II Input current VCC = 5.25V, VI = 5.5V 50 μA
IIH High-level input current VCC = 5.25V, VI = 2.7V 25 μA
IIL Low-level input current VCC = 5.25V, VI = 0.5V -200 μA
(4)
IOS Short-circuit output current VCC = 5.25V, VO = 0 -50 -150 mA
ICC Supply current (both drivers) VCC = 5.25V, No load, All inputs at 0V 45 65 mA

(1) All typical values are at VCC = 5 V and TA = 25°C.

(2) Δ| VOD | and Δ| VOC | are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high
level to a low level or vice versa.
(3) In Standard EIA-422-A, VOC, which is the average of the two output voltages with respect to ground, is called output offset voltage,
VOS.
(4) Only one output at a time should be shorted, and duration of the short circuit should not exceed one second.

5.6 Switching Characteristics

VCC = 5V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(OD) Differential output delay time See Figure 10 20 ns
CL = 15pF, RL = 100
tt(OD) Differential output transition time 6-2 10 20 ns
tsk(o) Output skew See Figure 6-2 1

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6 Parameter Measurement Information

Figure 6-1. Differential and Common-Mode Output Voltages

A. The input pulse generator has the following characteristics: ZO = 50Ω, PRR ≤ 500kHz, tw = 100ns, tr = ≤ 5ns.
B. CL includes probe and jig capacitance.

Figure 6-2. Test Circuit and Voltage Waveforms

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7 Device Functional Modes

Figure 7-1. Schematics of Inputs and Outputs

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8 Device and Documentation Support

8.1 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.2 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.4 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 1994) to Revision D (March 2024) Page
• Changed the numbering format for tables, figures, and cross-references throughout the document................ 1

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 20-Aug-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

UA9638CD OBSOLETE SOIC D 8 TBD Call TI Call TI 0 to 70 9638C

UA9638CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 9638C Samples

UA9638CDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 9638C Samples

UA9638CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 UA9638CP Samples

UA9638CPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 UA9638CP Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 20-Aug-2024

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UA9638CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UA9638CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UA9638CDR SOIC D 8 2500 353.0 353.0 32.0
UA9638CDR SOIC D 8 2500 340.5 336.1 25.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
UA9638CP P PDIP 8 50 506 13.97 11230 4.32
UA9638CPE4 P PDIP 8 50 506 13.97 11230 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

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 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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