APPLICATION NOTE

SMPS WITH L4990 FOR MULTISYNC MONITORS

by CW Park & G. Gattavari

This paper can be used as design guide of a overcurrent protection.

flyback converter for monitors power supply. The Due to the integration of the listed functions , very
high performance PWM controller L4990 is being often used in monitors power supplies, the com-
used to meet new spec requirements for moni- ponent count is dramatically reduced .
tors power supply. The basic requirements of a The L4990 allows to design high performance
monitor power supply are listed below: power supplies for high end monitors, as 17" and
- high output power range up to 120W, with uni- 21" and also low cost power supplies for low end
versal mains voltage monitors, as 14" and 15".
- synchronisation up to 100kHz
- power management BASIC CIRCUITS AND OPERATION
- over voltage and over load protections 1. CURRENT MODE CONTROL
- easy design, simple, with lower components The L4990 is based on a current mode architec-
count ture.
The L4990 is a current mode controller developed Fig. 1 shows the current mode control circuit in
to implement single-ended topologies, off-line fly- a typical flyback converter.
back and forward, and DC- DC converters at fix A clock signal initiates the power pulse at a fre-
frequency, up to 1MHz. quency fixed by the oscillator. The output of the
This device includes some additional features as error amplifier and the primary current are com-
programmable soft start, sync in/out, disable (to pared at the inputs of the PWM comparator that
be used for overvoltage and overcurrent detec- generates the PWM signal.
tion), maximum duty cycle control and hiccup

Figure 1: Current mode control

VSUPPLY VOUT

CLOCK

VREF

+ E/A PWM
COMP
- - S
R Q
+
LATCH

RSENSE

D96IN383

AN891/1297 1/14
APPLICATION NOTE

2. START- UP CIRCUITRY AND AUXILIARY 3. OSCILLATOR AND SYNCHRONISATION

SUPPLY FUNCTIONS (PINS 2,1,4,15).
Fig. 2 shows a couple of circuit solutions on Fig. 3 shows oscillator and sync circuits.
how to wake-up the device at mains turn-on. The oscillator frequency is given by the following
formula:
Figure 2a: Low cost start-up.
1.44
f≈
Rt ⋅ Ct
Figure 3: Oscillator with synchronisation.
Rin
SYNC DC-LIM

VCC
Cin
VREF 1 15
L4990 4

RSENSE OSC 2
TIMING T INTERNAL
CLOCK PULSE
D96IN384
D96IN386

Figure 2b: Very low consumption start-up.

Figure 4: Oscillator and sync waveforms.

3V

1V
R03 Q01 D02
t
VCC V
R04 Cin

Q02 L4990 SYNC

3.5V PULSE
VREF
ZD01

D96IN385
t
V

SYNC
OSCILL
Fig2-a is well suited to applications with fixed
mains, 110 or 220Vac; it’s the cheapest and 1V
largely used system to start-up an IC with hys-
t
teretic turn-on.
Fig2-b is suggested for quick start-up and for VPIN10
autoranging applications keeping constant the
wake-up time, having low consumption after de- VOLTAGE
AT PIN 10
vice turn-on. WHEN PIN 15 = GND

ZD01 is fixing the emitter voltage of Q1 that has

to be higher than the turn-on threshold max. t
value.
When the device turns-on, the auxiliary supply will VPIN10
keep the voltage across Cin at a typ. value of 13V
while VREF rising from 0 to it’s nominal value of VOLTAGE
5V will saturate Q2 turning-off Q1. AT PIN 10
WHEN PIN 15 = VREF
At this point the current consumption from the
mains it’s only due to R4, typically above 400kΩ D96IN387 t
for 220VAC mains.

2/14
 APPLICATION NOTE

The oscillator can be synchronised by a voltage Figure 6: Over voltage protection.

pulse sent to pin1.
When the voltage at pin 1 reaches 3,5V max., Ct
is discharged and a clock pulse is generated. R12 VCC
Fig. 4 shows the correspondent voltage waveforms.
8
According to Fig 4, when pin 15 is connected to DIS
14
Vref, the internal latch divide by two the oscillator
frequency, and the switching frequency of the L4990
R13
power section became the half (and the max.
duty cycle is limited to 50%).
D96IN389
This possibility conveniently reduces the switch-
ing losses; in particular we suggest to ground
pin15 from 31 to 48KHz, and pin15 to Vref when monitor the auxiliary supply through R12 and
operating from 56 to 100KHz, as summarised be- R13.
low: After a disable function intervention, to reset the
31KHz to 48KHz: pin 15 to gnd, same frequency IC, the VCC pin has to be forced below the
as sync input. UVLO threshold (10V), or the user has to discon-
56KHz to 100KHz: pin 15 to Vref, half of sync nect the mains.
frequency.
6. CURRENT SENSE AND OVERLOAD PRO-
4. ERROR AMPLIFIER (PIN 5, PIN 6) TECTION (PIN 13, 7)
Using a feedback with optocoupler, as in monitor The current sense function is implemented at
applications, there are available two solutions: pin13, detecting the voltage drop on the sensing
resistor R10.
a) by controlling the output of the error amplifier
directly with the optotransistor; The threshold voltage at pin13 is of 1V, while in
normal operation is lower. When the voltage at
b) using the on-board error amplifier; this pin reaches 1,2V, a fault condition is de-
For this application we choose solution a), re- tected.
ducing the component count, as shown in Fig 5. The power MOS is immediately turned-off, and
the fault signal is internally latched.
Figure 5: Voltage feedback loop.
A fault reset delay is implemented by discharging
L4990
the external Soft -Start (SS) timing capacitor be-
2.5V fore resetting the fault latch and initiating a new
E/A +
soft start cycle.
- 5 VFB 14V In case of continuous fault condition, the SS ca-
pacitor is charged at 5V before being discharged
6 R54 R53
again, to that on the power elements, power MOS
COMP
PC01
and secondary diodes, the power dissipation is
kept under safety limits.
50V
C08
Figure 7: Current sensing.
R55
C61
TL431
R58

D96IN388 L4990
OUT R08
10
7 13
5. OVER VOLTAGE PROTECTION (PIN 14)
SS ISEN R11 1K
At pin 14 is present a disable function. When the
voltage at this pin is higher than 2.5V, the device
is latched, and the device current consumption is C09 C05 R10
lower than 300µA. This pin is typically used to 470pF
monitor the rectified mains or the auxiliary sup- D96IN390
ply, or overcurrents too.
In the current application this function is used to

3/14
APPLICATION NOTE

DESIGN OF FLYBACK CONVERTER FOR secondary is:

MONITOR APPLICATIONS
Ns1 Vo1 + VDf 50 + 1
1. BASIC REQUIREMENTS OF A 15" MONI- N= = = = 0.567
TOR APPLICATION NP VR 90
Switching frequency
- standby or off mode : 25kHz A popular ferrite core as the EER424215 with
- free running mode : 28kHz 1mm air gap has been chosen.
- normal mode : 31kHz to 64kHz
Mains voltage range : 85V to 264V AC AL ≅ 0.28 µH/Np2.
Operating in
- discontinuous mode at 31kHz
The primary turns are so calculated:
- continuous and discontinuous mixed mode at
higher than 31kHz.
Nominal output power : 80W NP =√ LAPL = √

425 = 39T
0.28
Output voltage and power
- V1 for H-Def : 50V, 50W Ns1= Np ⋅ 0.567 = 22 T
- V2 for Video Amp : 80V, 12W
- V3, -V4 for V-Def : 14V, 12V 10W The voltage per turn, VT, is:
- V5 for heater : 6.3V, 4W
Vo1 + 1 50 + 1
VT = = ≅ 2.32V.
Ns1 22

1-1. Transformer Calculation Taking 13 to 14V from Nd auxiliary winding for

duty cycle ,dc : 50% max. at minimum mains L4990 auto-supply, the Nd turns are calculated
and nominal output power condition. below:
efficiency η : 0.85
13 + VDf 13 + 1
Vi min : 100V DC Nd = = ≅ 6 T.
period T : 32µs VT 2.32
Vdss of Mos-Fet : 600V In the following table is represented the final spec
of the transformer, in which all the turns wind-
The peak drain voltage of power Mos-Fet is given ings have been adjusted a bit to optimise each
by: output voltage:

Winding Pin Turns

Vdsspeak = Vinmax + VR + Vspike,
Np 1 to3 40

where VR is the secondary to primary reflected Nd 8 to 7 6

voltage. Ns1 (50V) 15 to 16 21
Considering a 15% of safety margin on Vdss, Ns2 (80V) 15 to 17 33
Vdssmax results in 600V ⋅ 0.85 = 510V ;
Ns3 (14V) 11 to 12 7
Vinmax = 264 ⋅ √ 2 ≅ 370V, and considering a
Vspike = 50V, Ns4 (-12V) 10 to 11 6
VR = Vdssmax - Vinmax - Vspike = 510 - 370 - 50 = 90V Ns5 (6.3V) 13 to 14 4
The primary inductance is given by the formula:
1-2. Vdss voltage clamp circuit
(Vimin ⋅ T ⋅ dc)2 (100 ⋅ 32 ⋅ 0.5)2
LP = ⋅η= ⋅ Fig 8 shows the Vdss voltage clamp network.
2 ⋅ PO ⋅ T 2 ⋅ 80 ⋅ 32
The secondary reflected voltage and the voltage
⋅ 0.85 = 425µH spike due to the leakage inductance, are charging
C10 through D05; R18, connected in parallel, is
discharging C10.
and the primary current is given by: The power dissipation on R18 is given by :
Vimin ⋅ T ⋅ dc 100 ⋅ 32 ⋅ 0.5 V2C10 1002
IP = = = 3.76A PR18 = = = 0.45W
LP 425 R18 22000
The transformer turn ratio between primary and When all the outputs are open, at no load, this
4/14
 APPLICATION NOTE

power consumption is operating as a dummy load The turn-on initialisation restarts, and an un-
and all the output voltages remain at its nominal wanted intermittence operation will be estab-
value. lished.
Figure 8: Vdss clamp circuit. In particular, for autoranging applications and
when a high start-up capacitor value is required,
it is recommended the use of a quick start-up, as
shown in fig2-b, in order to keep almost constant
R18 the start-up time on all the operating mains
C10
range.
D05

1-5. Current sense

OUT R08 When the voltage at ISEN (pin 13) reaches 1V,
L4990 10 Q01 the current limiting function is activated.
The peak voltage at ISEN input has been calcu-
R10 lated to be 0.85V at nominal output power (for
some margin for load transients) and min.
switching frequency (31kHz).
D96IN391
Rs, current sense resistor, is calculated here be-
low:
1-3. Over- voltage protection
The turn-on threshold voltage of the device is 0.85V 0.85V
Rs = = ≅ 0.22Ω
17V max.. So, the OVP intervention is fixed by IP 3.76A
the formula:
The max. primary peak current ILIMIT is :
R12 + R13 R12 + R13
VOVP = ⋅ V14 = ⋅ 2.5V
1V
R13 R13 ILIMIT = ⋅ 3.76A = 4.42A
0.85V
When R12=33KΩ and R13=5.1KΩ, the OVP in-
tervention starts at 18.7V. The max. output power Po LIMIT, at 31kHz, is :
If Vo1 winding is strictly coupled with the auxiliary 2 2
winding, OVP intervention happen at 69V of Vo1,  ILIMIT   4.42 
38% above the nominal value.
PoLIMIT = Po ⋅   = 80 ⋅  3.76  = 110W
I
 p   
Adjustments can be done by changing the R12
and R13 values, or Nd turns or by recalculating The available output power is higher at higher
the Volt/turns. switching frequency.
The VSUPPLY, device supply voltage provided by
the power transformer after turn-on , in normal 1-6. Voltage feedback loop
conditions, is:
For a good secondary regulation is requested the
use of an optocoupler and a secondary voltage
V o1 + V D 50 + 1
VSUPPLY = ⋅ ND − VD = ⋅ 6 −1 = 13.6 V reference with an error amplifier too.
Ns1 21
The output source current of the error amplifier,
pin 6, is 1.3mA typical.
1-4. Decoupling capacitor on Vcc supply line
and start up The sink current capability of PC01 has to be
higher, at least 3 mA.
C04, capacitor in parallel to the supply voltage of
the device, is charged by the external start-up The secondary to primary feedback is stabilising
circuit, up to the turn-on threshold. the Vo1 output, by sensing it before the LC filter
to avoid possible instabilities.
It has to be large enough (we chose 470µF) to
hold the device supply voltage, in open load con- C61 is introducing a pole in the origin, and the
ditions. series of C59 and R56 is effective to suppress
high frequency parasitic oscillations.
During load transients, from nominal to no load,
the output Vo1 has some overvoltages and L4990
turns-off the power transistor until Vo1 recovers 1-7. Power management
it’s nominal value. a) Normal mode
If C04 is not big enough, the supply voltage can The control input of Q72 and Q74 are both
cross the turn-off threshold, turning-off the de- high. So, Q71, Q73 and Q75 are in satura-
vice. tion. The Horiz. and vertical processors work
5/14
APPLICATION NOTE

with a supply voltage of 14V and -12V. degaussing coil circuit consumption. It is pos-
b) Suspend mode sible to keep at less than 4W the total power
The control input of Q74 is low and high for consumption if power losses due to the leak-
Q72. age current on the 80V output is less than
So, Q73 and Q75 are off. 0.5W.
H/V deflection is stopped, MCU and heater are
working. 1-8. Oscillator and synchronisation
c) Off mode The device oscillator frequency is set at 25KHz.
All control inputs are low, and Q71, Q73 and
Q75 are off. There is no supply for heater The synchronisation is obtained by the flyback
and H/V processors. The power consumption pulse from FBT via R17and a zener diode for volt-
of this mode depends on the load current of age clamping.
the 80V output. The total input power con-
sumption, in this mode, is 2.0W at the follow- 1-9. Circuit diagram
ing conditions:
AC 220V input, 80V output open, 50V output Fig.9 shows the complete schematic diagram for
0.25W dummy, MCU current 20mA from un- a 15" monitor application, and Figg. 10 a and b
switched 14V output. show the relative PCB layout. Fig. 11 shows the
The power consumption is 1.3W increased by transformer specification.

6/14
 C11 4700pF 4KV C12

F01 AC 250V T3.15A

BD01 R19 4.7M R20 4.7M
LF01
R01 3.3 1 18
P1 C01 C02
AC IM 0.1µF 0.1µF D52
C03 220µF R18 C10 80V
400V 33K 0.1µF 17
D53
200V 50V
16 C52
R03 10K D05 100µF C62
BYW13 R51 C53 100V 100µF 100V
Q01 GND
R04 600 3 15 C54
KSP45
470K D02 1N4148 D04 RGP100 7 14 D54 220µF 100V
Q02 Q71
KTC1815Y 6.3V
ZD01 R07 47
20V C55 C71
R13 4.7K R12 33K 470µF
R05
16V R71
10K R06 27 8 13
12 D55 R72
C07 1µF C04 470µF HEATER
15 14 9 CONTROL
4 8 C56 Q72
470µF 25V OFF
R05
10K 3 R08 22 Q01 11 C57
10 STP6 470µF 25V NOR SUSPEND
2
R09 5.6K NA60FI 14V
Figure 9: Complete PS. schematic diagram for 15" monitor.

C06 6800pF 10 D56 UNSWITCHED

5 R11 1K R52
L4990 13 47
Q73
SYNC IN R17 1K C05 14V
1 470pF SWITCHED
12 R10 R54 R53 C58 C74 R75
ZD02 0.22 1K 4.7K 47µF 25V R73
5.6V
11
+50V 16V ZD71
7 R21 100 16V
6 PC01
C09 0.01µF VR51
C08 10K C59 -12V
2.2nF 0.01µF Q75 SWITCHED

R55 R56
C61 18K 100
0.022µF R74
Q51 H/V DEF.
TL431 CONTROL
Q74
R58 SUSPEND OFF
1.2K
NOR
D96IN392A
APPLICATION NOTE

7/14
APPLICATION NOTE

Figure 10a: Printed Circuit Board Layout.(Overlay) (Dimensions: 182mm x 77.5mm).

8/14
 APPLICATION NOTE

Figure 10b: Printed Circuit Board Layout. (Bottom Layer) (Dimensions 182mm x 77.5mm).

9/14
APPLICATION NOTE

TRANSFORMER SPECIFICATION FOR 15"

MULTISYNC MONITOR
Transformer specification
CORE: EER424215
BOBBIN: VERT. 18 PIN
TOP BARRIER: 3mm
BOTTOM BARRIER: 6mm
Lp (1 - 4): 425µH

Winding specification
W/D WIRE (mm) S-F TURNS METHOD TAPE Ts
Ns4 0.5 10 - 11 6 SOLENOID 0.05 * 10 1
Ns5 0.5 11 - 12 7 SOLENOID AFTER Ns3 0.05 * 15 1
Ns6 0.5 13 - 14 4 SPACE AFTER Ns4 0.05 * 26 3
Nd 0.3 7-8 6 SPACE 1 LAYER 0.05 * 26 3
Np1/2 0.16 * 12 1-2 20 SOLENOID 0.05 * 26 3
Ns1 0.16 * 12 15 - 16 21 SOLENOID 0.05 * 26 3
Np1/2 0.16 * 12 2-4 20 SOLENOID 0.05 * 26 3
Ns2 0.3 16 - 17 12 SOLENOID 0.05 * 15 1
Ns3 0.3 17 - 18 29 SOLENOID AFTER Ns2 0.05 * 26 3

2. MEASUREMENT DATA
2-1. Efficiency at 70W, nominal output power

Mains Voltage at 31KHz at 64KHz

90Vac 86.8W 86.1W

80.6% 81.3%
110Vac 84.1W 83.8W
83.2% 83.5%
220Vac 80.3W 79.8W
87.1% 87.7%
270Vac 80.0W 80.5W
87.4% 86.9%
where in W is indicated the input power consumption at a load of 70W, and in % is indicated the sys-
tem efficiency.

2-2. Power consumption when in off mode

Conditions : 50V - 5mA, 14V- 20mA and all remaining outputs open.

Mains Voltage : 90Vac 110Vac 220Vac 270Vac

Power consum.: 1.7W 1.7W 2.0W 2.2W

10/14
 APPLICATION NOTE

3. MAIN CHARACTERISTICS OF A 17" MONI- output, the Vr is not anymore critical.

TOR APPLICATION At this point we can review also the VR value,
Switching frequency : choosing less than 100V.
- stand-by or off mode : 25KHz Considering VR = 95V and Vdp = 515V, the new
- free-running mode : 28KHz value of Vspike is:
- normal mode : 31KHz to 82KHz
Nominal output power : 90W
Vspike = 515V - 100V - 370V = 45V
Output voltage and power
- V1 for H-Def : 200V, 65W
- V2 for Video Amp : 80V, 10W Now, to limit again Vspike less than 45V, it is very
- V3, -V4 for V-Def : +14V, -12V 10W important to reduce the transformer leakage in-
- V5 for Heater : 6.3V, 5W ductance .

Figure 11: Rectifier circuits for 200V and 80V

outputs.
3-1. Transformer calculation
duty cycle, dc : 50% max. at min. mains
voltage and nominal load 200V
efficiency : 85% D52
Vimin : 100V DC
period T : 32µs
Vdss of Mos-Fet : 600V
D53
80V
The peak drain voltage of the power Mos-Fet is
given by : R51 C54
C53 220µF 100V
GND
D96IN393
Vdp = Vimax + VR + Vspike

The maximum value of VR has to be equal or

lower than Vimin to avoid negative Vdss gener- The primary transformer inductance is:
ated by ringing when the transformer has no en-
ergy. (Vimin ⋅ T ⋅ dc)2 (100 ⋅ 32 ⋅ 0.5)2
Lp = ⋅η= ⋅
Higher VR is chosen, higher Vdss is required for 2 ⋅ PO ⋅ T 2 ⋅ 90 ⋅ 32
power Mos-Fet; ⋅ 0.85 ≅ 380µH
but high VR means also Vr, reverse voltage, for
the secondary rectifier of the 200V output.
and the primary current becomes:
The peak reverse voltage of secondary diode is :
Vimin ⋅ T ⋅ dc 100 ⋅ 32 ⋅ 0.5
Vimax ⋅ Vout Ip = = = 4.2A
Vr = + Vout + Vspike Lp 380
VR
The turn ratio between primary and secondary
where Vspike is the voltage spike on the secon- winding is:
dary winding.
Considering VR = 100V and Vspike = 150V, the Ns1 + Ns2 Vo1 + 2 ⋅ VDf 200 + 2
Vr of the diode located on the 200V output results N= = = = 2.12
Np VR 95
in :
We chose the ferrite core EER424215 with 1.0
370V ⋅ 200V
Vr = + 200V + 150V = 1090V mm air gap.
100V

This reverse voltage, greater than 1000V, is ef- AL ≈ 0.28 µH/Np2

fectively too high for a fast recovery rectifier di-
ode.
Fig 11 shows a method to reduce the required NP = √
Lp = √
 = 37 T
380
reverse voltage. AL 0.28
Using this simple system to generate the 200V

11/14
APPLICATION NOTE

Considering 13 to 14V the auxiliary winding to

Ns1 + Ns2 = Np ⋅ 2.12 = 79 T supply the L4990, the number of turns is calcu-
lated as follows:
(120 + 1) ⋅ 79
Ns1 = = 47 T 13 + VDf 14
200 + 2 Nd = = =6T
VT 2.56
Ns2 = 79 - 47 = 32 T
The following paragraph shows the detailed
The volt/turn VT is: transformer windings spec and fig. 12
shows the schematic diagram of the complete
Vo1 + 2 200 +2 power supply.
VT = = = 2.56 V
Ns1 79

TRANSFORMER SPECIFICATION FOR 17" MULTISYNC MONITOR

Transformer specification
CORE: EER424215
BOBBIN: VERT. 18 PIN
TOP BARRIER: 3mm
BOTTOM BARRIER: 6mm

Winding specification
W/D WIRE (mm) S-F TURNS METHOD TAPE Ts
Ns4 0.5 10 - 11 5 SOLENOID 0.05 * 10 1
Ns5 0.5 11 - 12 6 SOLENOID AFTER Ns3 0.05 * 15 1
Ns6 0.5 13 - 14 3 SPACE AFTER Ns4 0.05 * 26 3
Nd 0.3 7-8 6 SPACE 1 LAYER 0.05 * 26 3
Np1/2 0.16 * 12 1-2 20 SOLENOID 0.05 * 26 3
Ns1 0.45 15 - 16 32 SOLENOID 0.05 * 26 3
Ns2 0.45 17 - 18 47 SOLENOID 0.05 * 15 1
Np1/2 0.16 * 12 2-4 17 SOLENOID 0.05 * 26 3

3. MEASUREMENT DATA
3-1. Efficiency at 90W, nominal output power
Mains Voltage at 31KHz at 82KHz
90Vac 112.7W 117.8W
79.9% 76.4%
110Vac 108W 112.5W
83.3% 80.0%
220Vac 102W 108.1W
88.2% 83.3%
270Vac 102.1W 108.5W
88.1% 82.9%

3-2. Power consumption when in off mode

Conditions : 0.5W on ±12V and all remaining outputs open.
Mains Voltage : 90Vac 110Vac 220Vac 270Vac
Power consum.: 1.8W 1.8W 2.6W 3.3W

12/14
 SUMMARY
C11 4700pF 4KV C12

F01 AC 250V T3.15A

BD01 R19 4.7M R20 4.7M
LF01
R01 3.3 1 18 D52
P1 C01 C02 200V
AC IM 0.1µF 0.1µF
C03 220µF R18 C10 17
400V 33K 0.1µF D53
200V 80V
16 C52
Figure 12: SMPS for 17" monitor.

R03 10K D05 100µF C62

BYW13 R51 C53 250V 100µF 100V
Q01 GND
R04 -600 3 15 C54
KSP45
470K 220µF 160V Q71
Q02 D02 1N4148 D04 RGP100 7 14 D54
KTC1815Y 6.3V
R07 47
C55 C71
R13 4.7K R012 33K 470µF
R05
16V R71
10K R06 27 8 13
12 D55 R72
C07 1µF C04 470µF HEATER

A practical flyback SMPS for 15" and 17" multi-

ity in normal operating conditions and stand-by

all the requested features for a correct functional-
sync monitors has been analysed, incorporating
15 14 9 CONTROL
4 8 C56 Q72
470µF 25V OFF
R05
10K 3 R08 22 Q01 11 C57
10 STP7 470µF 25V NOR SUSPEND
2
R09 5.6K NA60FI 14V
C06 6800pF 10 D56 Q73 UNSWITCHED
5 R11 1K R52

mode.
L4990 13 47 14V

plexity.
R017 1K SWITCHED
SYNC IN C05 C74 R75
1 470pF
12 R10 R54 R53 C58
ZD02 0.22 1K 4.7K 47µF 25V
5.6V
11 ZD71
R21 100 16V
7 R73
6 PC1
C09 0.1µF VR51
C08 22K C59 -12V
2.2nF 0.01µF Q75 SWITCHED

R55 R56
C61 68K 100
0.022µF R74
Q51 H/V DEF.
TL431 CONTROL
Q74
R58 SUSPEND OFF
1K
NOR
D96IN394A

mised, reducing the overall system cost and com-

By using the L4990 the component count is mini-
APPLICATION NOTE

13/14
APPLICATION NOTE

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-
THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
© 1997 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved
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