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EXP-8 CMOS Sangam

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Sangam Choudhary
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17 views6 pages

EXP-8 CMOS Sangam

Uploaded by

Sangam Choudhary
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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University Institute of Engineering

Department of Electronics & Communication Engineering

Experiment No: 8

Student Name: Sangam Choudhary UID: 24MEC10003

Branch: ME-ECE Section/Group: 1/A

Semester: 1st Date of Performance: 25/10/2024

Subject Code: CMOS VLSI DESIGN Subject Name: 24ECH-605

Aim: Design 06 transistor SRAM cell.

The tool used: Cadence Virtuoso 6.1.7

Technology used: 180nm CMOS process

Schematic:

24ECH-605 CMOS VLSI Design


University Institute of Engineering
Department of Electronics & Communication Engineering

Steps to start with Virtuoso:


1. Create a new folder, right-click on the folder and open new terminal
2. A new window opens. Now follow the given commands
3. csh ↩
4. source /home/install/cshrc ↩
5. virtuoso & ↩
6. A new window opens
7. Click File → Library → Name the Library →Technology →Attach to an existing technology
library →Apply and OK
8. Technology Library → gpdk180 →Apply and OK
9. New File appears →Cell view→Name the cell→ Apply and OK
10. The schematic editor window opens
11. Create instance→Library→browse→gpdk180→Cell→PMOS →Hide and place.
12. Create instance→Library→browse→gpdk180→Cell→NMOS →Hide and place.
13. Give the gnd from the analog library and respective pins with names and do the connections.

24ECH-605 CMOS VLSI Design


University Institute of Engineering
Department of Electronics & Communication Engineering

14. Save and check the circuit


15. To perform the transient analysis of the write operation, go to ADE L window → under the
analysis tab right click and a window opens → click on the trans open→ stop time(100n) →
select moderate →Apply →OK
16. Now right-click on the outputs tab→ from design→ from the schematic and select all the
input and output wires respectively→ check the plot and save box in the output tab.
17. Under the design variables tab, right-click and define a variable ‘x’ and give it value ‘1’
18. In the ADE L tab, go to setup→ stimuli→ a window displaying all the pins shows up.
19. Define the period and pulse width for the input pins respectively → Apply→ OK
20. Run the circuit. The output wave for the 6T SRAM cell’s write operation will be displayed.

24ECH-605 CMOS VLSI Design


University Institute of Engineering
Department of Electronics & Communication Engineering

21. For read operation in 6T SRAM cell, remove the BL and BL’ pin from the schematic.
22. To perform the transient analysis of the write operation, go to ADE L window → under the
analysis tab right click and a window opens → click on the trans open→ stop time(100n) →
select moderate →Apply →OK
23. Now right-click on the outputs tab→ from design→ from the schematic and select all the
input and output wires respectively→ check the plot and save box in the output tab.
24. Under the design variables tab, right-click and define a variable ‘x’ and give it value ‘1’
25. In the ADE L tab, go to setup→ stimuli→ a window displaying all the pins shows up.
26. Define the period and pulse width for the input pins respectively → Apply→ OK
27. Run the circuit. The output wave for the 6T SRAM cell’s read operation will be displayed.

24ECH-605 CMOS VLSI Design


University Institute of Engineering
Department of Electronics & Communication Engineering

Conclusion: 6T static random-access memory is a type of semiconductor memory that uses


bistable latching circuitry to store each bit. The term static differentiates it from dynamic RAM
which must be periodically refreshed. SRAM exhibits data remembrance but is still volatile in a
conventional sense, that data is eventually lost when memory is not powered.

6T SRAM CELL OPERATION

1. Standby Mode (the circuit is idle)


In standby mode word line is not asserted (word line=0), so pass transistors M5 and M6 which
connect 6t cell from bit lines are turned off. It means that cell cannot be accessed. The two
cross-coupled inverters formed by M1-M2 will continue to feedback each other as long as
they are connected to the supply, and data will hold in the latch.

2. Read Mode (the data has been requested)


In read mode, word line is asserted (word line=1), Word line enables both the access transistor
which will connect the cell from the bit lines. Now values stored in nodes (node Q and Q’)
are transferred to the bit lines. Assume that 1 is stored at node a so bit line bar will discharge
through the driver transistor (M1) and the bit line will be pull up through the Load transistors
(M3) toward VDD, a logical 1. The design of SRAM cell requires read stability (do not
disturb data when reading).

24ECH-605 CMOS VLSI Design


University Institute of Engineering
Department of Electronics & Communication Engineering

3. Write Mode (updating the contents)


Assume that the cell is originally storing a 1 and we wish to write a 0. To do this, the bit line is
lowered to 0V and bit bar is raised to VDD, and cell is selected by raising the word line to
VDD. Typically, each of the inverters is designed so that PMOS and NMOS are matched,
thus inverter threshold is kept at VDD/2. If we wish to write 0 at node Q’, M5 operates in
saturation. Initially, its source voltage is 1. Drain terminal of N2 is initially at 1 which is
pulled down by M5 because access transistor M5 is stronger than M1. Now M2 turns on and
M3 turns off, thus new value has been written which forces bit line lowered to 0V and bit
bar to VDD. SRAM to operate in write mode must have writability which is minimum bit
line voltage required to flip the state of the cell.

Evaluation Parameter Maximum Marks Marks Obtained

Student Performance 12
Viva 10

Worksheet 08

24ECH-605 CMOS VLSI Design

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