CY8C28243, CY8C28403, CY8C28413

PRELIMINARY CY8C28433, CY8C28445, CY8C28452

CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
®
PSoC Programmable System-on-Chip

Features ❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
■ Varied Resource Options Within One PSoC Device Group ❐ Analog Input on All GPIO
❐ 30 mA Analog Outputs on GPIO
■ Powerful Harvard Architecture Processor
❐ Configurable Interrupt on all GPIO
❐ M8C Processor Speeds up to 24 MHz
❐ 8x8 Multiply, 32-Bit Accumulate ■ Additional System Resources
2
❐ Low Power at High Speed ❐ Up to 2 Hardware I C Resources
❐ 3.0V to 5.25V Operating Voltage • Each Resource Implements Slave, Master, or Multi-Master
❐ Operating Voltages Down to 1.5V Using On-Chip Switched Modes
Mode Pump (SMP) • Operation Between 0 and 400 kHz
❐ Industrial Temperature Range: -40°C to +85°C ❐ Watchdog and Sleep Timers

■ Advanced Reconfigurable Peripherals (PSoC Blocks) ❐ User-Configurable Low Voltage Detection

❐ Flexible Internal Voltage References
❐ Up to 12 Rail-to-Rail Analog PSoC Blocks Provide:
❐ Integrated Supervisory Circuit
• Up to 14-Bit ADCs
❐ On-Chip Precision Voltage Reference
• Up to 9-Bit DACs
• Programmable Gain Amplifiers ■ Complete Development Tools
• Programmable Filters and Comparators ❐ Free Development Software (PSoC Designer™)

• Multiple ADC configurations ❐ Full Featured In-Circuit Emulator, and Programmer

❐ Full Speed Emulation
• Dedicated SAR ADC, up to 192 ksps with Sample and Hold
❐ Flexible and Functional Breakpoint Structure
• Up to 4 Synchronized or Independent Delta-Sigma ADCs
❐ 128K Trace Memory
for Advanced Applications
❐ Up to 4 Limited Type E Analog Blocks Provide: System Block Diagram
• Dual Channel Capacitive Sensing Capability
• Comparators with Programmable DAC Reference Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Analog
Drivers
• Up to 10-bit Single-Slope ADCs PSoC
❐ Up to 12 Digital PSoC Blocks Provide: CORE
• 8 to 32-Bit Timers, Counters, and PWMs
System Bus
• Shift Register, CRC, and PRS Modules
• Up to 3 Full-Duplex UARTs
Global Digital Interconnect
• Up to 6 Half-Duplex UARTs Global Analog Interconnect
SRAM
• Multiple Variable Data Length SPI™ Masters or Slaves 1K SROM Flash 16K
• Connectable to All GPIO CPU Core (M8C) Sleep and
Interrupt
❐ Complex Peripherals by Combining Blocks Controller
Watchdog

■ Precision, Programmable Clocking Multiple Clock Sources

❐ Internal ±2.5% 24/48 MHz Main Oscillator (Includes IMO, ILO, PLL, and ECO)
❐ Optional 32.768 kHz Crystal for Precise On-Chip Clocks
❐ Optional External Oscillator, up to 24 MHz DIGITAL SYSTEM ANALOG SYSTEM
❐ Internal Low Speed, Low Power Oscillator for Watchdog and Analog
Sleep Functionality Ref.
Digital Analog
■ Flexible On-Chip Memory Block Block
Array Array
❐ 16K Bytes Flash Program Storage 50,000 Erase/Write Cy- Analog
cles Input
Muxing
❐ 1K Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP™)
❐ Partial Flash Updates
❐ Flexible Protection Modes
POR and LVD Internal Switch
❐ EEPROM Emulation in Flash Digital 2 4 Type 2 2 I2C
Voltage Mode
Clocks MACs Decimators Blocks
System Resets Ref. Pump
■ Programmable Pin Configurations SYSTEM RESOURCES
❐ 25 mA Sink, 10 mA Drive on All GPIO

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-48111 Rev. *D Revised August 10, 2009

[+] Feedback
 PRELIMINARY
CY8C28xxx

PSoC Functional Overview alone or combined with other blocks to create 8, 16, 24, and
32-bit peripherals, which are called user modules. The digital
The PSoC family consists of many devices with On-Chip blocks can be connected to any GPIO through a series of global
Controllers. These devices are designed to replace multiple buses that can route any signal to any pin.
traditional MCU based system components with one low cost
Figure 1. Digital System Block Diagram[1]
single chip programmable component. A PSoC device includes
configurable analog blocks, digital blocks, and interconnections. Port 5 Port 3 Port 1
This architecture enables the user to create customized Port 4 Port 2 Port 0
peripheral configurations to match the requirements of each Digital Clocks To Analog
individual application. In addition, a fast CPU, Flash program From Core To System Bus System
memory, SRAM data memory, and configurable I/O are included
in a range of convenient pinouts and packages.
DIGITAL SYSTEM
The CY8C28xxx group of PSoC devices described in this data
sheet have multiple resource configuration options available. Digital PSoC Block Array
Therefore, not every resource mentioned in this data sheet is Row 0 4

Configuration

Configuration
Row Output
available for each CY8C28xxx subgroup. The CY8C28x45

Row Input
subgroup has a full feature set of all resources described. There DBC00 DBC01 DCC02 DCC03
are six more segmented subgroups that allow designers to use 4
a device with only the resources and functionality necessary for 8 8
a specific application. See Table 2 on page 6 to determine the
8 8
resources available for each CY8C28xxx subgroup. The same Row 1 4

Configuration

Configuration
Row Output
Row Input
information is also presented in more detail in the Ordering Infor-
mation section. DBC10 DBC11 DCC12 DCC13
4
The architecture for this specific PSoC device family, as shown
in the System Block Diagram on page 1, consists of four main
areas: PSoC Core, Digital System, Analog System, and System
Resources. The configurable global bus system allows all the Row 2 4
Configuration

Configuration
Row Output
Row Input

device resources to be combined into a complete custom DBC20 DBC21 DCC22 DCC23
system. PSoC CY8C28xxx family devices have up to six I/O 4
ports that connect to the global digital and analog interconnects,
providing access to up to 12 digital blocks and up to 16 analog
blocks. GIE[7:0] Global Digital GOE[7:0]
GIO[7:0] Interconnect GOO[7:0]
The PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable Digital peripheral configurations include:
general Purpose I/O (GPIO). The M8C CPU core is a powerful
processor with speeds up to 24 MHz, providing a four MIPS 8-bit ■ PWMs (8 to 16 bit, One-shot and Multi-shot capability)
Harvard architecture microcontroller.
■ PWMs with Dead band/Kill (8 to 16 bit)
Memory encompasses 16K bytes of Flash for program storage,
1K bytes of SRAM for data storage. The PSoC device incorpo- ■ Counters (8 to 32 bit)
rates flexible internal clock generators, including a 24 MHz ■ Timers (8 to 32 bit)
internal main oscillator (IMO) accurate to 2.5% over temperature
and voltage. A low power 32 kHz internal low speed oscillator ■ Full-duplex 8-bit UARTs (up to 3) with selectable parity
(ILO) is provided for the sleep timer and watch dog timer (WDT).
■ Half-duplex 8-bit UARTs (up to 6) with selectable parity
The 32.768 kHz external crystal oscillator (ECO) is available for
use as a real time clock (RTC) and can optionally generate a ■ Variable length SPI slave and master
crystal-accurate 24 MHz system clock using a PLL. ❐ Up to 6 total slaves and masters (8-bit)
PSoC GPIOs provide connections to the CPU, and digital and ❐ Supports 8 to 16 bit operation
analog resources. Each pin’s drive mode may be selected from
8 options, which allows great flexibility in external interfacing. ■ I2C slave, master, or multi-master (up to 2 available as System
Every pin also has the capability to generate a system interrupt Resources)
on high level, low level, and change from last read. ■ IrDA (up to 3)
The Digital System ■ Pseudo Random Sequence Generators (8 to 32 bit)
The Digital System is composed of up to 12 configurable digital ■ Cyclical Redundancy Checker/Generator (16 bit)
PSoC blocks. Each block is an 8-bit resource that can be used
■ Shift Register (2 to 32 bit)
Note
1. CY8C28x52 devices do not have digital block row 2. They have two digital rows with eight total digital blocks.

Document Number: 001-48111 Rev. *D Page 2 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

The Analog System Figure 2. Analog System Block Diagram for CY8C28x45 and
CY8C28x52 Devices
The Analog System is composed of up to 16 configurable analog
blocks, each containing an opamp circuit that allows the creation All GPIO

of complex analog signal flows. Some devices in this PSoC

P0[7] P0[6]
family have an analog multiplex bus that can connect to every
GPIO pin. This bus can also connect to the analog system for P0[5] P0[4]
analysis with comparators and analog-to-digital converters. It
can be split into two sections for simultaneous dual-channel P0[3] P0[2]

processing. P0[1] P0[0]

Some of the more common PSoC analog functions (most

AGNDIn RefIn
P2[6]
available as user modules) are: P2[3]

■ Analog-to-digital converters (6 to 14-bit resolution, up to 4, P2[4]

Analog Mux
selectable as Incremental or Delta Sigma) P2[1]
P2[2]

Bus
P2[0]
■ Dedicated 10-bit SAR ADC with sample rates up to 192 ksps
■ Synchronized, simultaneous Delta Sigma ADCs (up to 4)
■ Filters (2 to 8 pole band-pass, low-pass, and notch)
Array Input Configuration
■ Amplifiers (up to 4, with selectable gain to 48x)
■ Instrumentation amplifiers (up to 2, with selectable gain to 93x) ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0] ACI4[1:0] ACI5[1:0]

■ Comparators (up to 6, with 16 selectable thresholds)

■ DACs (up to 4, with 6 to 9-bit resolution) Block Array

■ Multiplying DACs (up to 4, with 6 to 9-bit resolution) ACC00 ACC01 ACC02 ACC03
ACE00 ACE01
■ High current output drivers (up to 4 with 30 mA drive) ASC10 ASD11 ASC12 ASD13
ASE10 ASE11
■ 1.3V reference (as a System Resource) ASD20 ASC21 ASD22 ASC23

■ DTMF Dialer
■ Modulators Analog Reference

■ Correlators Interface to RefHi Reference AGNDIn

Digital System RefLo Generators RefIn
■ Peak detectors AGND Bandgap

■ Many other topologies possible

M8C Interface (Address Bus, Data Bus, Etc.)

Document Number: 001-48111 Rev. *D Page 3 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Figure 3. Analog System Block Diagram for CY8C28x43 Figure 4. Analog System Block Diagram for CY8C28x33
Devices Devices
All GPIO
All GPIO

P0[7] P0[6]
P0[7]
P0[5] P0[4]
P0[5]
P0[6]
P0[3] P0[2]
P0[3]
P0[1] P0[0] P0[4]
P0[1]

AGNDIn RefIn P2[6]

P2[3]
P0[2]
P2[3]

Analog Mux
P0[0]
P2[1]
P2[4]

Bus

AGNDIn RefIn
Analog Mux

P2[1] P2[6]
P2[2]
Bus

P2[0]
P2[4]

Array Input Configuration

Array Input Configuration

ACI0[1:0] ACI1[1:0] ACI4[1:0] ACI5[1:0]

ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0]

Block Array

Block Array ACC00 ACC01

ACE00 ACE01
ACC00 ACC01 ACC02 ACC03 ASC10 ASD11
ASE10 ASE11
ASC10 ASD11 ASC12 ASD13 ASD20 ASC21

ASD20 ASC21 ASD22 ASC23

Analog Reference

Analog Reference Interface to RefHi Reference AGNDIn

Digital System RefLo Generators RefIn
Interface to Reference AGND Bandgap
RefHi AGNDIn
Digital System RefLo Generators RefIn
AGND Bandgap

M8C Interface (Address Bus, Data Bus, Etc.)

M8C Interface (Address Bus, Data Bus, Etc.)

Document Number: 001-48111 Rev. *D Page 4 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Figure 5. Analog System Block Diagram for CY8C28x23 Figure 6. Analog System Block Diagram for CY8C28x13
Devices Devices
P0[7]
All GPIO

P0[5]
P0[6]

Analog Mux
P0[7] P0[6]
P0[3]

Bus
P0[4]
P0[1] P0[5] P0[4]

P0[2]
P2[3]
P0[3] P0[2]
P0[0]
P2[1]
P0[1] P0[0]
AGNDIn RefIn

P2[6]

P2[4] Array Input

Configuration
ACI0[1:0] ACI1[1:0]

Array Input
Configuration
ACI0[1:0] ACI1[1:0] Block Array

ACE00 ACE01

Block Array ASE10 ASE11

ACC00 ACC01

ASC10 ASD11 Analog Reference

Interface to RefHi Reference AGNDIn

ASD20 ASC21
Digital System RefLo Generators RefIn
AGND Bandgap

Analog Reference
M8C Interface (Address Bus, Data Bus, Etc.)
Interface to RefHi Reference AGNDIn
Digital System RefLo Generators RefIn
AGND Bandgap

M8C Interface (Address Bus, Data Bus, Etc.)

Document Number: 001-48111 Rev. *D Page 5 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

System Resources
Table 1. PSoC Device Characteristics
System Resources, some of which are listed in the previous

Columns
sections, provide additional capability useful to complete

Outputs
Analog

Analog

Analog

Analog
Blocks

Blocks
Digital

Digital

Digital

Inputs

SRAM
Rows

Flash
Size

Size
PSoC Part

I/O
systems. Additional resources include a multiplier, multiple Number
decimators, switch mode pump, low voltage detection, and
power on reset. Statements describing the merits of each system CY8C29x66 up to 4 16 12 4 4 12 2K 32K
resource follow: 64
CY8C28xxx up to up to up to up to up to up to up to 1K 16K
■ Digital clock dividers provide three customizable clock 44 3 12 44 4 6 12/4[2]
frequencies for use in applications. The clocks can be routed
CY8C27x43 up to 2 8 12 4 4 12 256 16K
to both the digital and analog systems. Additional clocks can 44 Bytes
be generated using digital PSoC blocks as clock dividers. CY8C24x94 64 1 4 48 2 2 6 1K 16K
■ Multiply accumulate (MAC) provides fast 8-bit multiplier with CY8C24x23A up to 1 4 12 2 2 6 256 4K
32-bit accumulate, to assist in general math and digital filters. 24 Bytes
CY8C23x33 up to 1 4 12 2 2 4 256 8K
■ Up to four decimators provide custom hardware filters for digital Bytes
signal processing applications such as Delta-Sigma ADCs and CY8C21x34 up to 1 4 28 0 2 4[3] 512 8K
CapSense capacitive sensor measurement. 28 Bytes
CY8C21x23 16 1 4 8 0 2 4[3] 256 4K
■ Up to two I2C resources provide 0 to 400 kHz communication Bytes
over two wires. Slave, master, and multi-master modes are all CY8C20x34 up to 0 0 28 0 0 3[4] 512 8K
supported. I2C resources have hardware address detection 28 Bytes
capability.
■ Low Voltage Detection (LVD) interrupts can signal the appli- The devices covered by this data sheet all have the same archi-
cation of falling voltage levels, while the advanced POR (Power tecture, specifications, and ratings. However, the amount of
On Reset) circuit eliminates the need for a system supervisor. some hardware resources varies from device to device within the
group. The following table lists resources available for the
■ An internal 1.3V reference provides an absolute reference for specific device subgroups covered by this data sheet.
the analog system, including ADCs and DACs.
Table 2. CY8C28xxx Device Characteristics
■ An integrated switch mode pump (SMP) generates normal

Analog Blocks

Analog Blocks
operating voltages from a single 1.5V battery cell, providing a

Decimators
CapSense

Outputs
Regular

Limited

HW I2C

Analog

Analog
low cost boost converter.
Blocks
Digital

Digital

Inputs
PSoC Part

I/O
PSoC Device Characteristics Number

There are other PSoC device groups in addition to the one

described in this data sheet. These other PSoC device groups CY8C28x03 N 12 0 0 2 0 up to up to 0
offer even more resource options. The following table lists the 24 8
resources available for specific PSoC device groups. The PSoC
CY8C28x13 Y 12 0 4 1 2 up to up to 0
device group covered by this data sheet is highlighted. 40 40
CY8C28x23 N 12 6 0 2 2 up to up to 2
44 10
CY8C28x33 Y 12 6 4 1 4 up to up to 2
40 40
CY8C28x43 N 12 12 0 2 4 up to up to 4
44 44
CY8C28x45 Y 12 12 4 2 4 up to up to 4
44 44
CY8C28x52 Y 8 12 4 1 4 up to up to 4
24 24

Notes
2. Has 12 regular analog blocks and four limited Type-E analog blocks
3. Limited analog functionality.
4. Two analog blocks and one CapSense.

Document Number: 001-48111 Rev. *D Page 6 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Getting Started PSoC Designer also supports C language compilers developed

specifically for the devices in the PSoC family.
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development PSoC Designer Software Subsystems
Environment (IDE). This data sheet is an overview of the PSoC
System-Level View
integrated circuit and presents specific pin, register, and
electrical specifications. A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
For in depth information, along with detailed programming
model of your system inputs, outputs, and communication inter-
details, see the PSoC® Programmable System-on-Chip
faces. You define when and how an output device changes state
Technical Reference Manual for CY8C28xxx PSoC devices.
based upon any or all other system devices. Based upon the
For up-to-date ordering, packaging, and electrical specification design, PSoC Designer automatically selects one or more PSoC
information, see the latest PSoC device data sheets on the web On-Chip Controllers that match your system requirements.
at www.cypress.com/psoc.
PSoC Designer generates all embedded code, then compiles
Application Notes and links it into a programming file for a specific PSoC device.

Application notes are an excellent introduction to the wide variety Chip-Level View
of possible PSoC designs. They are located here: The chip-level view is a more traditional integrated development
www.cypress.com/psoc. Select Application Notes under the environment (IDE) based on PSoC Designer 4.4. Choose a base
Documentation tab. device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
Development Kits blocks. Examples of user modules are ADCs, DACs, Amplifiers,
PSoC Development Kits are available online from Cypress at and Filters. Configure the user modules for your chosen
www.cypress.com/shop and through a growing number of application and connect them to each other and to the proper
regional and global distributors, which include Arrow, Avnet, pins. Then generate your project. This prepopulates your project
Digi-Key, Farnell, Future Electronics, and Newark. with APIs and libraries that you can use to program your
application.
Training The device editor also supports easy development of multiple
Free PSoC technical training (on demand, webinars, and configurations and dynamic reconfiguration. Dynamic
workshops) is available online at www.cypress.com/training. The configuration allows for changing configurations at run time.
training covers a wide variety of topics and skill levels to assist
you in your designs. Hybrid Designs
You can begin in the system-level view, allow it to choose and
CYPros Consultants configure your user modules, routing, and generate code, then
Certified PSoC Consultants offer everything from technical switch to the chip-level view to gain complete control over
assistance to completed PSoC designs. To contact or become a on-chip resources. All views of the project share a common code
PSoC Consultant go to www.cypress.com/cypros. editor, builder, and common debug, emulation, and programming
tools.
Solutions Library Code Generation Tools
Visit our growing library of solution focused designs at PSoC Designer supports multiple third party C compilers and
www.cypress.com/solutions. Here you can find various appli- assemblers. The code generation tools work seamlessly within
cation designs that include firmware and hardware design files the PSoC Designer interface and have been tested with a full
that enable you to complete your designs quickly. range of debugging tools. The choice is yours.
Technical Support
Assemblers. The assemblers allow assembly code to merge
For assistance with technical issues, search KnowledgeBase seamlessly with C code. Link libraries automatically use absolute
articles and forums at www.cypress.com/support. If you cannot addressing or are compiled in relative mode, and linked with
find an answer to your question, call technical support at other software modules to get absolute addressing.
1-800-541-4736.
C Language Compilers. C language compilers are available
Development Tools that support the PSoC family of devices. The products allow you
PSoC Designer is a Microsoft® Windows-based, integrated to create complete C programs for the PSoC family devices.
development environment for the Programmable The optimizing C compilers provide all the features of C tailored
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs to the PSoC architecture. They come complete with embedded
on Windows XP or Windows Vista. libraries providing port and bus operations, standard keypad and
This system provides design database management by project, display support, and extended math functionality.
an integrated debugger with In-Circuit Emulator, in-system
Debugger
programming support, and built-in support for third-party
assemblers and C compilers. The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.

Document Number: 001-48111 Rev. *D Page 7 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Debugger commands allow the designer to read and program Width Modulator (PWM) User Module configures one or more
and read and write data memory, read and write I/O registers, digital PSoC blocks, one for each 8 bits of resolution. The user
read and write CPU registers, set and clear breakpoints, and module parameters permit you to establish the pulse width and
provide program run, halt, and step control. The debugger also duty cycle. Configure the parameters and properties to
allows the designer to create a trace buffer of registers and correspond to your chosen application. Enter values directly or
memory locations of interest. by selecting values from drop-down menus.
Online Help System Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in the PSoC
The online help system displays online, context-sensitive help Designer. These data sheets explain the internal operation of the
for the user. Designed for procedural and quick reference, each component and provide performance specifications. Each data
functional subsystem has its own context-sensitive help. This sheet describes the use of each user module parameter or driver
system also provides tutorials and links to FAQs and an Online property, and other information you may need to successfully
Support Forum to aid the designer in getting started. implement your design.
In-Circuit Emulator Organize and Connect
A low cost, high functionality ICE (In-Circuit Emulator) is You can build signal chains at the chip level by interconnecting
available for development support. This hardware has the user modules to each other and the I/O pins, or connect system
capability to program single devices. level inputs, outputs, and communication interfaces to each
The emulator consists of a base unit that connects to the PC by other with valuator functions.
way of a USB port. The base unit is universal and operates with In the system-level view, selecting a potentiometer driver to
all PSoC devices. Emulation pods for each device family are control a variable speed fan driver and setting up the valuators
available separately. The emulation pod takes the place of the to control the fan speed based on input from the pot selects,
PSoC device in the target board and performs full speed (24 places, routes, and configures a programmable gain amplifier
MHz) operation. (PGA) to buffer the input from the potentiometer, an analog to
Designing with PSoC Designer digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
The development process for the PSoC device differs from that In the chip-level view, perform the selection, configuration, and
of a traditional fixed function microprocessor. The configurable routing so that you have complete control over the use of all
analog and digital hardware blocks give the PSoC architecture a on-chip resources.
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs. Generate, Verify, and Debug
These configurable resources, called PSoC Blocks, have the
When you are ready to test the hardware configuration or move
ability to implement a wide variety of user-selectable functions.
on to developing code for the project, perform the “Generate
The PSoC development process can be summarized in the Application” step. This causes PSoC Designer to generate
following four steps: source code that automatically configures the device to your
1. Select components specification and provides the software for the system.
2. Configure components Both system-level and chip-level designs generate software
3. Organize and Connect based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
4. Generate, Verify, and Debug control and respond to hardware events at run-time and interrupt
Select Components service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
Both the system-level and chip-level views provide a library of controls the chosen application and contains placeholders for
prebuilt, pretested hardware peripheral components. In the custom code at strategic positions allowing you to further refine
system-level view, these components are called “drivers” and the software without disrupting the generated code.
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces A complete code development environment allows you to
(I2C-bus, for example), and the logic to control how they interact develop and customize your applications in C, assembly
with one another (called valuators). language, or both.

In the chip-level view, the components are called “user modules”. The last step in the development process takes place inside the
User modules make selecting and implementing peripheral PSoC Designer’s Debugger subsystem. The Debugger
devices simple, and come in analog, digital, and mixed signal downloads the HEX image to the In-Circuit Emulator (ICE) where
varieties. it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
Configure Components run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
Each of the components you select establishes the basic register
breakpoint events that include monitoring address and data bus
settings that implement the selected function. They also provide
values, memory locations and external signals.
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse

Document Number: 001-48111 Rev. *D Page 8 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Document Conventions
Acronyms Used Units of Measure
The following table lists the acronyms that are used in this A units of measure table is located in the Electrical Specifications
document. section. Table 8 on page 31 lists all the abbreviations used to
measure the PSoC devices.
Acronym Description
Numeric Naming
AC alternating current
Hexadecimal numbers are represented with all letters in
ADC analog-to-digital converter uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
API application programming interface ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
CPU central processing unit prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
CT continuous time ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
DAC digital-to-analog converter
DC direct current
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only
memory
FSR full scale range
GPIO general purpose I/O
GUI graphical user interface
HBM human body model
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
I/O input/output
IPOR imprecise power on reset
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
PLL phase-locked loop
POR power on reset
PPOR precision power on reset
PSoC Programmable System-on-Chip
PWM pulse width modulator
SAR successive approximation register
SC switched capacitor
SLIMO slow IMO
SMP switch mode pump
SRAM static random access memory

Document Number: 001-48111 Rev. *D Page 9 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Pinouts
This section describes, lists, and illustrates the CY8C28xxx PSoC device pins and pinout configurations.
The CY8C28xxx PSoC devices are available in a variety of packages which are listed and illustrated in the following tables. Every
port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, SMP, and XRES are not capable of Digital I/O.

20-Pin Part Pinout

Table 3. 20-Pin Part Pinout (SSOP)

Pin Type Pin CY8C28243 20-Pin PSoC Device
Description
No. Digital Analog Name
1 I/O I, M, S P0[7] Analog column mux and SAR ADC S, AI, M, P0[7] 1 20 Vdd
input.[6] S, AIO, M, P0[5] 2 19 P0[6], M, AI, S
2 I/O I/O, M, S P0[5] Analog column mux and SAR ADC S, AIO, M, P0[3] 3 18 P0[4], M, AIO, S
input. Analog column output.[6, 7] S, AI, M, P0[1] 4 17 P0[2], M, AIO, S
SMP 5 16 P0[0], M, AI, S
3 I/O I/O, M, S P0[3] Analog column mux and SAR ADC SSOP
I2C0 SCL, M, P1[7] 6 15 XRES
input. Analog column output.[6, 7]
I2C0 SDA, M, P1[5] 7 14 P1[6], M, I2C1 SCL
4 I/O I, M, S P0[1] Analog column mux and SAR ADC M, P1[3] 8 13 P1[4], M, EXTCLK
input. [6]
I2C0 SCL, XTALin, M, P1[1] 9 12 P1[2], M, I2C1 SDA
5 Output SMP Switch Mode Pump (SMP) Vss 10 11 P1[0], M, XTALout, I2C0 SDA
connection to external components.
6 I/O M P1[7] I2C0 Serial Clock (SCL).
7 I/O M P1[5] I2C0 Serial Data (SDA).
8 I/O M P1[3]
9 I/O M P1[1] Crystal Input (XTALin), I2C0 Serial
Clock (SCL), ISSP-SCLK[5].
10 Power Vss Ground connection.
11 I/O M P1[0] Crystal Output (XTALout), I2C0
Serial Data (SDA), ISSP-SDATA[5].
12 I/O M P1[2] I2C1 Serial Data (SDA).[8]
13 I/O M P1[4] Optional External Clock Input
(EXTCLK).
14 I/O M P1[6] I2C1 Serial Clock (SCL).[8]
15 Input XRES Active high external reset with
internal pull down.
16 I/O I, M, S P0[0] Analog column mux and SAR ADC
input.[6]
17 I/O I/O, M, S P0[2] Analog column mux and SAR ADC
input. Analog column output.[6, 9]
18 I/O I/O, M, S P0[4] Analog column mux and SAR ADC
input. Analog column output.[6, 9]
19 I/O I, M, S P0[6] Analog column mux and SAR ADC
input.[6]
20 Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input.

Notes
5. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for CY8C28xxx
PSoC devices for details.
6. CY8C28x52 and CY8C28x23 devices do not have a SAR ADC. Therefore, this pin does not function as a SAR ADC input for these devices.
7. CY8C28x13 and CY8C28x03 devices do not have any analog output buffers. Therefore, this pin does not function as an analog column output for these devices.
8. CY8C28x52, CY8C28x13, and CY8C28x33 devices only have one I2C block. Therefore, this GPIO does not function as an I2C pin for these devices.
9. CY8C28x33, CY8C28x23, CY8C28x13, and CY8C28x03 devices do not have an analog output buffer for this pin. Therefore, this pin does not function as an analog
column output for these devices.

Document Number: 001-48111 Rev. *D Page 10 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

28-Pin Part Pinout

Table 4. 28-Pin Part Pinout (SSOP)

Pin
Type
Pin
Description CY8C28403, CY8C28413, CY8C28433, CY8C28445, and
No. Digital Analog Name CY8C28452 28-Pin PSoC Devices

1 I/O I, M, S P0[7] Analog column mux and SAR ADC

input.[6] S, AI, M, P0[7] 1 28 Vdd
2 I/O I/O, M, S P0[5] Analog column mux and SAR ADC input. S, AIO, M, P0[5] 2 27 P0[6], M, AI, S
Analog column output.[6, 7] S, AIO, M, P0[3] 3 26 P0[4], M, AIO, S
3 I/O I/O, M, S P0[3] Analog column mux and SAR ADC input. S, AI, M, P0[1] 4 25 P0[2], M, AIO, S
Analog column output.[6, 7] M, P2[7] 5 24 P0[0], M, AI, S
4 I/O I, M, S P0[1] Analog column mux and SAR ADC M, P2[5] 6 23 P2[6], M, External VRef
input.[6] AI, M, P2[3] 7 22 P2[4], M, External AGND
SSOP
5 I/O M P2[7] AI, M, P2[1] 8 21 P2[2], M, AI
SMP 9 20 P2[0], M, AI
6 I/O M P2[5]
I2C0 SCL, M, P1[7] 10 19 XRES
7 I/O I, M P2[3] Direct switched capacitor block input.[10] I2C0 SDA, M, P1[5] 11 18 P1[6], M, I2C1 SCL
8 I/O I, M P2[1] Direct switched capacitor block input.[10] M, P1[3] 12 17 P1[4], M, EXTCLK
9 Output SMP Switch Mode Pump (SMP) connection to I2C0 SCL, XTALin, M, P1[1] 13 16 P1[2], M, I2C1 SDA
external components. Vss 14 15 P1[0], M, XTALout, I2C0 SDA
10 I/O M P1[7] I2C0 Serial Clock (SCL).
11 I/O M P1[5] I2C0 Serial Data (SDA).
12 I/O M P1[3]
13 I/O M P1[1] Crystal Input (XTALin), I2C0 Serial Clock
(SCL), ISSP-SCLK[5].
14 Power Vss Ground connection.
15 I/O M P1[0] Crystal Output (XTALout), I2C0 Serial
Data (SDA), ISSP-SDATA[5].
16 I/O M P1[2] I2C1 Serial Data (SDA).[8]
17 I/O M P1[4] Optional External Clock Input (EXTCLK).
18 I/O M P1[6] I2C1 Serial Clock (SCL).[8]
19 Input XRES Active high external reset with internal
pull down.
20 I/O I, M P2[0] Direct switched capacitor block input.[11]
21 I/O I, M P2[2] Direct switched capacitor block input.[11]
22 I/O M P2[4] External Analog Ground (AGND).
23 I/O M P2[6] External Voltage Reference (VRef).
24 I/O I, M, S P0[0] Analog column mux and SAR ADC
input.[6]
25 I/O I/O, M, S P0[2] Analog column mux and SAR ADC input.
Analog column output.[6, 9]
26 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input.
Analog column output.[6, 9]
27 I/O I, M, S P0[6] Analog column mux and SAR ADC
input.[6]
28 Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input

Notes
10. This pin is not a direct switched capacitor block analog input for CY8C28x03 and CY8C28x13 devices.
11. This pin is not a direct switched capacitor block analog input for CY8C28x03, CY8C28x13, CY8C28x23, and CY8C28x33 devices.

Document Number: 001-48111 Rev. *D Page 11 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

44-Pin Part Pinout

Table 5. 44-Pin Part Pinout (TQFP)
Pin Type Pin CY8C28513, CY8C28533, and CY8C28545
Description 44-Pin PSoC Devices
No. Digital Analog Name
1 I/O M P2[5]

P2[6], M, External VRef

2 I/O I, M P2[3] Direct switched capacitor block input.[10]
3 I/O I, M P2[1] Direct switched capacitor block input.[10]

P0[3], M, AIO, S
P0[5], M, AIO, S

P0[4], M, AIO, S
P0[2], M, AIO, S
P0[1], M, AI, S

P0[7], M, AI, S

P0[6], M, AI, S

P0[0], M, AI, S
4 I/O M P4[7]
5 I/O M P4[5]

P2[7], M
6 I/O M P4[3]

Vdd
7 I/O M P4[1]
8 Output SMP Switch Mode Pump (SMP) connection to

44
43
42
41
40
39
38
37
36
35
34
external components.
9 I/O M P3[7] M, P2[5] 1 33 P2[4], M, External AGND
AI, M, P2[3] 2 32 P2[2], M, AI
10 I/O M P3[5]
AI, M, P2[1] 3 31 P2[0], M, AI
11 I/O M P3[3] M, P4[7] 4 30 P4[6], M
12 I/O M P3[1] M, P4[5] 5 29 P4[4], M
13 I/O M P1[7] I2C0 Serial Clock (SCL). M, P4[3] 6 TQFP 28 P4[2], M
14 I/O M P1[5] I2C0 Serial Data (SDA). M, P4[1] 7 27 P4[0], M
15 I/O M P1[3] SMP 8 26 XRES
16 I/O M P1[1] Crystal Input (XTALin), I2C0 Serial Clock M, P3[7] 9 25 P3[6], M
(SCL), ISSP-SCLK[5]. M, P3[5] 10 24 P3[4], M
17 Output Vss Ground connection. M, P3[3] 11 23 P3[2], M, I2C1 SCL

12
13
14
15
16
17
18
19
20
21
22
18 I/O M P1[0] Crystal Output (XTALout), I2C0 Serial Data
(SDA), ISSP-SDATA[5].

Vss
I2C0 SDA, M, P1[5]

I2C0 SCL, XTALin, M, P1[1]

M, P3[1]

M, P1[3]

I2C1 SDA, M, P1[2]

I2C1 SDA, M, P3[0]

I2C0 SDA, XTALout, M, P1[0]

EXTCLK, M, P1[4]
I2C0 SCL, M, P1[7]

I2C1 SCL, M, P1[6]

19 I/O M P1[2] I2C1 Serial Data (SDA).[8]
20 I/O M P1[4] Optional External Clock Input (EXTCLK).
21 I/O M P1[6] I2C1 Serial Clock (SCL).[8]
22 I/O M P3[0] I2C1 Serial Data (SDA).[8]
23 I/O M P3[2] I2C1 Serial Clock (SCL).[8]
24 I/O M P3[4]
25 I/O M P3[6]
26 Input XRES Active high external reset with internal pull
down.
27 I/O M P4[0]
28 I/O M P4[2]
29 I/O M P4[4]
30 I/O M P4[6]
31 I/O I, M P2[0] Direct switched capacitor block input.[11]
32 I/O I, M P2[2] Direct switched capacitor block input.[11]
33 I/O M P2[4] External Analog Ground (AGND).
34 I/O M P2[6] External Voltage Reference (VRef).
35 I/O I, M, S P0[0] Analog column mux and SAR ADC input.[6]
36 I/O I/O, M S P0[2] Analog column mux and SAR ADC input.
Analog column output.[6, 9]
37 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input.
Analog column output.[6, 9]
38 I/O I, M, S P0[6] Analog column mux and SAR ADC input.[6]
39 Power Vdd Supply voltage.
40 I/O I, M, S P0[7] Analog column mux and SAR ADC input.[6]
41 I/O I/O, M, S P0[5] Analog column mux and SAR ADC input.
Analog column output.[6, 7]
42 I/O I/O, M, S P0[3] Analog column mux and SAR ADC input.
Analog column output.[6, 7]
43 I/O I, M, S P0[1] Analog column mux and SAR ADC input.[6]
44 I/O P2[7]
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input.

Document Number: 001-48111 Rev. *D Page 12 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

48-Pin Part Pinout

Table 6. 48-Pin Part Pinout (QFN[12])
Pin Type Pin CY8C28623, CY8C28643, and CY8C28645
Description
No. Digital Analog Name 48-Pin PSoC Devices
1 I/O I, M P2[3] Direct switched capacitor block input.[10]

P2[6], M, External VRef

2 I/O I, M P2[1] Direct switched capacitor block input.[10]

P0[3], M, AIO, S
P0[5], M, AIO, S

P0[4], M, AIO, S
P0[2], M, AIO, S
3 I/O M P4[7]

P0[1], M, AI, S

P0[7], M, AI, S

P0[6], M, AI, S

P0[0], M, AI, S
4 I/O M P4[5]

P2[5], M
P2[7], M
5 I/O M P4[3]

Vdd
6 I/O M P4[1]
7 Output SMP Switch Mode Pump (SMP) connection to

48
47
46
45
44
43
42
41
40
39
38
37
external components. AI, M, P2[3] 1 36 P2[4], M, External AGND
AI, M, P2[1] 2 35 P2[2], M, AI
8 I/O M P3[7]
M, P4[7] 3 34 P2[0], M, AI
9 I/O M P3[5] M, P4[5] 4 33 P4[6], M
10 I/O M P3[3] M, P4[3] 5 32 P4[4], M
11 I/O M P3[1] M, P4[1] 6 QFN 31 P4[2], M
12 I/O M P5[3] SMP 7 (Top View) 30 P4[0], M
M, P3[7] 8 29 XRES
13 I/O M P5[1]
M, P3[5] 9 28 P3[6], M
14 I/O M P1[7] I2C0 Serial Clock (SCL). M, P3[3] 10 27 P3[4], M
15 I/O M P1[5] I2C0 Serial Data (SDA). M, P3[1] 11 26 P3[2], M, I2C1 SCL
16 I/O M P1[3] M, P5[3] 12 25 P3[0], M, I2C1 SDA

13
14
15
16
17
18
19
20
21
22
23
24
17 I/O M P1[1] Crystal Input (XTALin), I2C0 Serial Clock
(SCL), ISSP-SCLK[5].

Vss
I2C0 SDA, M, P1[5]

I2C0 SCL, XTALin, M, P1[1]

I2C0 SCL, M, P1[7]

I2C0 SDA, XTALout, M, P1[0]

I2C1 SDA, M, P1[2]
EXTCLK, M, P1[4]
I2C1 SCL, M, P1[6]
M, P5[1]

M, P1[3]

M, P5[0]
M, P5[2]
18 Power Vss Ground connection.
19 I/O M P1[0] Crystal Output (XTALout), I2C0 Serial
Data (SDA), ISSP-SDATA[5].
20 I/O M P1[2] I2C1 Serial Data (SDA).[8]
21 I/O M P1[4] Optional External Clock Input
(EXTCLK).
22 I/O M P1[6] I2C1 Serial Clock (SCL).[8]
23 I/O M P5[0]
24 I/O M P5[2]
25 I/O M P3[0] I2C1 Serial Data (SDA).[8]
26 I/O M P3[2] I2C1 Serial Clock (SCL).[8]
27 I/O M P3[4]
28 I/O M P3[6]
29 Input XRES Active high external reset with internal
pull down.
30 I/O M P4[0]
31 I/O M P4[2] Pin Type Pin
Description
32 I/O M P4[4] No. Digital Analog Name
33 I/O M P4[6] 41 I/O I, M, S P0[6] Analog column mux and SAR ADC
input.[6]
34 I/O I, M P2[0] Direct switched capacitor block input.[11] 42 Power Vdd Supply voltage.
35 I/O I, M P2[2] Direct switched capacitor block input.[11] 43 I/O I, M, S P0[7] Analog column mux and SAR ADC
input.[6]
36 I/O M P2[4] External Analog Ground (AGND). 44 I/O I/O, M, P0[5] Analog column mux and SAR ADC
S input. Analog column output.[6, 7]
37 I/O M P2[6] External Voltage Reference (VRef). 45 I/O I/O, M, P0[3] Analog column mux and SAR ADC
S input. Analog column output.[6, 7]
38 I/O I, M, S P0[0]
Analog column mux and SAR ADC 46 I/O I, M, S P0[1] Analog column mux and SAR ADC
input.[6] input.[6]
39 I/O I/O, M, S P0[2] Analog column mux and SAR ADC input. 47 I/O M P2[7]
Analog column output.[6, 9]
40 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input. 48 I/O M P2[5]
Analog column output.[6, 9]
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input.

Note
12. The QFN package has a center pad that must be connected to ground (Vss)

Document Number: 001-48111 Rev. *D Page 13 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

56-Pin Part Pinout

The 56-pin SSOP part is for the CY8C28000 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.

Table 7. 56-Pin Part Pinout (SSOP)

Pin Type Pin CY8C28000 56-Pin PSoC Device
Description
No. Digital Analog Name
1 NC No connection. NC 1 56 Vdd
S, AI, M, P0[7] 2 55 P0[6], M, AI, S
2 I/O I, M, S P0[7] Analog column mux and SAR ADC input. S, AIO, M, P0[5] 3 54 P0[4], M, AIO, S
3 I/O I/O, M, S P0[5] Analog column mux and SAR ADC input. S, AIO, M, P0[3] 4 53 P0[2], M, AIO, S
Analog column output. S, AI, M, P0[1] 5 52 P0[0], M, AI, S
M, P2[7] 6 51 P2[6], M, External VRef
4 I/O I/O, M, S P0[3] Analog column mux and SAR ADC input. M, P2[5] 7 50 P2[4], M, External AGND
Analog column output. AI, M, P2[3] 8 49 P2[2], M, AI
AI, M, P2[1] 9 48 P2[0], M, AI
5 I/O I, M, S P0[1] Analog column mux and SAR ADC input. M, P4[7] 10 47 P4[6], M
M, P4[5] 11 46 P4[4], M
6 I/O M P2[7] M, P4[3] 12 45 P4[2], M
M, P4[1] 13 44 P4[0], M
7 I/O M P2[5]
OCDE 14 SSOP 43 CCLK
8 I/O I P2[3] Direct switched capacitor block input. OCDO 15 42 HCLK
SMP 16 41 XRES
9 I/O I P2[1] Direct switched capacitor block input. M, P3[7] 17 40 P3[6], M
M, P3[5] 18 39 P3[4], M
10 I/O M P4[7] M, P3[3] P3[2], M, I2C1 SCL
19 38
11 I/O M P4[5] M, P3[1] 20 37 P3[0], M, I2C1 SDA
M, P5[3] 21 36 P5[2], M
12 I/O I, M P4[3] M, P5[1] 22 35 P5[0], M
I2C0 SCL, M, P1[7] 23 34 P1[6], M, I2C1 SCL
13 I/O I, M P4[1] I2C0 SDA, M, P1[5] 24 33 P1[4], M, EXTCLK
14 OCD M OCDE OCD even data I/O. NC 25 32 P1[2], M, I2C1 SDA
M, P1[3] 26 31 P1[0], M, XTALOut, I2C0 SDA, SDATA
15 OCD M OCDO OCD odd data output. SCLK, I2C0 SCL, XTALIn, M, P1[1] 27 30 NC
Vss 28 29 NC
16 Output SMP Switch Mode Pump (SMP) connection to
required external components.
Not for Production
17 I/O M P3[7]
18 I/O M P3[5]
19 I/O M P3[3]
20 I/O M P3[1]
21 I/O M P5[3]
22 I/O M P5[1]
23 I/O M P1[7] I2C0 Serial Clock (SCL).
24 I/O M P1[5] I2C0 Serial Data (SDA).
25 NC No connection.
26 I/O M P1[3]
27 I/O M P1[1] Crystal Input (XTALin), I2C0 Serial Clock
(SCL), ISSP-SCLK[5].
28 Power Vdd Ground connection.
29 NC No connection.
30 NC No connection.
31 I/O M P1[0] Crystal Output (XTALout), I2C0 Serial
Data (SDA), ISSP-SDATA[5].
32 I/O M P1[2] I2C1 Serial Data (SDA).
33 I/O M P1[4] Optional External Clock Input (EXTCLK).
34 I/O M P1[6] I2C1 Serial Clock (SCL).
35 I/O M P5[0]
36 I/O M P5[2]
37 I/O M P3[0] I2C1 Serial Data (SDA).
38 I/O M P3[2] I2C1 Serial Clock (SCL).
39 I/O M P3[4]
40 I/O M P3[6]

Document Number: 001-48111 Rev. *D Page 14 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Table 7. 56-Pin Part Pinout (SSOP) (continued)

Pin Type Pin Description
No. Digital Analog Name
41 Input XRES Active high external reset with internal
pull down.
42 OCD M HCLK OCD high-speed clock output.
43 OCD M CCLK OCD CPU clock output.
44 I/O M P4[0]
45 I/O M P4[2]
46 I/O M P4[4]
47 I/O M P4[6]
48 I/O I, M P2[0] Direct switched capacitor block input.
49 I/O I, M P2[2] Direct switched capacitor block input.
50 I/O M P2[4] External Analog Ground (AGND).
51 I/O M P2[6] External Voltage Reference (VRef).
52 I/O I, M, S P0[0] Analog column mux and SAR ADC input.
53 I/O I/O, M, S P0[2] Analog column mux and SAR ADC input.
Analog column output.
54 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input.
Analog column output.
55 I/O I, M, S P0[6] Analog column mux and SAR ADC input.
56 Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, M = Analog Mux Bus Input, and OCD = On-Chip Debug.

Document Number: 001-48111 Rev. *D Page 15 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Register Reference
This section lists the registers of the CY8C28xxx PSoC devices. For detailed register information, reference the
PSoC Programmable System-on-Chip Technical Reference Manual for CY8C28xxx PSoC devices.

Register Conventions Register Mapping Tables

The register conventions specific to this section are listed in the CY8C28xxx PSoC devices have a total register address space
following table. of 512 bytes. The register space is referred to as I/O space and
is divided into two banks. The XIO bit in the Flag register
(CPU_F) determines which bank of registers CPU instructions
Convention Description access. When the XIO bit is set the registers in Bank 1 are
R Read register or bit(s) accessed by CPU instructions. When the XIO bit is cleared the
W Write register or bit(s) registers in Bank 0 are accessed by CPU instructions.

L Logical register or bit(s) Note In the following register mapping tables, blank fields are
reserved and should not be accessed.
C Clearable register or bit(s)
# Access is bit specific

Document Number: 001-48111 Rev. *D Page 16 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

CY8C28x03 Register Map Bank 0 Table: User Space

Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW DBC20DR0 40 # 80 RDI2RI C0 RW
PRT0IE 01 RW DBC20DR1 41 W 81 RDI2SYN C1 RW
PRT0GS 02 RW DBC20DR2 42 RW 82 RDI2IS C2 RW
PRT0DM2 03 RW DBC20CR0 43 # 83 RDI2LT0 C3 RW
PRT1DR 04 RW DBC21DR0 44 # 84 RDI2LT1 C4 RW
PRT1IE 05 RW DBC21DR1 45 W 85 RDI2RO0 C5 RW
PRT1GS 06 RW DBC21DR2 46 RW 86 RDI2RO1 C6 RW
PRT1DM2 07 RW DBC21CR0 47 # 87 RDI2DSM C7 RW
PRT2DR 08 RW DCC22DR0 48 # 88 C8
PRT2IE 09 RW DCC22DR1 49 W 89 C9
PRT2GS 0A RW DCC22DR2 4A RW 8A CA
PRT2DM2 0B RW DCC22CR0 4B # 8B CB
PRT3DR 0C RW DCC23DR0 4C # 8C CC
PRT3IE 0D RW DCC23DR1 4D W 8D CD
PRT3GS 0E RW DCC23DR2 4E RW 8E CE
PRT3DM2 0F RW DCC23CR0 4F # 8F CF
PRT4DR 10 RW 50 90 CUR_PP D0 RW
PRT4IE 11 RW 51 91 STK_PP D1 RW
PRT4GS 12 RW 52 92 D2
PRT4DM2 13 RW 53 93 IDX_PP D3 RW
PRT5DR 14 RW 54 94 MVR_PP D4 RW
PRT5IE 15 RW 55 95 MVW_PP D5 RW
PRT5GS 16 RW 56 96 I2C0_CFG D6 RW
PRT5DM2 17 RW 57 97 I2C0_SCR D7 #
18 58 98 I2C0_DR D8 RW
19 59 99 I2C0_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C INT_CLR2 DC RW
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK3 DE RW
1F 5F 9F INT_MSK2 DF RW
DBC00DR0 20 # 60 A0 INT_MSK0 E0 RW
DBC00DR1 21 W 61 A1 INT_MSK1 E1 RW
DBC00DR2 22 RW 62 A2 INT_VC E2 RC
DBC00CR0 23 # 63 A3 RES_WDT E3 W
DBC01DR0 24 # 64 A4 I2C1_SCR E4 #
DBC01DR1 25 W 65 A5 I2C1_MSCR E5 #
DBC01DR2 26 RW 66 A6 E6
DBC01CR0 27 # I2C1_DR 67 RW A7 E7
DCC02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W
DCC02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W
DCC02DR2 2A RW SADC_DH 6A RW MUL1_DH AA R MUL0_DH EA R
DCC02CR0 2B # SADC_DL 6B RW MUL1_DL AB R MUL0_DL EB R
DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW
DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW
DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW
DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW
DBC10DR0 30 # 70 RDI0RI B0 RW F0
DBC10DR1 31 W 71 RDI0SYN B1 RW F1
DBC10DR2 32 RW 72 RDI0IS B2 RW F2
DBC10CR0 33 # 73 RDI0LT0 B3 RW F3
DBC11DR0 34 # 74 RDI0LT1 B4 RW F4
DBC11DR1 35 W 75 RDI0RO0 B5 RW F5
DBC11DR2 36 RW 76 RDI0RO1 B6 RW F6
DBC11CR0 37 # 77 RDI0DSM B7 RW CPU_F F7 RL
DCC12DR0 38 # 78 RDI1RI B8 RW F8
DCC12DR1 39 W 79 RDI1SYN B9 RW F9
DCC12DR2 3A RW 7A RDI1IS BA RW FA
DCC12CR0 3B # 7B RDI1LT0 BB RW FB
DCC13DR0 3C # 7C RDI1LT1 BC RW FC
DCC13DR1 3D W 7D RDI1RO0 BD RW FD
DCC13DR2 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR0 3F # 7F RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-48111 Rev. *D Page 17 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

CY8C28x03 Register Map Bank 1 Table: Configuration Space

Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access
PRT0DM0 00 RW DBC20FN 40 RW 80 RDI2RI C0 RW
PRT0DM1 01 RW DBC20IN 41 RW SADC_TSCMPL 81 RW RDI2SYN C1 RW
PRT0IC0 02 RW DBC20OU 42 RW SADC_TSCMPH 82 RW RDI2IS C2 RW
PRT0IC1 03 RW DBC20CR1 43 RW 83 RDI2LT0 C3 RW
PRT1DM0 04 RW DBC21FN 44 RW 84 RDI2LT1 C4 RW
PRT1DM1 05 RW DBC21IN 45 RW 85 RDI2RO0 C5 RW
PRT1IC0 06 RW DBC21OU 46 RW 86 RDI2RO1 C6 RW
PRT1IC1 07 RW DBC21CR1 47 RW 87 RDI2DSM C7 RW
PRT2DM0 08 RW DCC22FN 48 RW 88 C8
PRT2DM1 09 RW DCC22IN 49 RW 89 C9
PRT2IC0 0A RW DCC22OU 4A RW 8A CA
PRT2IC1 0B RW DCC22CR1 4B RW 8B CB
PRT3DM0 0C RW DCC23FN 4C RW 8C CC
PRT3DM1 0D RW DCC23IN 4D RW 8D CD
PRT3IC0 0E RW DCC23OU 4E RW 8E CE
PRT3IC1 0F RW DCC23CR1 4F RW 8F CF
PRT4DM0 10 RW 50 90 GDI_O_IN D0 RW
PRT4DM1 11 RW 51 91 GDI_E_IN D1 RW
PRT4IC0 12 RW 52 92 GDI_O_OU D2 RW
PRT4IC1 13 RW 53 93 GDI_E_OU D3 RW
PRT5DM0 14 RW 54 94 D4
PRT5DM1 15 RW 55 95 D5
PRT5IC0 16 RW 56 96 D6
PRT5IC1 17 RW 57 97 D7
18 58 98 D8
19 59 99 D9
1A 5A 9A DA
1B 5B 9B DB
1C 5C 9C DC
1D 5D 9D OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBC00FN 20 RW 60 GDI_O_IN_CR A0 RW OSC_CR0 E0 RW
DBC00IN 21 RW 61 GDI_E_IN_CR A1 RW OSC_CR1 E1 RW
DBC00OU 22 RW 62 GDI_O_OU_CR A2 RW OSC_CR2 E2 RW
DBC00CR1 23 RW 63 GDI_E_OU_CR A3 RW VLT_CR E3 RW
DBC01FN 24 RW 64 RTC_H A4 RW VLT_CMP E4 RW
DBC01IN 25 RW 65 RTC_M A5 RW E5
DBC01OU 26 RW 66 RTC_S A6 RW E6
DBC01CR1 27 RW 67 RTC_CR A7 RW E7
DCC02FN 28 RW 68 SADC_CR0 A8 RW IMO_TR E8 RW
DCC02IN 29 RW 69 SADC_CR1 A9 RW ILO_TR E9 RW
DCC02OU 2A RW 6A SADC_CR2 AA RW BDG_TR EA RW
DCC02CR1 2B RW I2C1_CFG 6B RW SADC_CR3 AB RW ECO_TR EB RW
DCC03FN 2C RW TMP_DR0 6C RW SADC_CR4 AC RW EC
DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW ED
DCC03OU 2E RW TMP_DR2 6E RW I2C1_ADDR AE RW EE
DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF
DBC10FN 30 RW 70 RDI0RI B0 RW F0
DBC10IN 31 RW SADC_TSCR0 71 RW RDI0SYN B1 RW F1
DBC10OU 32 RW SADC_TSCR1 72 RW RDI0IS B2 RW F2
DBC10CR1 33 RW 73 RDI0LT0 B3 RW F3
DBC11FN 34 RW 74 RDI0LT1 B4 RW F4
DBC11IN 35 RW 75 RDI0RO0 B5 RW F5
DBC11OU 36 RW 76 RDI0RO1 B6 RW F6
DBC11CR1 37 RW 77 RDIODSM B7 RW CPU_F F7 RL
DCC12FN 38 RW 78 RDI1RI B8 RW F8
DCC12IN 39 RW 79 RDI1SYN B9 RW F9
DCC12OU 3A RW 7A RDI1IS BA RW FLS_PR1 FA RW
DCC12CR1 3B RW 7B RDI1LT0 BB RW FB
DCC13FN 3C RW 7C RDI1LT1 BC RW FC
DCC13IN 3D RW 7D RDI1RO0 BD RW FD
DCC13OU 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR1 3F RW 7F RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-48111 Rev. *D Page 18 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

CY8C28x13 Register Map Bank 0 Table: User Space

Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW DBC20DR0 40 # 80 RDI2RI C0 RW
PRT0IE 01 RW DBC20DR1 41 W 81 RDI2SYN C1 RW
PRT0GS 02 RW DBC20DR2 42 RW 82 RDI2IS C2 RW
PRT0DM2 03 RW DBC20CR0 43 # 83 RDI2LT0 C3 RW
PRT1DR 04 RW DBC21DR0 44 # 84 RDI2LT1 C4 RW
PRT1IE 05 RW DBC21DR1 45 W 85 RDI2RO0 C5 RW
PRT1GS 06 RW DBC21DR2 46 RW 86 RDI2RO1 C6 RW
PRT1DM2 07 RW DBC21CR0 47 # 87 RDI2DSM C7 RW
PRT2DR 08 RW DCC22DR0 48 # 88 C8
PRT2IE 09 RW DCC22DR1 49 W 89 C9
PRT2GS 0A RW DCC22DR2 4A RW 8A CA
PRT2DM2 0B RW DCC22CR0 4B # 8B CB
PRT3DR 0C RW DCC23DR0 4C # 8C CC
PRT3IE 0D RW DCC23DR1 4D W 8D CD
PRT3GS 0E RW DCC23DR2 4E RW 8E CE
PRT3DM2 0F RW DCC23CR0 4F # 8F CF
PRT4DR 10 RW 50 90 CUR_PP D0 RW
PRT4IE 11 RW 51 91 STK_PP D1 RW
PRT4GS 12 RW 52 92 D2
PRT4DM2 13 RW 53 93 IDX_PP D3 RW
PRT5DR 14 RW 54 94 MVR_PP D4 RW
PRT5IE 15 RW 55 95 MVW_PP D5 RW
PRT5GS 16 RW 56 96 I2C0_CFG D6 RW
PRT5DM2 17 RW 57 97 I2C0_SCR D7 #
18 58 98 I2C0_DR D8 RW
19 59 99 I2C0_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C INT_CLR2 DC RW
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK3 DE RW
1F 5F 9F INT_MSK2 DF RW
DBC00DR0 20 # 60 DEC0_DH A0 RC INT_MSK0 E0 RW
DBC00DR1 21 W AMUX_CFG 61 RW DEC0_DL A1 RC INT_MSK1 E1 RW
DBC00DR2 22 RW 62 DEC1_DH A2 RC INT_VC E2 RC
DBC00CR0 23 # 63 DEC1_DL A3 RC RES_WDT E3 W
DBC01DR0 24 # 64 A4 E4
DBC01DR1 25 W 65 A5 E5
DBC01DR2 26 RW 66 A6 DEC_CR0* E6 RW
DBC01CR0 27 # 67 A7 DEC_CR1* E7 RW
DCC02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W
DCC02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W
DCC02DR2 2A RW SADC_DH 6A RW MUL1_DH AA R MUL0_DH EA R
DCC02CR0 2B # SADC_DL 6B RW MUL1_DL AB R MUL0_DL EB R
DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW
DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW
DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW
DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW
DBC10DR0 30 # 70 RDI0RI B0 RW F0
DBC10DR1 31 W 71 RDI0SYN B1 RW F1
DBC10DR2 32 RW 72 RDI0IS B2 RW F2
DBC10CR0 33 # 73 RDI0LT0 B3 RW F3
DBC11DR0 34 # 74 RDI0LT1 B4 RW F4
DBC11DR1 35 W 75 RDI0RO0 B5 RW F5
DBC11DR2 36 RW 76 RDI0RO1 B6 RW F6
DBC11CR0 37 # 77 RDI0DSM B7 RW CPU_F F7 RL
DCC12DR0 38 # 78 RDI1RI B8 RW F8
DCC12DR1 39 W 79 RDI1SYN B9 RW F9
DCC12DR2 3A RW 7A RDI1IS BA RW FA
DCC12CR0 3B # 7B RDI1LT0 BB RW FB
DCC13DR0 3C # 7C RDI1LT1 BC RW DAC1_D FC RW
DCC13DR1 3D W 7D RDI1RO0 BD RW DAC0_D FD RW
DCC13DR2 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR0 3F # 7F RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-48111 Rev. *D Page 19 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

CY8C28x13 Register Map Bank 1 Table: Configuration Space

Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access
PRT0DM0 00 RW DBC20FN 40 RW 80 RDI2RI C0 RW
PRT0DM1 01 RW DBC20IN 41 RW SADC_TSCMPL 81 RW RDI2SYN C1 RW
PRT0IC0 02 RW DBC20OU 42 RW SADC_TSCMPH 82 RW RDI2IS C2 RW
PRT0IC1 03 RW DBC20CR1 43 RW ACE_AMD_CR1 83 RW RDI2LT0 C3 RW
PRT1DM0 04 RW DBC21FN 44 RW 84 RDI2LT1 C4 RW
PRT1DM1 05 RW DBC21IN 45 RW ACE_PWM_CR 85 RW RDI2RO0 C5 RW
PRT1IC0 06 RW DBC21OU 46 RW ACE_ADC0_CR 86 RW RDI2RO1 C6 RW
PRT1IC1 07 RW DBC21CR1 47 RW ACE_ADC1_CR 87 RW RDI2DSM C7 RW
PRT2DM0 08 RW DCC22FN 48 RW 88 C8
PRT2DM1 09 RW DCC22IN 49 RW ACE_CLK_CR0 89 RW C9
PRT2IC0 0A RW DCC22OU 4A RW ACE_CLK_CR1 8A RW CA
PRT2IC1 0B RW DCC22CR1 4B RW ACE_CLK_CR3 8B RW CB
PRT3DM0 0C RW DCC23FN 4C RW 8C RW CC
PRT3DM1 0D RW DCC23IN 4D RW ACE01CR1 8D RW CD
PRT3IC0 0E RW DCC23OU 4E RW ACE01CR2 8E RW CE
PRT3IC1 0F RW DCC23CR1 4F RW ASE11CR0 8F RW CF
PRT4DM0 10 RW 50 90 GDI_O_IN D0 RW
PRT4DM1 11 RW 51 DEC0_CR0 91 RW GDI_E_IN D1 RW
PRT4IC0 12 RW 52 DEC_CR3 92 RW GDI_O_OU D2 RW
PRT4IC1 13 RW 53 93 GDI_E_OU D3 RW
PRT5DM0 14 RW 54 94 DEC0_CR D4 RW
PRT5DM1 15 RW 55 DEC1_CR0 95 RW DEC1_CR D5 RW
PRT5IC0 16 RW 56 96 D6
PRT5IC1 17 RW 57 97 D7
18 58 98 MUX_CR0 D8 RW
19 59 99 MUX_CR1 D9 RW
1A 5A DEC_CR5 9A RW MUX_CR2 DA RW
1B 5B 9B MUX_CR3 DB RW
1C 5C 9C IDAC_CR1 DC RW
1D 5D 9D OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBC00FN 20 RW 60 GDI_O_IN_CR A0 RW OSC_CR0 E0 RW
DBC00IN 21 RW 61 GDI_E_IN_CR A1 RW OSC_CR1 E1 RW
DBC00OU 22 RW 62 GDI_O_OU_CR A2 RW OSC_CR2 E2 RW
DBC00CR1 23 RW 63 GDI_E_OU_CR A3 RW VLT_CR E3 RW
DBC01FN 24 RW 64 RTC_H A4 RW VLT_CMP E4 RW
DBC01IN 25 RW 65 RTC_M A5 RW ADC0_TR E5 RW
DBC01OU 26 RW 66 RTC_S A6 RW ADC1_TR E6 RW
DBC01CR1 27 RW 67 RTC_CR A7 RW IDAC_CR2 E7 RW
DCC02FN 28 RW 68 SADC_CR0 A8 RW IMO_TR E8 RW
DCC02IN 29 RW 69 SADC_CR1 A9 RW ILO_TR E9 RW
DCC02OU 2A RW AMUX_CFG1 6A RW SADC_CR2 AA RW BDG_TR EA RW
DCC02CR1 2B RW 6B SADC_CR3 AB RW ECO_TR EB RW
DCC03FN 2C RW TMP_DR0 6C RW SADC_CR4 AC RW MUX_CR4 EC RW
DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW MUX_CR5 ED RW
DCC03OU 2E RW TMP_DR2 6E RW AE EE
DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF
DBC10FN 30 RW 70 RDI0RI B0 RW F0
DBC10IN 31 RW SADC_TSCR0 71 RW RDI0SYN B1 RW F1
DBC10OU 32 RW SADC_TSCR1 72 RW RDI0IS B2 RW F2
DBC10CR1 33 RW ACE_AMD_CR0 73 RW RDI0LT0 B3 RW F3
DBC11FN 34 RW 74 RW RDI0LT1 B4 RW F4
DBC11IN 35 RW ACE_AMX_IN 75 RW RDI0RO0 B5 RW F5
DBC11OU 36 RW ACE_CMP_CR0 76 RW RDI0RO1 B6 RW F6
DBC11CR1 37 RW ACE_CMP_CR1 77 RW RDIODSM B7 RW CPU_F F7 RL
DCC12FN 38 RW 78 RDI1RI B8 RW F8
DCC12IN 39 RW ACE_CMP_GI_EN 79 RW RDI1SYN B9 RW F9
DCC12OU 3A RW ACE_ALT_CR0 7A RW RDI1IS BA RW FLS_PR1 FA RW
DCC12CR1 3B RW ACE_ABF_CR0 7B RW RDI1LT0 BB RW FB
DCC13FN 3C RW 7C RDI1LT1 BC RW FC
DCC13IN 3D RW ACE0_CR1 7D RW RDI1RO0 BD RW IDAC_CR0 FD RW
DCC13OU 3E RW ACE0_CR2 7E RW RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR1 3F RW ACE0_CR3 7F RW RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-48111 Rev. *D Page 20 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

CY8C28x23 Register Map Bank 0 Table: User Space

Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW DBC20DR0 40 # ASC10CR0 80 RW RDI2RI C0 RW
PRT0IE 01 RW DBC20DR1 41 W ASC10CR1 81 RW RDI2SYN C1 RW
PRT0GS 02 RW DBC20DR2 42 RW ASC10CR2 82 RW RDI2IS C2 RW
PRT0DM2 03 RW DBC20CR0 43 # ASC10CR3 83 RW RDI2LT0 C3 RW
PRT1DR 04 RW DBC21DR0 44 # ASD11CR0 84 RW RDI2LT1 C4 RW
PRT1IE 05 RW DBC21DR1 45 W ASD11CR1 85 RW RDI2RO0 C5 RW
PRT1GS 06 RW DBC21DR2 46 RW ASD11CR2 86 RW RDI2RO1 C6 RW
PRT1DM2 07 RW DBC21CR0 47 # ASD11CR3 87 RW RDI2DSM C7 RW
PRT2DR 08 RW DCC22DR0 48 # 88 C8
PRT2IE 09 RW DCC22DR1 49 W 89 C9
PRT2GS 0A RW DCC22DR2 4A RW 8A CA
PRT2DM2 0B RW DCC22CR0 4B # 8B CB
PRT3DR 0C RW DCC23DR0 4C # 8C CC
PRT3IE 0D RW DCC23DR1 4D W 8D CD
PRT3GS 0E RW DCC23DR2 4E RW 8E CE
PRT3DM2 0F RW DCC23CR0 4F # 8F CF
PRT4DR 10 RW 50 ASD20CR0 90 RW CUR_PP D0 RW
PRT4IE 11 RW 51 ASD20CR1 91 RW STK_PP D1 RW
PRT4GS 12 RW 52 ASD20CR2 92 RW D2
PRT4DM2 13 RW 53 ASD20CR3 93 RW IDX_PP D3 RW
PRT5DR 14 RW 54 ASC21CR0 94 RW MVR_PP D4 RW
PRT5IE 15 RW 55 ASC21CR1 95 RW MVW_PP D5 RW
PRT5GS 16 RW 56 ASC21CR2 96 RW I2C0_CFG D6 RW
PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C0_SCR D7 #
18 58 98 I2C0_DR D8 RW
19 59 99 I2C0_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C INT_CLR2 DC RW
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK3 DE RW
1F 5F 9F INT_MSK2 DF RW
DBC00DR0 20 # AMX_IN 60 RW DEC0_DH A0 RC INT_MSK0 E0 RW
DBC00DR1 21 W AMUX_CFG 61 RW DEC0_DL A1 RC INT_MSK1 E1 RW
DBC00DR2 22 RW CLK_CR3 62 RW DEC1_DH A2 RC INT_VC E2 RC
DBC00CR0 23 # ARF_CR 63 RW DEC1_DL A3 RC RES_WDT E3 W
DBC01DR0 24 # CMP_CR0 64 # A4 I2C1_SCR E4 #
DBC01DR1 25 W ASY_CR 65 # A5 I2C1_MSCR E5 #
DBC01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0* E6 RW
DBC01CR0 27 # I2C1_DR 67 RW A7 DEC_CR1* E7 RW
DCC02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W
DCC02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W
DCC02DR2 2A RW 6A MUL1_DH AA R MUL0_DH EA R
DCC02CR0 2B # 6B MUL1_DL AB R MUL0_DL EB R
DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW
DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW
DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW
DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW
DBC10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0
DBC10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1
DBC10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2
DBC10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3
DBC11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4
DBC11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5
DBC11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6
DBC11CR0 37 # ACB01CR2 77 RW RDI0DSM B7 RW CPU_F F7 RL
DCC12DR0 38 # 78 RDI1RI B8 RW F8
DCC12DR1 39 W 79 RDI1SYN B9 RW F9
DCC12DR2 3A RW 7A RDI1IS BA RW FA
DCC12CR0 3B # 7B RDI1LT0 BB RW FB
DCC13DR0 3C # 7C RDI1LT1 BC RW FC
DCC13DR1 3D W 7D RDI1RO0 BD RW FD
DCC13DR2 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR0 3F # 7F RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-48111 Rev. *D Page 21 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

CY8C28x23 Register Map Bank 1 Table: Configuration Space

Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access
PRT0DM0 00 RW DBC20FN 40 RW 80 RDI2RI C0 RW
PRT0DM1 01 RW DBC20IN 41 RW 81 RDI2SYN C1 RW
PRT0IC0 02 RW DBC20OU 42 RW 82 RDI2IS C2 RW
PRT0IC1 03 RW DBC20CR1 43 RW 83 RDI2LT0 C3 RW
PRT1DM0 04 RW DBC21FN 44 RW 84 RDI2LT1 C4 RW
PRT1DM1 05 RW DBC21IN 45 RW 85 RDI2RO0 C5 RW
PRT1IC0 06 RW DBC21OU 46 RW 86 RDI2RO1 C6 RW
PRT1IC1 07 RW DBC21CR1 47 RW 87 RDI2DSM C7 RW
PRT2DM0 08 RW DCC22FN 48 RW 88 C8
PRT2DM1 09 RW DCC22IN 49 RW 89 C9
PRT2IC0 0A RW DCC22OU 4A RW 8A CA
PRT2IC1 0B RW DCC22CR1 4B RW 8B CB
PRT3DM0 0C RW DCC23FN 4C RW 8C CC
PRT3DM1 0D RW DCC23IN 4D RW 8D CD
PRT3IC0 0E RW DCC23OU 4E RW 8E CE
PRT3IC1 0F RW DCC23CR1 4F RW 8F CF
PRT4DM0 10 RW 50 90 GDI_O_IN D0 RW
PRT4DM1 11 RW 51 DEC0_CR0 91 RW GDI_E_IN D1 RW
PRT4IC0 12 RW 52 DEC_CR3 92 RW GDI_O_OU D2 RW
PRT4IC1 13 RW 53 93 RW GDI_E_OU D3 RW
PRT5DM0 14 RW 54 94 RW DEC0_CR D4 RW
PRT5DM1 15 RW 55 DEC1_CR0 95 RW DEC1_CR D5 RW
PRT5IC0 16 RW 56 96 D6
PRT5IC1 17 RW 57 97 D7
18 58 98 D8
19 59 99 D9
1A 5A DEC_CR5 9A RW DA
1B 5B 9B DB
1C 5C 9C DC
1D 5D 9D OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBC00FN 20 RW CLK_CR0 60 RW GDI_O_IN_CR A0 RW OSC_CR0 E0 RW
DBC00IN 21 RW CLK_CR1 61 RW GDI_E_IN_CR A1 RW OSC_CR1 E1 RW
DBC00OU 22 RW ABF_CR0 62 RW GDI_O_OU_CR A2 RW OSC_CR2 E2 RW
DBC00CR1 23 RW AMD_CR0 63 RW GDI_E_OU_CR A3 RW VLT_CR E3 RW
DBC01FN 24 RW CMP_GO_EN 64 RW RTC_H A4 RW VLT_CMP E4 RW
DBC01IN 25 RW 65 RTC_M A5 RW E5
DBC01OU 26 RW AMD_CR1 66 RW RTC_S A6 RW E6
DBC01CR1 27 RW ALT_CR0 67 RW RTC_CR A7 RW E7
DCC02FN 28 RW 68 A8 IMO_TR E8 RW
DCC02IN 29 RW CLK_CR2 69 RW A9 ILO_TR E9 RW
DCC02OU 2A RW 6A AA BDG_TR EA RW
DCC02CR1 2B RW I2C1_CFG 6B RW AB ECO_TR EB RW
DCC03FN 2C RW TMP_DR0 6C RW AC EC
DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW ED
DCC03OU 2E RW TMP_DR2 6E RW I2C1_ADDR AE RW EE
DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF
DBC10FN 30 RW 70 RDI0RI B0 RW F0
DBC10IN 31 RW 71 RDI0SYN B1 RW F1
DBC10OU 32 RW 72 RDI0IS B2 RW F2
DBC10CR1 33 RW 73 RDI0LT0 B3 RW F3
DBC11FN 34 RW 74 RDI0LT1 B4 RW F4
DBC11IN 35 RW 75 RDI0RO0 B5 RW F5
DBC11OU 36 RW 76 RDI0RO1 B6 RW F6
DBC11CR1 37 RW 77 RDIODSM B7 RW CPU_F F7 RL
DCC12FN 38 RW 78 RDI1RI B8 RW F8
DCC12IN 39 RW 79 RDI1SYN B9 RW F9
DCC12OU 3A RW 7A RDI1IS BA RW FLS_PR1 FA RW
DCC12CR1 3B RW 7B RDI1LT0 BB RW FB
DCC13FN 3C RW 7C RDI1LT1 BC RW FC
DCC13IN 3D RW 7D RDI1RO0 BD RW FD
DCC13OU 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR1 3F RW 7F RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-48111 Rev. *D Page 22 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

CY8C28x33 Register Map Bank 0 Table: User Space

Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW DBC20DR0 40 # ASC10CR0 80 RW RDI2RI C0 RW
PRT0IE 01 RW DBC20DR1 41 W ASC10CR1 81 RW RDI2SYN C1 RW
PRT0GS 02 RW DBC20DR2 42 RW ASC10CR2 82 RW RDI2IS C2 RW
PRT0DM2 03 RW DBC20CR0 43 # ASC10CR3 83 RW RDI2LT0 C3 RW
PRT1DR 04 RW DBC21DR0 44 # ASD11CR0 84 RW RDI2LT1 C4 RW
PRT1IE 05 RW DBC21DR1 45 W ASD11CR1 85 RW RDI2RO0 C5 RW
PRT1GS 06 RW DBC21DR2 46 RW ASD11CR2 86 RW RDI2RO1 C6 RW
PRT1DM2 07 RW DBC21CR0 47 # ASD11CR3 87 RW RDI2DSM C7 RW
PRT2DR 08 RW DCC22DR0 48 # 88 C8
PRT2IE 09 RW DCC22DR1 49 W 89 C9
PRT2GS 0A RW DCC22DR2 4A RW 8A CA
PRT2DM2 0B RW DCC22CR0 4B # 8B CB
PRT3DR 0C RW DCC23DR0 4C # 8C CC
PRT3IE 0D RW DCC23DR1 4D W 8D CD
PRT3GS 0E RW DCC23DR2 4E RW 8E CE
PRT3DM2 0F RW DCC23CR0 4F # 8F CF
PRT4DR 10 RW 50 ASD20CR0 90 RW CUR_PP D0 RW
PRT4IE 11 RW 51 ASD20CR1 91 RW STK_PP D1 RW
PRT4GS 12 RW 52 ASD20CR2 92 RW D2
PRT4DM2 13 RW 53 ASD20CR3 93 RW IDX_PP D3 RW
PRT5DR 14 RW 54 ASC21CR0 94 RW MVR_PP D4 RW
PRT5IE 15 RW 55 ASC21CR1 95 RW MVW_PP D5 RW
PRT5GS 16 RW 56 ASC21CR2 96 RW I2C0_CFG D6 RW
PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C0_SCR D7 #
18 58 98 I2C0_DR D8 RW
19 59 99 I2C0_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C INT_CLR2 DC RW
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK3 DE RW
1F 5F 9F INT_MSK2 DF RW
DBC00DR0 20 # AMX_IN 60 RW DEC0_DH A0 RC INT_MSK0 E0 RW
DBC00DR1 21 W AMUX_CFG 61 RW DEC0_DL A1 RC INT_MSK1 E1 RW
DBC00DR2 22 RW CLK_CR3 62 RW DEC1_DH A2 RC INT_VC E2 RC
DBC00CR0 23 # ARF_CR 63 RW DEC1_DL A3 RC RES_WDT E3 W
DBC01DR0 24 # CMP_CR0 64 # DEC2_DH A4 RC E4
DBC01DR1 25 W ASY_CR 65 # DEC2_DL A5 RC E5
DBC01DR2 26 RW CMP_CR1 66 RW DEC3_DH A6 RC DEC_CR0* E6 RW
DBC01CR0 27 # 67 DEC3_DL A7 RC DEC_CR1* E7 RW
DCC02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W
DCC02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W
DCC02DR2 2A RW SADC_DH 6A RW MUL1_DH AA R MUL0_DH EA R
DCC02CR0 2B # SADC_DL 6B RW MUL1_DL AB R MUL0_DL EB R
DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW
DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW
DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW
DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW
DBC10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0
DBC10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1
DBC10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2
DBC10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3
DBC11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4
DBC11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5
DBC11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6
DBC11CR0 37 # ACB01CR2 77 RW RDI0DSM B7 RW CPU_F F7 RL
DCC12DR0 38 # 78 RDI1RI B8 RW F8
DCC12DR1 39 W 79 RDI1SYN B9 RW F9
DCC12DR2 3A RW 7A RDI1IS BA RW FA
DCC12CR0 3B # 7B RDI1LT0 BB RW FB
DCC13DR0 3C # 7C RDI1LT1 BC RW DAC1_D FC RW
DCC13DR1 3D W 7D RDI1RO0 BD RW DAC0_D FD RW
DCC13DR2 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR0 3F # 7F RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-48111 Rev. *D Page 23 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

CY8C28x33 Register Map Bank 1 Table: Configuration Space

Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access
PRT0DM0 00 RW DBC20FN 40 RW 80 RDI2RI C0 RW
PRT0DM1 01 RW DBC20IN 41 RW SADC_TSCMPL 81 RW RDI2SYN C1 RW
PRT0IC0 02 RW DBC20OU 42 RW SADC_TSCMPH 82 RW RDI2IS C2 RW
PRT0IC1 03 RW DBC20CR1 43 RW ACE_AMD_CR1 83 RW RDI2LT0 C3 RW
PRT1DM0 04 RW DBC21FN 44 RW 84 RDI2LT1 C4 RW
PRT1DM1 05 RW DBC21IN 45 RW ACE_PWM_CR 85 RW RDI2RO0 C5 RW
PRT1IC0 06 RW DBC21OU 46 RW ACE_ADC0_CR 86 RW RDI2RO1 C6 RW
PRT1IC1 07 RW DBC21CR1 47 RW ACE_ADC1_CR 87 RW RDI2DSM C7 RW
PRT2DM0 08 RW DCC22FN 48 RW 88 RW C8
PRT2DM1 09 RW DCC22IN 49 RW ACE_CLK_CR0 89 RW C9
PRT2IC0 0A RW DCC22OU 4A RW ACE_CLK_CR1 8A RW CA
PRT2IC1 0B RW DCC22CR1 4B RW ACE_CLK_CR3 8B RW CB
PRT3DM0 0C RW DCC23FN 4C RW 8C CC
PRT3DM1 0D RW DCC23IN 4D RW ACE01CR1 8D RW CD
PRT3IC0 0E RW DCC23OU 4E RW ACE01CR2 8E RW CE
PRT3IC1 0F RW DCC23CR1 4F RW ASE11CR0 8F RW CF
PRT4DM0 10 RW 50 90 GDI_O_IN D0 RW
PRT4DM1 11 RW 51 DEC0_CR0 91 RW GDI_E_IN D1 RW
PRT4IC0 12 RW 52 DEC_CR3 92 RW GDI_O_OU D2 RW
PRT4IC1 13 RW 53 93 GDI_E_OU D3 RW
PRT5DM0 14 RW 54 94 DEC0_CR D4 RW
PRT5DM1 15 RW 55 DEC1_CR0 95 RW DEC1_CR D5 RW
PRT5IC0 16 RW 56 DEC_CR4 96 RW DEC2_CR D6 RW
PRT5IC1 17 RW 57 97 DEC3_CR D7 RW
18 58 98 MUX_CR0 D8 RW
19 59 DEC2_CR0 99 RW MUX_CR1 D9 RW
1A 5A DEC_CR5 9A RW MUX_CR2 DA RW
1B 5B 9B MUX_CR3 DB RW
1C 5C 9C IDAC_CR1 DC RW
1D 5D DEC3_CR0 9D RW OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBC00FN 20 RW CLK_CR0 60 RW GDI_O_IN_CR A0 RW OSC_CR0 E0 RW
DBC00IN 21 RW CLK_CR1 61 RW GDI_E_IN_CR A1 RW OSC_CR1 E1 RW
DBC00OU 22 RW ABF_CR0 62 RW GDI_O_OU_CR A2 RW OSC_CR2 E2 RW
DBC00CR1 23 RW AMD_CR0 63 RW GDI_E_OU_CR A3 RW VLT_CR E3 RW
DBC01FN 24 RW CMP_GO_EN 64 RW RTC_H A4 RW VLT_CMP E4 RW
DBC01IN 25 RW 65 RTC_M A5 RW ADC0_TR E5 RW
DBC01OU 26 RW AMD_CR1 66 RW RTC_S A6 RW ADC1_TR E6 RW
DBC01CR1 27 RW ALT_CR0 67 RW RTC_CR A7 RW IDAC_CR2 E7 RW
DCC02FN 28 RW 68 SADC_CR0 A8 RW IMO_TR E8 RW
DCC02IN 29 RW CLK_CR2 69 RW SADC_CR1 A9 RW ILO_TR E9 RW
DCC02OU 2A RW AMUX_CFG1 6A RW SADC_CR2 AA RW BDG_TR EA RW
DCC02CR1 2B RW 6B SADC_CR3 AB RW ECO_TR EB RW
DCC03FN 2C RW TMP_DR0 6C RW SADC_CR4 AC RW MUX_CR4 EC RW
DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW MUX_CR5 ED RW
DCC03OU 2E RW TMP_DR2 6E RW AE EE
DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF
DBC10FN 30 RW 70 RDI0RI B0 RW F0
DBC10IN 31 RW SADC_TSCR0 71 RW RDI0SYN B1 RW F1
DBC10OU 32 RW SADC_TSCR1 72 RW RDI0IS B2 RW F2
DBC10CR1 33 RW ACE_AMD_CR0 73 RW RDI0LT0 B3 RW F3
DBC11FN 34 RW 74 RDI0LT1 B4 RW F4
DBC11IN 35 RW ACE_AMX_IN 75 RW RDI0RO0 B5 RW F5
DBC11OU 36 RW ACE_CMP_CR0 76 RW RDI0RO1 B6 RW F6
DBC11CR1 37 RW ACE_CMP_CR1 77 RW RDIODSM B7 RW CPU_F F7 RL
DCC12FN 38 RW 78 RDI1RI B8 RW F8
DCC12IN 39 RW ACE_CMP_GI_EN 79 RW RDI1SYN B9 RW F9
DCC12OU 3A RW ACE_ALT_CR0 7A RW RDI1IS BA RW FLS_PR1 FA RW
DCC12CR1 3B RW ACE_ABF_CR0 7B RW RDI1LT0 BB RW FB
DCC13FN 3C RW 7C RDI1LT1 BC RW FC
DCC13IN 3D RW ACE0_CR1 7D RW RDI1RO0 BD RW IDAC_CR0 FD RW
DCC13OU 3E RW ACE0_CR2 7E RW RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR1 3F RW ACE0_CR3 7F RW RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-48111 Rev. *D Page 24 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

CY8C28x43 Register Map Bank 0 Table: User Space

Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW DBC20DR0 40 # ASC10CR0 80 RW RDI2RI C0 RW
PRT0IE 01 RW DBC20DR1 41 W ASC10CR1 81 RW RDI2SYN C1 RW
PRT0GS 02 RW DBC20DR2 42 RW ASC10CR2 82 RW RDI2IS C2 RW
PRT0DM2 03 RW DBC20CR0 43 # ASC10CR3 83 RW RDI2LT0 C3 RW
PRT1DR 04 RW DBC21DR0 44 # ASD11CR0 84 RW RDI2LT1 C4 RW
PRT1IE 05 RW DBC21DR1 45 W ASD11CR1 85 RW RDI2RO0 C5 RW
PRT1GS 06 RW DBC21DR2 46 RW ASD11CR2 86 RW RDI2RO1 C6 RW
PRT1DM2 07 RW DBC21CR0 47 # ASD11CR3 87 RW RDI2DSM C7 RW
PRT2DR 08 RW DCC22DR0 48 # ASC12CR0 88 RW C8
PRT2IE 09 RW DCC22DR1 49 W ASC12CR1 89 RW C9
PRT2GS 0A RW DCC22DR2 4A RW ASC12CR2 8A RW CA
PRT2DM2 0B RW DCC22CR0 4B # ASC12CR3 8B RW CB
PRT3DR 0C RW DCC23DR0 4C # ASD13CR0 8C RW CC
PRT3IE 0D RW DCC23DR1 4D W ASD13CR1 8D RW CD
PRT3GS 0E RW DCC23DR2 4E RW ASD13CR2 8E RW CE
PRT3DM2 0F RW DCC23CR0 4F # ASD13CR3 8F RW CF
PRT4DR 10 RW 50 ASD20CR0 90 RW CUR_PP D0 RW
PRT4IE 11 RW 51 ASD20CR1 91 RW STK_PP D1 RW
PRT4GS 12 RW 52 ASD20CR2 92 RW D2
PRT4DM2 13 RW 53 ASD20CR3 93 RW IDX_PP D3 RW
PRT5DR 14 RW 54 ASC21CR0 94 RW MVR_PP D4 RW
PRT5IE 15 RW 55 ASC21CR1 95 RW MVW_PP D5 RW
PRT5GS 16 RW 56 ASC21CR2 96 RW I2C0_CFG D6 RW
PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C0_SCR D7 #
18 58 ASD22CR0 98 RW I2C0_DR D8 RW
19 59 ASD22CR1 99 RW I2C0_MSCR D9 #
1A 5A ASD22CR2 9A RW INT_CLR0 DA RW
1B 5B ASD22CR3 9B RW INT_CLR1 DB RW
1C 5C ASC23CR0 9C RW INT_CLR2 DC RW
1D 5D ASC23CR1 9D RW INT_CLR3 DD RW
1E 5E ASC23CR2 9E RW INT_MSK3 DE RW
1F 5F ASC23CR3 9F RW INT_MSK2 DF RW
DBC00DR0 20 # AMX_IN 60 RW DEC0_DH A0 RC INT_MSK0 E0 RW
DBC00DR1 21 W AMUX_CFG 61 RW DEC0_DL A1 RC INT_MSK1 E1 RW
DBC00DR2 22 RW CLK_CR3 62 RW DEC1_DH A2 RC INT_VC E2 RC
DBC00CR0 23 # ARF_CR 63 RW DEC1_DL A3 RC RES_WDT E3 W
DBC01DR0 24 # CMP_CR0 64 # DEC2_DH A4 RC I2C1_SCR E4 #
DBC01DR1 25 W ASY_CR 65 # DEC2_DL A5 RC I2C1_MSCR E5 #
DBC01DR2 26 RW CMP_CR1 66 RW DEC3_DH A6 RC DEC_CR0* E6 RW
DBC01CR0 27 # I2C1_DR 67 RW DEC3_DL A7 RC DEC_CR1* E7 RW
DCC02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W
DCC02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W
DCC02DR2 2A RW SADC_DH 6A RW MUL1_DH AA R MUL0_DH EA R
DCC02CR0 2B # SADC_DL 6B RW MUL1_DL AB R MUL0_DL EB R
DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW
DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW
DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW
DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW
DBC10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0
DBC10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1
DBC10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2
DBC10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3
DBC11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4
DBC11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5
DBC11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6
DBC11CR0 37 # ACB01CR2 77 RW RDI0DSM B7 RW CPU_F F7 RL
DCC12DR0 38 # ACB02CR3 78 RW RDI1RI B8 RW F8
DCC12DR1 39 W ACB02CR0 79 RW RDI1SYN B9 RW F9
DCC12DR2 3A RW ACB02CR1 7A RW RDI1IS BA RW FA
DCC12CR0 3B # ACB02CR2 7B RW RDI1LT0 BB RW FB
DCC13DR0 3C # ACB03CR3 7C RW RDI1LT1 BC RW FC
DCC13DR1 3D W ACB03CR0 7D RW RDI1RO0 BD RW FD
DCC13DR2 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR0 3F # ACB03CR2 7F RW RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-48111 Rev. *D Page 25 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

CY8C28x43 Register Map Bank 1 Table: Configuration Space

Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access
PRT0DM0 00 RW DBC20FN 40 RW 80 RDI2RI C0 RW
PRT0DM1 01 RW DBC20IN 41 RW SADC_TSCMPL 81 RW RDI2SYN C1 RW
PRT0IC0 02 RW DBC20OU 42 RW SADC_TSCMPH 82 RW RDI2IS C2 RW
PRT0IC1 03 RW DBC20CR1 43 RW 83 RDI2LT0 C3 RW
PRT1DM0 04 RW DBC21FN 44 RW 84 RDI2LT1 C4 RW
PRT1DM1 05 RW DBC21IN 45 RW 85 RDI2RO0 C5 RW
PRT1IC0 06 RW DBC21OU 46 RW 86 RDI2RO1 C6 RW
PRT1IC1 07 RW DBC21CR1 47 RW 87 RDI2DSM C7 RW
PRT2DM0 08 RW DCC22FN 48 RW 88 C8
PRT2DM1 09 RW DCC22IN 49 RW 89 C9
PRT2IC0 0A RW DCC22OU 4A RW 8A CA
PRT2IC1 0B RW DCC22CR1 4B RW 8B CB
PRT3DM0 0C RW DCC23FN 4C RW 8C CC
PRT3DM1 0D RW DCC23IN 4D RW 8D CD
PRT3IC0 0E RW DCC23OU 4E RW 8E CE
PRT3IC1 0F RW DCC23CR1 4F RW 8F CF
PRT4DM0 10 RW 50 90 GDI_O_IN D0 RW
PRT4DM1 11 RW 51 DEC0_CR0 91 RW GDI_E_IN D1 RW
PRT4IC0 12 RW 52 DEC_CR3 92 RW GDI_O_OU D2 RW
PRT4IC1 13 RW 53 93 GDI_E_OU D3 RW
PRT5DM0 14 RW 54 94 DEC0_CR D4 RW
PRT5DM1 15 RW 55 DEC1_CR0 95 RW DEC1_CR D5 RW
PRT5IC0 16 RW 56 DEC_CR4 96 RW DEC2_CR D6 RW
PRT5IC1 17 RW 57 97 DEC3_CR D7 RW
18 58 98 MUX_CR0 D8 RW
19 59 DEC2_CR0 99 RW MUX_CR1 D9 RW
1A 5A DEC_CR5 9A RW MUX_CR2 DA RW
1B 5B 9B MUX_CR3 DB RW
1C 5C 9C DC
1D 5D DEC3_CR0 9D RW OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBC00FN 20 RW CLK_CR0 60 RW GDI_O_IN_CR A0 RW OSC_CR0 E0 RW
DBC00IN 21 RW CLK_CR1 61 RW GDI_E_IN_CR A1 RW OSC_CR1 E1 RW
DBC00OU 22 RW ABF_CR0 62 RW GDI_O_OU_CR A2 RW OSC_CR2 E2 RW
DBC00CR1 23 RW AMD_CR0 63 RW GDI_E_OU_CR A3 RW VLT_CR E3 RW
DBC01FN 24 RW CMP_GO_EN 64 RW RTC_H A4 RW VLT_CMP E4 RW
DBC01IN 25 RW CMP_GO_EN1 65 RW RTC_M A5 RW E5
DBC01OU 26 RW AMD_CR1 66 RW RTC_S A6 RW E6
DBC01CR1 27 RW ALT_CR0 67 RW RTC_CR A7 RW E7
DCC02FN 28 RW ALT_CR1 68 RW SADC_CR0 A8 RW IMO_TR E8 RW
DCC02IN 29 RW CLK_CR2 69 RW SADC_CR1 A9 RW ILO_TR E9 RW
DCC02OU 2A RW AMUX_CFG1 6A RW SADC_CR2 AA RW BDG_TR EA RW
DCC02CR1 2B RW I2C1_CFG 6B RW SADC_CR3 AB RW ECO_TR EB RW
DCC03FN 2C RW TMP_DR0 6C RW SADC_CR4 AC RW MUX_CR4 EC RW
DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW MUX_CR5 ED RW
DCC03OU 2E RW TMP_DR2 6E RW I2C1_ADDR AE RW EE
DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF
DBC10FN 30 RW 70 RDI0RI B0 RW F0
DBC10IN 31 RW SADC_TSCR0 71 RW RDI0SYN B1 RW F1
DBC10OU 32 RW SADC_TSCR1 72 RW RDI0IS B2 RW F2
DBC10CR1 33 RW 73 RDI0LT0 B3 RW F3
DBC11FN 34 RW 74 RDI0LT1 B4 RW F4
DBC11IN 35 RW 75 RDI0RO0 B5 RW F5
DBC11OU 36 RW 76 RDI0RO1 B6 RW F6
DBC11CR1 37 RW 77 RDIODSM B7 RW CPU_F F7 RL
DCC12FN 38 RW 78 RDI1RI B8 RW F8
DCC12IN 39 RW 79 RDI1SYN B9 RW F9
DCC12OU 3A RW 7A RDI1IS BA RW FLS_PR1 FA RW
DCC12CR1 3B RW 7B RDI1LT0 BB RW FB
DCC13FN 3C RW 7C RDI1LT1 BC RW FC
DCC13IN 3D RW 7D RDI1RO0 BD RW FD
DCC13OU 3E RW 7E RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR1 3F RW 7F RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-48111 Rev. *D Page 26 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

CY8C28x45 Register Map Bank 0 Table: User Space

Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW DBC20DR0 40 # ASC10CR0 80 RW RDI2RI C0 RW
PRT0IE 01 RW DBC20DR1 41 W ASC10CR1 81 RW RDI2SYN C1 RW
PRT0GS 02 RW DBC20DR2 42 RW ASC10CR2 82 RW RDI2IS C2 RW
PRT0DM2 03 RW DBC20CR0 43 # ASC10CR3 83 RW RDI2LT0 C3 RW
PRT1DR 04 RW DBC21DR0 44 # ASD11CR0 84 RW RDI2LT1 C4 RW
PRT1IE 05 RW DBC21DR1 45 W ASD11CR1 85 RW RDI2RO0 C5 RW
PRT1GS 06 RW DBC21DR2 46 RW ASD11CR2 86 RW RDI2RO1 C6 RW
PRT1DM2 07 RW DBC21CR0 47 # ASD11CR3 87 RW RDI2DSM C7 RW
PRT2DR 08 RW DCC22DR0 48 # ASC12CR0 88 RW C8
PRT2IE 09 RW DCC22DR1 49 W ASC12CR1 89 RW C9
PRT2GS 0A RW DCC22DR2 4A RW ASC12CR2 8A RW CA
PRT2DM2 0B RW DCC22CR0 4B # ASC12CR3 8B RW CB
PRT3DR 0C RW DCC23DR0 4C # ASD13CR0 8C RW CC
PRT3IE 0D RW DCC23DR1 4D W ASD13CR1 8D RW CD
PRT3GS 0E RW DCC23DR2 4E RW ASD13CR2 8E RW CE
PRT3DM2 0F RW DCC23CR0 4F # ASD13CR3 8F RW CF
PRT4DR 10 RW 50 ASD20CR0 90 RW CUR_PP D0 RW
PRT4IE 11 RW 51 ASD20CR1 91 RW STK_PP D1 RW
PRT4GS 12 RW 52 ASD20CR2 92 RW D2
PRT4DM2 13 RW 53 ASD20CR3 93 RW IDX_PP D3 RW
PRT5DR 14 RW 54 ASC21CR0 94 RW MVR_PP D4 RW
PRT5IE 15 RW 55 ASC21CR1 95 RW MVW_PP D5 RW
PRT5GS 16 RW 56 ASC21CR2 96 RW I2C0_CFG D6 RW
PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C0_SCR D7 #
18 58 ASD22CR0 98 RW I2C0_DR D8 RW
19 59 ASD22CR1 99 RW I2C0_MSCR D9 #
1A 5A ASD22CR2 9A RW INT_CLR0 DA RW
1B 5B ASD22CR3 9B RW INT_CLR1 DB RW
1C 5C ASC23CR0 9C RW INT_CLR2 DC RW
1D 5D ASC23CR1 9D RW INT_CLR3 DD RW
1E 5E ASC23CR2 9E RW INT_MSK3 DE RW
1F 5F ASC23CR3 9F RW INT_MSK2 DF RW
DBC00DR0 20 # AMX_IN 60 RW DEC0_DH A0 RC INT_MSK0 E0 RW
DBC00DR1 21 W AMUX_CFG 61 RW DEC0_DL A1 RC INT_MSK1 E1 RW
DBC00DR2 22 RW CLK_CR3 62 RW DEC1_DH A2 RC INT_VC E2 RC
DBC00CR0 23 # ARF_CR 63 RW DEC1_DL A3 RC RES_WDT E3 W
DBC01DR0 24 # CMP_CR0 64 # DEC2_DH A4 RC I2C1_SCR E4 #
DBC01DR1 25 W ASY_CR 65 # DEC2_DL A5 RC I2C1_MSCR E5 #
DBC01DR2 26 RW CMP_CR1 66 RW DEC3_DH A6 RC DEC_CR0* E6 RW
DBC01CR0 27 # I2C1_DR 67 RW DEC3_DL A7 RC DEC_CR1* E7 RW
DCC02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W
DCC02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W
DCC02DR2 2A RW SADC_DH 6A RW MUL1_DH AA R MUL0_DH EA R
DCC02CR0 2B # SADC_DL 6B RW MUL1_DL AB R MUL0_DL EB R
DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW
DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW
DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW
DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW
DBC10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0
DBC10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1
DBC10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2
DBC10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3
DBC11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4
DBC11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5
DBC11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6
DBC11CR0 37 # ACB01CR2 77 RW RDI0DSM B7 RW CPU_F F7 RL
DCC12DR0 38 # ACB02CR3 78 RW RDI1RI B8 RW F8
DCC12DR1 39 W ACB02CR0 79 RW RDI1SYN B9 RW F9
DCC12DR2 3A RW ACB02CR1 7A RW RDI1IS BA RW FA
DCC12CR0 3B # ACB02CR2 7B RW RDI1LT0 BB RW FB
DCC13DR0 3C # ACB03CR3 7C RW RDI1LT1 BC RW DAC1_D FC RW
DCC13DR1 3D W ACB03CR0 7D RW RDI1RO0 BD RW DAC0_D FD RW
DCC13DR2 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR0 3F # ACB03CR2 7F RW RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-48111 Rev. *D Page 27 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

CY8C28x45 Register Map Bank 1 Table: Configuration Space

Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access
PRT0DM0 00 RW DBC20FN 40 RW 80 RW RDI2RI C0 RW
PRT0DM1 01 RW DBC20IN 41 RW SADC_TSCMPL 81 RW RDI2SYN C1 RW
PRT0IC0 02 RW DBC20OU 42 RW SADC_TSCMPH 82 RW RDI2IS C2 RW
PRT0IC1 03 RW DBC20CR1 43 RW ACE_AMD_CR1 83 RW RDI2LT0 C3 RW
PRT1DM0 04 RW DBC21FN 44 RW 84 RW RDI2LT1 C4 RW
PRT1DM1 05 RW DBC21IN 45 RW ACE_PWM_CR 85 RW RDI2RO0 C5 RW
PRT1IC0 06 RW DBC21OU 46 RW ACE_ADC0_CR 86 RW RDI2RO1 C6 RW
PRT1IC1 07 RW DBC21CR1 47 RW ACE_ADC1_CR 87 RW RDI2DSM C7 RW
PRT2DM0 08 RW DCC22FN 48 RW 88 RW C8
PRT2DM1 09 RW DCC22IN 49 RW ACE_CLK_CR0 89 RW C9
PRT2IC0 0A RW DCC22OU 4A RW ACE_CLK_CR1 8A RW CA
PRT2IC1 0B RW DCC22CR1 4B RW ACE_CLK_CR3 8B RW CB
PRT3DM0 0C RW DCC23FN 4C RW 8C RW CC
PRT3DM1 0D RW DCC23IN 4D RW ACE01CR1 8D RW CD
PRT3IC0 0E RW DCC23OU 4E RW ACE01CR2 8E RW CE
PRT3IC1 0F RW DCC23CR1 4F RW ASE11CR0 8F RW CF
PRT4DM0 10 RW 50 90 GDI_O_IN D0 RW
PRT4DM1 11 RW 51 DEC0_CR0 91 RW GDI_E_IN D1 RW
PRT4IC0 12 RW 52 DEC_CR3 92 RW GDI_O_OU D2 RW
PRT4IC1 13 RW 53 93 GDI_E_OU D3 RW
PRT5DM0 14 RW 54 94 DEC0_CR D4 RW
PRT5DM1 15 RW 55 DEC1_CR0 95 RW DEC1_CR D5 RW
PRT5IC0 16 RW 56 DEC_CR4 96 RW DEC2_CR D6 RW
PRT5IC1 17 RW 57 97 DEC3_CR D7 RW
18 58 98 MUX_CR0 D8 RW
19 59 DEC2_CR0 99 RW MUX_CR1 D9 RW
1A 5A DEC_CR5 9A RW MUX_CR2 DA RW
1B 5B 9B MUX_CR3 DB RW
1C 5C 9C IDAC_CR1 DC RW
1D 5D DEC3_CR0 9D RW OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBC00FN 20 RW CLK_CR0 60 RW GDI_O_IN_CR A0 RW OSC_CR0 E0 RW
DBC00IN 21 RW CLK_CR1 61 RW GDI_E_IN_CR A1 RW OSC_CR1 E1 RW
DBC00OU 22 RW ABF_CR0 62 RW GDI_O_OU_CR A2 RW OSC_CR2 E2 RW
DBC00CR1 23 RW AMD_CR0 63 RW GDI_E_OU_CR A3 RW VLT_CR E3 RW
DBC01FN 24 RW CMP_GO_EN 64 RW RTC_H A4 RW VLT_CMP E4 RW
DBC01IN 25 RW CMP_GO_EN1 65 RW RTC_M A5 RW ADC0_TR E5 RW
DBC01OU 26 RW AMD_CR1 66 RW RTC_S A6 RW ADC1_TR E6 RW
DBC01CR1 27 RW ALT_CR0 67 RW RTC_CR A7 RW IDAC_CR2 E7 RW
DCC02FN 28 RW ALT_CR1 68 RW SADC_CR0 A8 RW IMO_TR E8 RW
DCC02IN 29 RW CLK_CR2 69 RW SADC_CR1 A9 RW ILO_TR E9 RW
DCC02OU 2A RW AMUX_CFG1 6A RW SADC_CR2 AA RW BDG_TR EA RW
DCC02CR1 2B RW I2C1_CFG 6B RW SADC_CR3 AB RW ECO_TR EB RW
DCC03FN 2C RW TMP_DR0 6C RW SADC_CR4 AC RW MUX_CR4 EC RW
DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW MUX_CR5 ED RW
DCC03OU 2E RW TMP_DR2 6E RW I2C1_ADDR AE RW EE
DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF
DBC10FN 30 RW 70 RDI0RI B0 RW F0
DBC10IN 31 RW SADC_TSCR0 71 RW RDI0SYN B1 RW F1
DBC10OU 32 RW SADC_TSCR1 72 RW RDI0IS B2 RW F2
DBC10CR1 33 RW ACE_AMD_CR0 73 RW RDI0LT0 B3 RW F3
DBC11FN 34 RW 74 RDI0LT1 B4 RW F4
DBC11IN 35 RW ACE_AMX_IN 75 RW RDI0RO0 B5 RW F5
DBC11OU 36 RW ACE_CMP_CR0 76 RW RDI0RO1 B6 RW F6
DBC11CR1 37 RW ACE_CMP_CR1 77 RW RDIODSM B7 RW CPU_F F7 RL
DCC12FN 38 RW 78 RDI1RI B8 RW F8
DCC12IN 39 RW ACE_CMP_GI_EN 79 RW RDI1SYN B9 RW F9
DCC12OU 3A RW ACE_ALT_CR0 7A RW RDI1IS BA RW FLS_PR1 FA RW
DCC12CR1 3B RW ACE_ABF_CR0 7B RW RDI1LT0 BB RW FB
DCC13FN 3C RW 7C RDI1LT1 BC RW FC
DCC13IN 3D RW ACE0_CR1 7D RW RDI1RO0 BD RW IDAC_CR0 FD RW
DCC13OU 3E RW ACE0_CR2 7E RW RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR1 3F RW ACE0_CR3 7F RW RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-48111 Rev. *D Page 28 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

CY8C28x52 Register Map Bank 0 Table: User Space

Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW 40 ASC10CR0 80 RW C0
PRT0IE 01 RW 41 ASC10CR1 81 RW C1
PRT0GS 02 RW 42 ASC10CR2 82 RW C2
PRT0DM2 03 RW 43 ASC10CR3 83 RW C3
PRT1DR 04 RW 44 ASD11CR0 84 RW C4
PRT1IE 05 RW 45 ASD11CR1 85 RW C5
PRT1GS 06 RW 46 ASD11CR2 86 RW C6
PRT1DM2 07 RW 47 ASD11CR3 87 RW C7
PRT2DR 08 RW 48 ASC12CR0 88 RW C8
PRT2IE 09 RW 49 ASC12CR1 89 RW C9
PRT2GS 0A RW 4A ASC12CR2 8A RW CA
PRT2DM2 0B RW 4B ASC12CR3 8B RW CB
PRT3DR 0C RW 4C ASD13CR0 8C RW CC
PRT3IE 0D RW 4D ASD13CR1 8D RW CD
PRT3GS 0E RW 4E ASD13CR2 8E RW CE
PRT3DM2 0F RW 4F ASD13CR3 8F RW CF
PRT4DR 10 RW 50 ASD20CR0 90 RW CUR_PP D0 RW
PRT4IE 11 RW 51 ASD20CR1 91 RW STK_PP D1 RW
PRT4GS 12 RW 52 ASD20CR2 92 RW D2
PRT4DM2 13 RW 53 ASD20CR3 93 RW IDX_PP D3 RW
PRT5DR 14 RW 54 ASC21CR0 94 RW MVR_PP D4 RW
PRT5IE 15 RW 55 ASC21CR1 95 RW MVW_PP D5 RW
PRT5GS 16 RW 56 ASC21CR2 96 RW I2C0_CFG D6 RW
PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C0_SCR D7 #
18 58 ASD22CR0 98 RW I2C0_DR D8 RW
19 59 ASD22CR1 99 RW I2C0_MSCR D9 #
1A 5A ASD22CR2 9A RW INT_CLR0 DA RW
1B 5B ASD22CR3 9B RW INT_CLR1 DB RW
1C 5C ASC23CR0 9C RW INT_CLR2 DC RW
1D 5D ASC23CR1 9D RW INT_CLR3 DD RW
1E 5E ASC23CR2 9E RW INT_MSK3 DE RW
1F 5F ASC23CR3 9F RW INT_MSK2 DF RW
DBC00DR0 20 # AMX_IN 60 RW DEC0_DH A0 RC INT_MSK0 E0 RW
DBC00DR1 21 W AMUX_CFG 61 RW DEC0_DL A1 RC INT_MSK1 E1 RW
DBC00DR2 22 RW CLK_CR3 62 RW DEC1_DH A2 RC INT_VC E2 RC
DBC00CR0 23 # ARF_CR 63 RW DEC1_DL A3 RC RES_WDT E3 W
DBC01DR0 24 # CMP_CR0 64 # DEC2_DH A4 RC E4
DBC01DR1 25 W ASY_CR 65 # DEC2_DL A5 RC E5
DBC01DR2 26 RW CMP_CR1 66 RW DEC3_DH A6 RC DEC_CR0* E6 RW
DBC01CR0 27 # 67 DEC3_DL A7 RC DEC_CR1* E7 RW
DCC02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W
DCC02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W
DCC02DR2 2A RW 6A MUL1_DH AA R MUL0_DH EA R
DCC02CR0 2B # 6B MUL1_DL AB R MUL0_DL EB R
DCC03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW
DCC03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW
DCC03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW
DCC03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW
DBC10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0
DBC10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1
DBC10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2
DBC10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3
DBC11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4
DBC11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5
DBC11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6
DBC11CR0 37 # ACB01CR2 77 RW RDI0DSM B7 RW CPU_F F7 RL
DCC12DR0 38 # ACB02CR3 78 RW RDI1RI B8 RW F8
DCC12DR1 39 W ACB02CR0 79 RW RDI1SYN B9 RW F9
DCC12DR2 3A RW ACB02CR1 7A RW RDI1IS BA RW FA
DCC12CR0 3B # ACB02CR2 7B RW RDI1LT0 BB RW FB
DCC13DR0 3C # ACB03CR3 7C RW RDI1LT1 BC RW DAC1_D FC RW
DCC13DR1 3D W ACB03CR0 7D RW RDI1RO0 BD RW DAC0_D FD RW
DCC13DR2 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR0 3F # ACB03CR2 7F RW RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-48111 Rev. *D Page 29 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

CY8C28x52 Register Map Bank 1 Table: Configuration Space

Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access
PRT0DM0 00 RW 40 80 C0
PRT0DM1 01 RW 41 81 C1
PRT0IC0 02 RW 42 82 C2
PRT0IC1 03 RW 43 ACE_AMD_CR1 83 RW C3
PRT1DM0 04 RW 44 84 C4
PRT1DM1 05 RW 45 ACE_PWM_CR 85 RW C5
PRT1IC0 06 RW 46 ACE_ADC0_CR 86 RW C6
PRT1IC1 07 RW 47 ACE_ADC1_CR 87 RW C7
PRT2DM0 08 RW 48 88 C8
PRT2DM1 09 RW 49 ACE_CLK_CR0 89 RW C9
PRT2IC0 0A RW 4A ACE_CLK_CR1 8A RW CA
PRT2IC1 0B RW 4B ACE_CLK_CR3 8B RW CB
PRT3DM0 0C RW 4C 8C CC
PRT3DM1 0D RW 4D ACE01CR1 8D RW CD
PRT3IC0 0E RW 4E ACE01CR2 8E RW CE
PRT3IC1 0F RW 4F ASE11CR0 8F RW CF
PRT4DM0 10 RW 50 90 GDI_O_IN D0 RW
PRT4DM1 11 RW 51 DEC0_CR0 91 RW GDI_E_IN D1 RW
PRT4IC0 12 RW 52 DEC_CR3 92 RW GDI_O_OU D2 RW
PRT4IC1 13 RW 53 93 GDI_E_OU D3 RW
PRT5DM0 14 RW 54 94 DEC0_CR D4 RW
PRT5DM1 15 RW 55 DEC1_CR0 95 RW DEC1_CR D5 RW
PRT5IC0 16 RW 56 DEC_CR4 96 RW DEC2_CR D6 RW
PRT5IC1 17 RW 57 97 DEC3_CR D7 RW
18 58 98 MUX_CR0 D8 RW
19 59 DEC2_CR0 99 RW MUX_CR1 D9 RW
1A 5A DEC_CR5 9A RW MUX_CR2 DA RW
1B 5B 9B MUX_CR3 DB RW
1C 5C 9C IDAC_CR1 DC RW
1D 5D DEC3_CR0 9D RW OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBC00FN 20 RW CLK_CR0 60 RW GDI_O_IN_CR A0 RW OSC_CR0 E0 RW
DBC00IN 21 RW CLK_CR1 61 RW GDI_E_IN_CR A1 RW OSC_CR1 E1 RW
DBC00OU 22 RW ABF_CR0 62 RW GDI_O_OU_CR A2 RW OSC_CR2 E2 RW
DBC00CR1 23 RW AMD_CR0 63 RW GDI_E_OU_CR A3 RW VLT_CR E3 RW
DBC01FN 24 RW CMP_GO_EN 64 RW RTC_H A4 RW VLT_CMP E4 RW
DBC01IN 25 RW CMP_GO_EN1 65 RW RTC_M A5 RW ADC0_TR E5 RW
DBC01OU 26 RW AMD_CR1 66 RW RTC_S A6 RW ADC1_TR E6 RW
DBC01CR1 27 RW ALT_CR0 67 RW RTC_CR A7 RW IDAC_CR2 E7 RW
DCC02FN 28 RW ALT_CR1 68 RW A8 IMO_TR E8 RW
DCC02IN 29 RW CLK_CR2 69 RW A9 ILO_TR E9 RW
DCC02OU 2A RW AMUX_CFG1 6A RW AA BDG_TR EA RW
DCC02CR1 2B RW 6B AB ECO_TR EB RW
DCC03FN 2C RW TMP_DR0 6C RW AC MUX_CR4 EC RW
DCC03IN 2D RW TMP_DR1 6D RW I2C0_ADDR AD RW MUX_CR5 ED RW
DCC03OU 2E RW TMP_DR2 6E RW AE EE
DCC03CR1 2F RW TMP_DR3 6F RW AMUX_CLK AF RW EF
DBC10FN 30 RW 70 RDI0RI B0 RW F0
DBC10IN 31 RW 71 RDI0SYN B1 RW F1
DBC10OU 32 RW 72 RDI0IS B2 RW F2
DBC10CR1 33 RW ACE_AMD_CR0 73 RW RDI0LT0 B3 RW F3
DBC11FN 34 RW 74 RDI0LT1 B4 RW F4
DBC11IN 35 RW ACE_AMX_IN 75 RW RDI0RO0 B5 RW F5
DBC11OU 36 RW ACE_CMP_CR0 76 RW RDI0RO1 B6 RW F6
DBC11CR1 37 RW ACE_CMP_CR1 77 RW RDIODSM B7 RW CPU_F F7 RL
DCC12FN 38 RW 78 RDI1RI B8 RW F8
DCC12IN 39 RW ACE_CMP_GI_EN 79 RW RDI1SYN B9 RW F9
DCC12OU 3A RW ACE_ALT_CR0 7A RW RDI1IS BA RW FLS_PR1 FA RW
DCC12CR1 3B RW ACE_ABF_CR0 7B RW RDI1LT0 BB RW FB
DCC13FN 3C RW 7C RDI1LT1 BC RW FC
DCC13IN 3D RW ACE0_CR1 7D RW RDI1RO0 BD RW IDAC_CR0 FD RW
DCC13OU 3E RW ACE0_CR2 7E RW RDI1RO1 BE RW CPU_SCR1 FE #
DCC13CR1 3F RW ACE0_CR3 7F RW RDI1DSM BF RW CPU_SCR0 FF #
Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251

Document Number: 001-48111 Rev. *D Page 30 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C28xxx PSoC devices. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. Specifications for devices running at greater than
12 MHz are valid for -40oC ≤ TA ≤ 70oC and TJ ≤ 82oC.
Figure 7. Voltage versus CPU Frequency

5.25

Va rat on
4.75

O R eg
pe i
lid ing
Vdd Voltage

3.00

93 kHz 12 MHz 24 MHz

CPU Frequency

The following table lists the units of measure that are used in this section.

Table 8. Units of Measure

Symbol Unit of Measure Symbol Unit of Measure

o
C degree Celsius μW microwatts
dB decibels mA milli-ampere
fF femto farad ms milli-second
Hz hertz mV milli-volts
KB 1024 bytes nA nanoampere
Kbit 1024 bits ns nanosecond
kHz kilohertz nV nanovolts
kΩ kilohm Ω ohm
MHz megahertz pA picoampere
MΩ megaohm pF picofarad
μA microampere pp peak-to-peak
μF microfarad ppm parts per million
μH microhenry ps picosecond
μs microsecond ksps kilo-samples per second
μV microvolts ∑ sigma: one standard deviation
μVrms microvolts root-mean-square V volts

Document Number: 001-48111 Rev. *D Page 31 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Absolute Maximum Ratings

Table 9. Absolute Maximum Ratings

Symbol Description Min Typ Max Units Notes

o
TSTG Storage Temperature -55 25 +100 C Higher storage temperatures reduce
data retention time. Recommended
storage temperature is +25oC ±
25oC. Extended duration storage
temperatures above 65oC degrade
reliability.
o
TA Ambient Temperature with Power Applied -40 – +85 C
Vdd Supply Voltage on Vdd Relative to Vss -0.5 – +6.0 V
VIO DC Input Voltage Vss- – Vdd + V
0.5 0.5
VIOZ DC Voltage Applied to Tri-state Vss - – Vdd + V
0.5 0.5
IMIO Maximum Current into any Port Pin -25 – +50 mA
IMAIO Maximum Current into any Port Pin -50 – +50 mA
Configured as Analog Driver
ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD.
LU Latch-up Current – – 200 mA

Operating Temperature
Table 10. Operating Temperature

Symbol Description Min Typ Max Units Notes

oC
TA Ambient Temperature -40 – +85
TJ Junction Temperature -40 – +100 oC The temperature rise from ambient to
junction is package specific. See
Thermal Impedances on page 60. The
user must limit the power
consumption to comply with this
requirement.

Document Number: 001-48111 Rev. *D Page 32 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

DC Electrical Characteristics
DC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 11. DC Chip Level Specifications

Symbol Description Min Typ Max Units Notes

Vdd Supply Voltage 3.00 – 5.25 V
IDD Supply Current – 8 14 mA Conditions are Vdd = 5.0V, TA = 25 oC,
CPU = 3 MHz, SYSCLK doubler
disabled. VC1 = 1.5 MHz, VC2 = 93.75
kHz, VC3 = 93.75 kHz.
IDD3 Supply Current – 5 9 mA Conditions are Vdd = 3.3V, TA = 25 oC,
CPU = 3 MHz, SYSCLK doubler
disabled. VC1 = 1.5 MHz, VC2 = 93.75
kHz, VC3 = 93.75 kHz.
ISB Sleep (Mode) Current with POR, LVD, Sleep – 3 10 μA Conditions are with internal slow
Timer, and WDT.[13] speed oscillator, Vdd = 3.3V, -40 oC ≤
TA ≤ 55 oC.
ISBH Sleep (Mode) Current with POR, LVD, Sleep – 4 25 μA Conditions are with internal slow
Timer, and WDT at high temperature.[13] speed oscillator, Vdd = 3.3V, 55 oC <
TA ≤ 85 oC.
ISBXTL Sleep (Mode) Current with POR, LVD, Sleep – 4 11 μA Conditions are with properly loaded, 1
Timer, WDT, and external crystal.[13] μW max, 32.768 kHz crystal. Vdd =
3.3V, -40 oC ≤ TA ≤ 55 oC.
ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep – 5 26 μA Conditions are with properly loaded, 1
Timer, WDT, and external crystal at high μW max, 32.768 kHz crystal. Vdd =
temperature.[13] 3.3V, 55 oC < TA ≤ 85 oC.
VREF Reference Voltage (Bandgap) 1.280 1.300 1.320 V Trimmed for appropriate Vdd.
IXRES 1.00 – 1.058 mA

Note
13. Standby (sleep) current includes all functions (POR, LVD, WDT, Sleep Timer) needed for reliable system operation. This should be compared with devices that have
similar functions enabled.

Document Number: 001-48111 Rev. *D Page 33 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

DC General Purpose I/O Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 12. DC GPIO Specifications

Symbol Description Min Typ Max Units Notes
RPU Pull Up Resistor 4 5.6 8 kΩ
RPD Pull Down Resistor 4 5.6 8 kΩ
VOH High Output Level Vdd - – – V IOH = 10 mA, Vdd = 4.75 to 5.25V (8
1.0 total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
VOL Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
IOH High Level Source Current 10 – – mA VOH = Vdd-1.0V, see the limitations of
the total current in the note for VOH.
IOL Low Level Sink Current 25 – – mA VOL = 0.75V, see the limitations of the
total current in the note for VOL.
VIL Input Low Level – – 0.8 V Vdd = 3.0 to 5.25.
VIH Input High Level 2.1 – V Vdd = 3.0 to 5.25.
VH Input Hysteresis – 60 – mV
IIL Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μA.
CIN Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent. Temp =
25oC.
COUT Capacitive Load on Pins as Output – 3.5 10 pF Package and pin dependent. Temp =
25oC.

DC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only. The Operational Amplifiers covered by these specifications are components of both the Analog
Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog
Continuous Time PSoC block.

Table 13. 5V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes
VOSOA Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High – 1.6 10 mV
Power = Medium, Opamp Bias = High – 1.3 10 mV
Power = High, Opamp Bias = High – 1.2 10 mV
TCVOSOA Average Input Offset Voltage Drift – 7.0 35.0 μV/oC
IEBOA Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA.
CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. Temp =
25oC.
VCMOA Common Mode Voltage Range 0.0 – Vdd V The common-mode input voltage
Common Mode Voltage Range (high power 0.5 – Vdd - range is measured through an analog
or high opamp bias) 0.5 output buffer. The specification
includes the limitations imposed by
the characteristics of the analog
output buffer.

Document Number: 001-48111 Rev. *D Page 34 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Table 13. 5V DC Operational Amplifier Specifications (continued)

Symbol Description Min Typ Max Units Notes
CMRROA Common Mode Rejection Ratio – – dB Specification is applicable at high
Power = Low 60 power. For all other bias modes
Power = Medium 60 (except high power, high opamp
Power = High 60 bias), minimum is 60 dB.
GOLOA Open Loop Gain – – dB Specification is applicable at high
Power = Low 60 power. For all other bias modes
Power = Medium 60 (except high power, high opamp
Power = High 80 bias), minimum is 60 dB.
VOHIGHOA High Output Voltage Swing (internal signals)
Power = Low Vdd - – – V
Power = Medium 0.2 – – V
Power = High Vdd - – – V
0.2
Vdd -
0.5
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low – – 0.2 V
Power = Medium – – 0.2 V
Power = High – – 0.5 V
ISOA Supply Current (including associated AGND
buffer)
Power = Low, Opamp Bias = Low – 150 200 μA
Power = Low, Opamp Bias = High – 300 400 μA
Power = Medium, Opamp Bias = Low – 600 800 μA
Power = Medium, Opamp Bias = High – 1200 1600 μA
Power = High, Opamp Bias = Low – 2400 3200 μA
Power = High, Opamp Bias = High – 4600 6400 μA
PSRROA Supply Voltage Rejection Ratio 60 – – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd -
1.25V) ≤ VIN ≤ Vdd.

Table 14. 3.3V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes
VOSOA Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High – 1.65 10 mV
Power = Medium, Opamp Bias = High – 1.32 8 mV
High Power is 5 Volts Only
TCVOSOA Average Input Offset Voltage Drift – 7.0 35.0 μV/oC
IEBOA Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA.
CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. Temp =
25oC.
VCMOA Common Mode Voltage Range 0.2 – Vdd - 0.2 V The common-mode input voltage
range is measured through an
analog output buffer. The specifi-
cation includes the limitations
imposed by the characteristics of the
analog output buffer.
CMRROA Common Mode Rejection Ratio – – dB Specification is applicable at high
Power = Low 50 power. For all other bias modes
Power = Medium 50 (except high power, high opamp
Power = High 50 bias), minimum is 50 dB.
GOLOA Open Loop Gain – – dB Specification is applicable at high
Power = Low 60 power. For all other bias modes
Power = Medium 60 (except high power, high opamp
Power = High 80 bias), minimum is 60 dB.

Document Number: 001-48111 Rev. *D Page 35 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Table 14. 3.3V DC Operational Amplifier Specifications (continued)

Symbol Description Min Typ Max Units Notes
VOHIGHOA High Output Voltage Swing (internal signals)
Power = Low Vdd - – – V
Power = Medium 0.2 – – V
Power = High is 5V only Vdd - – – V
0.2
Vdd -
0.2
VOLOWOA Low Output Voltage Swing (internal signals)
Power = Low – – 0.2 V
Power = Medium – – 0.2 V
Power = High – – 0.2 V
ISOA Supply Current (including associated AGND
buffer) – 150 200 μA
Power = Low, Opamp Bias = Low – 300 400 μA
Power = Low, Opamp Bias = High – 600 800 μA
Power = Medium, Opamp Bias = Low – 1200 1600 μA
Power = Medium, Opamp Bias = High – 2400 3200 μA
Power = High, Opamp Bias = Low – 4600 6400 μA
Power = High, Opamp Bias = High
PSRROA Supply Voltage Rejection Ratio 50 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd -
1.25V) ≤ VIN ≤ Vdd.

DC Type-E Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C £ TA £ 85°C, or 3.0V to 3.6V and -40°C £ TA £ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only. The Operational Amplifiers covered by these specifications are components of the Limited Type E Analog
PSoC blocks.
Table 15. 5V DC Type-E Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA Input Offset Voltage (absolute value) – 2.5 15 mV For 0.2V < Vin < Vdd - 1.2V.
– 2.5 20 mV For Vin = 0 to 0.2V and Vin > Vdd -
1.2V.
TCVOSOA Average Input Offset Voltage Drift – 10 – μV/oC
IEBOA[14] Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA.
CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. Temp
= 25oC.
VCMOA Common Mode Voltage Range 0.0 – Vdd - 1 V
ISOA Amplifier Supply Current – 10 30 μA

Table 16. 3.3V DC Type-E Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes
VOSOA Input Offset Voltage (absolute value) – 2.5 15 mV For 0.2V < Vin < Vdd - 1.2V.
– 2.5 20 mV For Vin = 0 to 0.2V and Vin > Vdd -
1.2V.
TCVOSOA Average Input Offset Voltage Drift – 10 – μV/oC
IEBOA[14] Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA.
CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. Temp =
25oC.
VCMOA Common Mode Voltage Range 0 – Vdd - 1 V
ISOA Amplifier Supply Current – 10 30 μA

Note
14. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25°C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.

Document Number: 001-48111 Rev. *D Page 36 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

DC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.

Table 17. DC Low Power Comparator Specifications

Symbol Description Min Typ Max Units Notes
VREFLPC Low power comparator (LPC) reference 0.2 – Vdd - 1 V
voltage range
VOSLPC LPC voltage offset – 2.5 30 mV
ISLPC LPC supply current – 10 40 μA

DC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 18. 5V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

VOSOB Input Offset Voltage (Absolute Value) – 3 12 mV
TCVOSOB Average Input Offset Voltage Drift – +6 TBD μV/°C
VCMOB Common-Mode Input Voltage Range 0.5 – Vdd - 1.0 V
ROUTOB Output Resistance
Power = Low – 1 – Ω
Power = High – 1 – Ω
VOHIGHOB High Output Voltage Swing (Load = 32
ohms to Vdd/2)
Power = Low 0.5 x Vdd – – V
+ 1.3
Power = High 0.5 x Vdd – – V
+ 1.3
VOLOWOB Low Output Voltage Swing (Load = 32 ohms
to Vdd/2)
Power = Low – – 0.5 x Vdd V
- 1.3
Power = High – – 0.5 x Vdd V
- 1.3
ISOB Supply Current Including Bias Cell (No
Load)
Power = Low – 1.1 5.1 mA
Power = High – 2.6 8.8 mA
PSRROB Supply Voltage Rejection Ratio 60 64 – dB

Document Number: 001-48111 Rev. *D Page 37 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Table 19. 3.3V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes
VOSOB Input Offset Voltage (Absolute Value) – 3 12 mV
TCVOSOB Average Input Offset Voltage Drift – +6 TBD μV/°C
VCMOB Common-Mode Input Voltage Range 0.5 - Vdd - 1.0 V
ROUTOB Output Resistance
Power = Low – 1 – Ω
Power = High – 1 – Ω
VOHIGHOB High Output Voltage Swing (Load = 1k ohms
to Vdd/2)
Power = Low 0.5 x Vdd – – V
+ 1.0
Power = High 0.5 x Vdd – – V
+ 1.0
VOLOWOB Low Output Voltage Swing (Load = 1k ohms
to Vdd/2)
Power = Low – – 0.5 x Vdd V
- 1.0
Power = High – – 0.5 x Vdd V
- 1.0
ISOB Supply Current Including Bias Cell (No Load)
Power = Low 0.8 2.0 mA
Power = High – 2.0 4.3 mA
PSRROB Supply Voltage Rejection Ratio 60 64 – dB

Document Number: 001-48111 Rev. *D Page 38 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

DC Switch Mode Pump Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 20. DC Switch Mode Pump (SMP) Specifications

Symbol Description Min Typ Max Units Notes
VPUMP 5V 5V Output Voltage 4.75 5.0 5.25 V Configuration of footnote.[15]
Average, neglecting ripple. SMP trip
voltage is set to 5.0V.
VPUMP 3V 3V Output Voltage 3.00 3.25 3.60 V Configuration of footnote.[15]
Average, neglecting ripple. SMP trip
voltage is set to 3.25V.
IPUMP Available Output Current Configuration of footnote.[15]
VBAT = 1.5V, VPUMP = 3.25V 8 – – mA SMP trip voltage is set to 3.25V.
VBAT = 1.8V, VPUMP = 5.0V 5 – – mA SMP trip voltage is set to 5.0V.
To get better performance, refer to
Cypress application note, AN2349.
VBAT5V Input Voltage Range from Battery 1.8 – 5.0 V Configuration of footnote.[15] SMP trip
voltage is set to 5.0V.
VBAT3V Input Voltage Range from Battery 1.5 – 3.3 V Configuration of footnote.[15] SMP trip
voltage is set to 3.25V.
VBATSTART Minimum Input Voltage from Battery to 1.1 – – V Configuration of footnote.[15]
Start Pump
ΔVPUMP_Line Line Regulation (over VBAT range) – 5 – %VO Configuration of footnote.[15] VO is the
“Vdd Value for PUMP Trip” specified
by the VM[2:0] setting in the DC POR
and LVD Specification, Table 30 on
page 45.
ΔVPUMP_Load Load Regulation – 5 – %VO Configuration of footnote.[15] VO is the
“Vdd Value for PUMP Trip” specified
by the VM[2:0] setting in the DC POR
and LVD Specification, Table 30 on
page 45.
ΔVPUMP_Ripple Output Voltage Ripple (depends on – 100 – mVpp Configuration of footnote.[15] Load is
capacitor/load) 5mA.
E3 Efficiency 35 50 – % Configuration of footnote.[15] Load is
5 mA. SMP trip voltage is set to 3.25V.
FPUMP Switching Frequency – 1.3 – MHz
DCPUMP Switching Duty Cycle – 50 – %

Note
15. L1 = 2 uH inductor, C1 = 10 uF capacitor, D1 = Schottky diode. See Figure 8.

Document Number: 001-48111 Rev. *D Page 39 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Figure 8. Basic Switch Mode Pump Circuit

D1

Vdd V PUMP

L1 C1
SMP
+
V BAT Battery PSoC TM

Vss

DC Analog Reference Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.

Table 21. 5V DC Analog Reference Specifications for High Power

Symbol Description Min Typ Max Units

VBG5 Bandgap Voltage Reference 5V 1.28 1.30 1.32 V
– AGND = Vdd/2[16] Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V
– AGND = 2 x BandGap[16] 2.52 2.60 2.72 V
– AGND = P2[4] (P2[4] = Vdd/2)[16] P2[4] - 0.013 P2[4] P2[4] + 0.013 V
– AGND = BandGap[16] 1.27 1.3 1.34 V
– AGND = 1.6 x BandGap[16] 2.03 2.08 2.13 V
– AGND Block to Block Variation (AGND = Vdd/2)[16] -0.034 0.000 0.034 V
– RefHi = Vdd/2 + BandGap Vdd/2 + 1.21 Vdd/2 + 1.3 Vdd/2 + 1.382 V
– RefHi = 3 x BandGap 3.75 3.9 4.05 V
– RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) P2[6] + 2.478 P2[6] + 2.6 P2[6] + 2.722 V
– RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + 1.218 P2[4] + 1.3 P2[4] + 1.382 V
– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] - P2[4] + P2[6] P2[4] + P2[6] + V
0.058 0.058
– RefHi = 2 x BandGap 2.50 2.60 2.70 V
– RefHi = 3.2 x BandGap 4.02 4.16 4.29 V
– RefLo = Vdd/2 – BandGap Vdd/2 - 1.369 Vdd/2 - 1.30 Vdd/2 - 1.231 V
– RefLo = BandGap 1.20 1.30 1.40 V
– RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2.489 - P2[6] 2.6 - P2[6] 2.711 - P2[6] V
– RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] - 1.368 P2[4] - 1.30 P2[4] - 1.232 V
– RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] - P2[4] - P2[6] P2[4] - P2[6] + V
0.042 0.042

Note
16. AGND tolerance includes the offsets of the local buffer in the PSoC block.

Document Number: 001-48111 Rev. *D Page 40 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Table 22. 5V DC Analog Reference Specifications for Medium Power

Symbol Description Min Typ Max Units
VBG5 Bandgap Voltage Reference 5V 1.28 1.30 1.32 V
– AGND = Vdd/2[16] Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V
– AGND = 2 x BandGap[16] 2.52 2.60 2.72 V
– AGND = P2[4] (P2[4] = Vdd/2)[16] P2[4] - 0.013 P2[4] P2[4] + 0.013 V
– AGND = BandGap[16] 1.27 1.3 1.34 V
– AGND = 1.6 x BandGap[16] 2.03 2.08 2.13 V
– AGND Block to Block Variation (AGND = Vdd/2)[16] -0.034 0.000 0.034 V
– RefHi = Vdd/2 + BandGap Vdd/2 + 1.21 Vdd/2 + 1.3 Vdd/2 + 1.382 V
– RefHi = 3 x BandGap 3.75 3.9 4.05 V
– RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) P2[6] + 2.478 P2[6] + 2.6 P2[6] + 2.722 V
– RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + 1.218 P2[4] + 1.3 P2[4] + 1.382 V
– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] - P2[4] + P2[6] P2[4] + P2[6] + V
0.058 0.058
– RefHi = 2 x BandGap 2.50 2.60 2.70 V
– RefHi = 3.2 x BandGap 4.02 4.16 4.29 V
– RefLo = Vdd/2 – BandGap Vdd/2 - 1.369 Vdd/2 - 1.30 Vdd/2 - 1.231 V
– RefLo = BandGap 1.20 1.30 1.40 V
– RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2.489 - P2[6] 2.6 - P2[6] 2.711 - P2[6] V
– RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] - 1.368 P2[4] - 1.30 P2[4] - 1.232 V
– RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] - P2[4] - P2[6] P2[4] - P2[6] + V
0.042 0.042

Table 23. 5V DC Analog Reference Specifications for Low Power

Symbol Description Min Typ Max Units

VBG5 Bandgap Voltage Reference 5V 1.28 1.30 1.32 V
– AGND = Vdd/2[16] Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V
– AGND = 2 x BandGap[16] 2.52 2.60 2.72 V
– AGND = P2[4] (P2[4] = Vdd/2)[16] P2[4] - 0.013 P2[4] P2[4] + 0.013 V
– AGND = BandGap[16] 1.27 1.3 1.34 V
– AGND = 1.6 x BandGap[16] 2.03 2.08 2.13 V
– AGND Block to Block Variation (AGND = Vdd/2)[16] -0.034 0.000 0.034 V
– RefHi = Vdd/2 + BandGap Vdd/2 + 1.21 Vdd/2 + 1.3 Vdd/2 + 1.382 V
– RefHi = 3 x BandGap 3.75 3.9 4.05 V
– RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) P2[6] + 2.478 P2[6] + 2.6 P2[6] + 2.722 V
– RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + 1.218 P2[4] + 1.3 P2[4] + 1.382 V
– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] - P2[4] + P2[6] P2[4] + P2[6] + V
0.058 0.058
– RefHi = 2 x BandGap 2.50 2.60 2.70 V
– RefHi = 3.2 x BandGap 4.02 4.16 4.29 V
– RefLo = Vdd/2 – BandGap Vdd/2 - 1.369 Vdd/2 - 1.30 Vdd/2 - 1.231 V
– RefLo = BandGap 1.20 1.30 1.40 V
– RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2.489 - P2[6] 2.6 - P2[6] 2.711 - P2[6] V
– RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] - 1.368 P2[4] - 1.30 P2[4] - 1.232 V
– RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] - P2[4] - P2[6] P2[4] - P2[6] + V
0.042 0.042

Document Number: 001-48111 Rev. *D Page 41 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Table 24. 3.3V DC Analog Reference Specifications for High Power

Symbol Description Min Typ Max Units
VBG33 Bandgap Voltage Reference 3.3V 1.28 1.30 1.32 V
– AGND = Vdd/2[16] Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V
– AGND = 2 x BandGap[16] Not Allowed
– AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.009 P2[4] P2[4] + 0.009 V
– AGND = BandGap[16] 1.27 1.30 1.34 V
– AGND = 1.6 x BandGap[16] 2.03 2.08 2.13 V
– AGND Block to Block Variation (AGND = Vdd/2)[16] -0.034 0.000 0.034 mV
– RefHi = Vdd/2 + BandGap Not Allowed
– RefHi = 3 x BandGap Not Allowed
– RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed
– RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed
– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
P2[4] + P2[6] - P2[4] + P2[6] P2[4] + P2[6] + V
0.042 0.042
– RefHi = 2 x BandGap 2.50 2.60 2.70 V
– RefHi = 3.2 x BandGap Not Allowed
– RefLo = Vdd/2 - BandGap Not Allowed
– RefLo = BandGap Not Allowed
– RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed
– RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed
– RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] - P2[4] - P2[6] P2[4] - P2[6] + V
0.036 0.036

Table 25. 3.3V DC Analog Reference Specifications for Medium Power

Symbol Description Min Typ Max Units

VBG33 Bandgap Voltage Reference 3.3V 1.28 1.30 1.32 V
– AGND = Vdd/2[16] Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V
– AGND = 2 x BandGap[16] Not Allowed
– AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.009 P2[4] P2[4] + 0.009 V
– AGND = BandGap[16] 1.27 1.30 1.34 V
– AGND = 1.6 x BandGap[16] 2.03 2.08 2.13 V
– AGND Block to Block Variation (AGND = Vdd/2)[16] -0.034 0.000 0.034 mV
– RefHi = Vdd/2 + BandGap Not Allowed
– RefHi = 3 x BandGap Not Allowed
– RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed
– RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed
– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
P2[4] + P2[6] - P2[4] + P2[6] P2[4] + P2[6] + V
0.042 0.042
– RefHi = 2 x BandGap 2.50 2.60 2.70 V
– RefHi = 3.2 x BandGap Not Allowed
– RefLo = Vdd/2 - BandGap Not Allowed
– RefLo = BandGap Not Allowed
– RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed
– RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed
– RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] - P2[4] - P2[6] P2[4] - P2[6] + V
0.036 0.036

Document Number: 001-48111 Rev. *D Page 42 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Table 26. 3.3V DC Analog Reference Specifications for Low Power

Symbol Description Min Typ Max Units
VBG33 Bandgap Voltage Reference 3.3V 1.28 1.30 1.32 V
– AGND = Vdd/2[16] Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V
– AGND = 2 x BandGap[16] Not Allowed
– AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.009 P2[4] P2[4] + 0.009 V
– AGND = BandGap[16] 1.27 1.30 1.34 V
– AGND = 1.6 x BandGap[16] 2.03 2.08 2.13 V
– AGND Block to Block Variation (AGND = Vdd/2)[16] -0.034 0.000 0.034 mV
– RefHi = Vdd/2 + BandGap Not Allowed
– RefHi = 3 x BandGap Not Allowed
– RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed
– RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed
– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
P2[4] + P2[6] - P2[4] + P2[6] P2[4] + P2[6] + V
0.042 0.042
– RefHi = 2 x BandGap 2.50 2.60 2.70 V
– RefHi = 3.2 x BandGap Not Allowed
– RefLo = Vdd/2 - BandGap Not Allowed
– RefLo = BandGap Not Allowed
– RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed
– RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed
– RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] - P2[4] - P2[6] P2[4] - P2[6] + V
0.036 0.036

Note See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on
trimming for operation at 3.3V.

DC Analog PSoC Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 27. DC Analog PSoC Block Specifications

Symbol Description Min Typ Max Units Notes
RCT Resistor Unit Value (Continuous Time) – 12.24 – kΩ
CSC Capacitor Unit Value (Switch Cap) – 80 – fF

DC Analog Mux Bus Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 28. DC Analog Mux Bus Specifications

Symbol Description Min Typ Max Units Notes
RSW Switch Resistance to Common Analog Bus – – 400 Ω Vdd ≥ 3.0V
RVSS Resistance of Initialization Switch to VSS – – 800 Ω

Document Number: 001-48111 Rev. *D Page 43 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

DC SAR10 ADC Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 29. DC SAR10 ADC Specifications

Symbol Description Min Typ Max Units Notes

INLSAR10 Integral nonlinearity -2.5 - 2.5 LSB 10-bit resolution
DNLSAR10 Differential nonlinearity -1.5 - 1.5 LSB 10-bit resolution
ISAR10 Active current consumption 0.08 TBD 0.497 mA
IVREFSAR10 Input current into P2[5] when configured as - - 0.5 mA The internal voltage reference buffer is
the SAR10 ADC's VREF input. disabled in this configuration.
VVREFSAR10 Input reference voltage at P2[5] when 3.0 - 4.95 V When VREF is buffered inside the SAR10
configured as the SAR10 ADC's external ADC, the voltage level at P2[5] (when
voltage reference. configured as the external reference
voltage) must always be at least 300 mV
less than the chip supply voltage level on
the Vdd pin.
(VVREFSAR10 < (Vdd - 300 mV) ).
VOSSAR10 Offset voltage 5 TBD 9 mV

Document Number: 001-48111 Rev. *D Page 44 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

DC POR and LVD Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Programmable System-on-Chip
Technical Reference Manual for CY8C28xxx PSoC devices, for more information on the VLT_CR register.

Table 30. DC POR and LVD Specifications

Symbol Description Min Typ Max Units Notes
Vdd Value for PPOR Trip (positive ramp) Vdd must be greater than or equal
VPPOR0R PORLEV[1:0] = 00b 2.91 V to 2.5V during startup, reset from
VPPOR1R PORLEV[1:0] = 01b – 4.39 – V the XRES pin, or reset from
VPPOR2R PORLEV[1:0] = 10b 4.55 V Watchdog.
Vdd Value for PPOR Trip (negative ramp)
VPPOR0 PORLEV[1:0] = 00b 2.82 V
VPPOR1 PORLEV[1:0] = 01b – 4.39 – V
VPPOR2 PORLEV[1:0] = 10b 4.55 V
PPOR Hysteresis
VPH0 PORLEV[1:0] = 00b – 92 – mV
VPH1 PORLEV[1:0] = 01b – 0 – mV
VPH2 PORLEV[1:0] = 10b – 0 – mV
Vdd Value for LVD Trip
VLVD0 VM[2:0] = 000b 2.86 2.92 2.98[17] V
VLVD1 VM[2:0] = 001b 2.96 3.02 3.08 V
VLVD2 VM[2:0] = 010b 3.07 3.13 3.20 V
VLVD3 VM[2:0] = 011b 3.92 4.00 4.08 V
VLVD4 VM[2:0] = 100b 4.39 4.48 4.57 V
VLVD5 VM[2:0] = 101b 4.55 4.64 4.74[18] V
VLVD6 VM[2:0] = 110b 4.63 4.73 4.82 V
VLVD7 VM[2:0] = 111b 4.72 4.81 4.91 V
Vdd Value for PUMP Trip
VPUMP0 VM[2:0] = 000b 2.96 3.02 3.08 V
VPUMP1 VM[2:0] = 001b 3.03 3.10 3.16 V
VPUMP2 VM[2:0] = 010b 3.18 3.25 3.32 V
VPUMP3 VM[2:0] = 011b 4.11 4.19 4.28 V
VPUMP4 VM[2:0] = 100b 4.55 4.64 4.74 V
VPUMP5 VM[2:0] = 101b 4.63 4.73 4.82 V
VPUMP6 VM[2:0] = 110b 4.72 4.82 4.91 V
VPUMP7 VM[2:0] = 111b 4.90 5.00 5.10 V

Notes
17. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
18. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.

Document Number: 001-48111 Rev. *D Page 45 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 31. DC Programming Specifications

Symbol Description Min Typ Max Units Notes

IDDP Supply Current During Programming or Verify – 5 25 mA
VILP Input Low Voltage During Programming or – – 0.8 V
Verify
VIHP Input High Voltage During Programming or 2.2 – – V
Verify
IILP Input Current when Applying Vilp to P1[0] or – – 0.2 mA Driving internal pull-down
P1[1] During Programming or Verify resistor.
IIHP Input Current when Applying Vihp to P1[0] or – – 1.5 mA Driving internal pull-down
P1[1] During Programming or Verify resistor.
VOLV Output Low Voltage During Programming or – – Vss + 0.75 V
Verify
VOHV Output High Voltage During Programming or Vdd - 1.0 – Vdd V
Verify
FlashENPB Flash Endurance (per block) 50,000 – – – Erase/write cycles per block.
FlashENT Flash Endurance (total)[19] 1,800,000 – – – Erase/write cycles.
FlashDR Flash Data Retention 10 – – Years

Note
19. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever
sees more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

Document Number: 001-48111 Rev. *D Page 46 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 32. AC Chip-Level Specifications

Symbol Description Min Typ Max Units Notes
FIMO Internal Main Oscillator Frequency 23.4 24 24.6[20] MHz Trimmed. Utilizing factory trim values.
FIMO6 Internal Main Oscillator Frequency for 5.5 6 6.5[20] MHz Trimmed for 5V or 3.3V operation
6 MHz using factory trim values. SLIMO
Mode = 1.
FCPU1 CPU Frequency (5V Nominal) 0.091 24 24.6[20, 21] MHz Trimmed. Utilizing factory trim values.
FCPU2 CPU Frequency (3.3V Nominal) 0.091 12 12.3[21,22] MHz Trimmed. Utilizing factory trim values.
FBLK5 Digital PSoC Block Frequency 0 - 49.2[20,21,23] MHz 4.75V< Vdd <5.25V
FBLK33 Digital PSoC Block Frequency 0 24 24.6[21, 23] MHz 3.0V<Vdd<3.6V
F32K1 Internal Low Speed Oscillator 15 32 64 kHz Trimmed. Utilizing factory trim values.
Frequency
F32K2 External Crystal Oscillator – 32.768 – kHz Accuracy is capacitor and crystal
dependent. 50% duty cycle.
F32K_U Internal Low Speed Oscillator 5 – – kHz After a reset and before the m8c starts
Untrimmed Frequency to run, the ILO is not trimmed. See the
System Resets section of the PSoC
Technical Reference manual for
details on timing this.
FPLL PLL Frequency – 23.986 – MHz Multiple (x732) of crystal frequency.
Jitter24M2 24 MHz RMS Period Jitter (PLL) – – 600 ps
TPLLSLEW PLL Lock Time 0.5 – 10 ms
TPLLSLEWS PLL Lock Time for Low Gain Setting 0.5 – 50 ms
LOW
TOS External Crystal Oscillator Startup to – 1700 2620 ms
1%
TOSACC External Crystal Oscillator Startup to – 2800 3800 ms The crystal oscillator frequency is
100 ppm within 100 ppm of its final value by the
end of the Tosacc period. Correct
operation assumes a properly loaded
1 uW maximum drive level 32.768 kHz
crystal. 3.0V £ Vdd £ 5.5V, -40 oC £ TA
£ 85 oC.
Jitter32k 32 kHz RMS Period Jitter – 100 ns
TXRST External Reset Pulse Width 10 – – μs
DC24M 24 MHz Duty Cycle 40 50 60 %
DCILO Internal Low Speed Oscillator Duty 20 50 80 %
Cycle
Fout48M 48 MHz Output Frequency 46.8 48.0 49.2[20,22] MHz Trimmed. Utilizing factory trim values.
Jitter24M1 24 MHz RMS Period Jitter (IMO) – 600 ps
FMAX Maximum Frequency of Signal on Row – – 12.3 MHz
Input or Row Output.
TRAMP Supply Ramp Time 0 – – μs

Notes
20. 4.75V < Vdd < 5.25V.
21. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
22. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3V.
23. See the individual user module data sheets for information on maximum frequencies for user modules.

Document Number: 001-48111 Rev. *D Page 47 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Figure 9. PLL Lock Timing Diagram

PLL
Enable
TPLLSLEW 24 MHz

FPLL

PLL
0
Gain

Figure 10. PLL Lock for Low Gain Setting Timing Diagram

PLL
Enable
TPLLSLEWLOW 24 MHz

FPLL

PLL
1
Gain

Figure 11. External Crystal Oscillator Startup Timing Diagram

32K
Select 32 kHz
TOS

F32K2

Figure 12. 24 MHz Period Jitter (IMO) Timing Diagram

Jitter24M1

F 24M

Figure 13. 32 kHz Period Jitter (ECO) Timing Diagram

Jitter32k

F 32K2

Document Number: 001-48111 Rev. *D Page 48 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

AC General Purpose I/O Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 33. AC GPIO Specifications

Symbol Description Min Typ Max Units Notes
FGPIO GPIO Operating Frequency 0 – 12.3 MHz Normal Strong Mode
TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90%
TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90%
TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 10 27 – ns Vdd = 3 to 5.25V, 10% - 90%
TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 10 22 – ns Vdd = 3 to 5.25V, 10% - 90%

Figure 14. GPIO Timing Diagram

90%

GPIO
Pin
Output
Voltage

10%

TRiseF TFallF
TRiseS TFallS

AC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only. The Operational Amplifiers covered by these specifications are components of both the Analog
Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. Settling times, slew rates, and gain bandwidth are based
on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.

Table 34. 5V AC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes
TROA Rising Settling Time from 80% of ΔV to 0.1% of
ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low – – 3.9 μs
Power = Medium, Opamp Bias = High – – 0.72 μs
Power = High, Opamp Bias = High – – 0.62 μs
TSOA Falling Settling Time from 20% of ΔV to 0.1%
of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low – – 5.9 μs
Power = Medium, Opamp Bias = High – – 0.92 μs
Power = High, Opamp Bias = High – – 0.72 μs
SRROA Rising Slew Rate (20% to 80%)(10 pF load,
Unity Gain) 0.15 – – V/μs
Power = Low, Opamp Bias = Low 1.7 – – V/μs
Power = Medium, Opamp Bias = High 6.5 – – V/μs
Power = High, Opamp Bias = High

Document Number: 001-48111 Rev. *D Page 49 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Table 34. 5V AC Operational Amplifier Specifications (continued)

Symbol Description Min Typ Max Units Notes
SRFOA Falling Slew Rate (20% to 80%)(10 pF load,
Unity Gain) 0.01 – – V/μs
Power = Low, Opamp Bias = Low 0.5 – – V/μs
Power = Medium, Opamp Bias = High 4.0 – – V/μs
Power = High, Opamp Bias = High
BWOA Gain Bandwidth Product
Power = Low, Opamp Bias = Low 0.75 – – MHz
Power = Medium, Opamp Bias = High 3.1 – – MHz
Power = High, Opamp Bias = High 5.4 – – MHz
ENOA Noise at 1 kHz – 100 – nV/rt-Hz
Power = Medium, Opamp Bias = High

Table 35. 3.3V AC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes
TROA Rising Settling Time from 80% of ΔV to 0.1% of
ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low – – 3.92 μs
Power = Low, Opamp Bias = High – – 0.72 μs
TSOA Falling Settling Time from 20% of ΔV to 0.1%
of ΔV (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low – – 5.41 μs
Power = Medium, Opamp Bias = High – – 0.72 μs
SRROA Rising Slew Rate (20% to 80%)(10 pF load,
Unity Gain) 0.31 – – V/μs
Power = Low, Opamp Bias = Low 2.7 – – V/μs
Power = Medium, Opamp Bias = High
SRFOA Falling Slew Rate (80% to 20%)(10 pF load,
Unity Gain) 0.24 – – V/μs
Power = Low, Opamp Bias = Low 1.8 – – V/μs
Power = Medium, Opamp Bias = High
BWOA Gain Bandwidth Product
Power = Low, Opamp Bias = Low 0.67 – – MHz
Power = Medium, Opamp Bias = High 2.8 – – MHz
ENOA Noise at 1 kHz – 100 – nV/rt-Hz
Power = Medium, Opamp Bias = High

Document Number: 001-48111 Rev. *D Page 50 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to TBD (TBD dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 15. Typical AGND Noise with P2[4] Bypass

TBD

At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 16. Typical Opamp Noise

TBD

Document Number: 001-48111 Rev. *D Page 51 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

AC Type-E Operational Amplifier Specifications

Table 36 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to
5V, 3.3V, or 2.7V at 25°C and are for design guidance only. The Operational Amplifiers covered by these specifications are components
of the Limited Type E Analog PSoC blocks.

Table 36. AC Type-E Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes
TCOMP Comparator Mode Response Time, 50 mV – 100 ns
Overdrive

AC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.

Table 37. AC Low Power Comparator Specifications

Symbol Description Min Typ Max Units Notes
TRLPC LPC Response Time – – 50 μs ≥ 50 mV overdrive comparator
reference set within VREFLPC.

AC Analog Mux Bus Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 38. AC Analog Mux Bus Specifications

Symbol Description Min Typ Max Units Notes
FSW Switch Rate – – 3.17 MHz

AC Digital Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 39. AC Digital Block Specifications
Function Description Min Typ Max Units Notes
All Maximum Block Clocking Frequency (> 4.75V) – – 49.2 MHz 4.75V < Vdd < 5.25V.
Functions Maximum Block Clocking Frequency (< 4.75V) – – 24.6 MHz 3.0V < Vdd < 4.75V.
Timer Capture Pulse Width 50[24] – – ns
Maximum Frequency, No Capture – – 49.2 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, With Capture – – 24.6 MHz
Counter Enable Pulse Width 50[24] – – ns
Maximum Frequency, No Enable Input – – 49.2 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, Enable Input – – 24.6 MHz
Dead Kill Pulse Width:
Band Asynchronous Restart Mode 20 – – ns
Synchronous Restart Mode 50[24] – – ns
Disable Mode 50[24] – – ns
Maximum Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V.
CRCPRS Maximum Input Clock Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V.
(PRS
Mode)

Document Number: 001-48111 Rev. *D Page 52 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Table 39. AC Digital Block Specifications (continued)

Function Description Min Typ Max Units Notes
CRCPRS Maximum Input Clock Frequency – – 24.6 MHz
(CRC
Mode)
SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz
due to 2 x over clocking.
SPIS Maximum Input Clock Frequency – – 4.1 MHz
Width of SS_ Negated Between Transmissions 50[24] – – ns
Trans- Full Vdd Range – – 24.6 MHz Maximum data rate at 3.16 MHz
mitter due to 8 x over clocking.
Vdd ≥ 4.75V, 2 Stop Bits – – 49.2 MHz Maximum data rate at 6.30 MHz
due to 8 x over clocking.
Receiver Full Vdd Range – – 24.6 MHz Maximum data rate at 3.16 MHz
due to 8 x over clocking.
Vdd ≥ 4.75V, 2 Stop Bits – – 49.2 MHz Maximum data rate at 6.30 MHz
due to 8 x over clocking.

AC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 40. 5V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

TROB Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low – – 2.5 μs
Power = High – – 2.5 μs
TSOB Falling Settling Time to 0.1%, 1V Step, 100 pF
Load – – 2.2 μs
Power = Low – – 2.2 μs
Power = High
SRROB Rising Slew Rate (20% to 80%), 1V Step, 100 pF
Load 0.65 – – V/μs
Power = Low 0.65 – – V/μs
Power = High
SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100 pF
Load 0.65 – – V/μs
Power = Low 0.65 – – V/μs
Power = High
BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF
Load 0.8 – – MHz
Power = Low 0.8 – – MHz
Power = High
BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF
Load 300 – – kHz
Power = Low 300 – – kHz
Power = High

Note
24. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

Document Number: 001-48111 Rev. *D Page 53 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Table 41. 3.3V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

TROB Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low – – 3.8 μs
Power = High – – 3.8 μs
TSOB Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low – – 2.6 μs
Power = High – – 2.6 μs
SRROB Rising Slew Rate (20% to 80%), 1V Step, 100 pF
Load 0.5 – – V/μs
Power = Low 0.5 – – V/μs
Power = High
SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100 pF
Load 0.5 – – V/μs
Power = Low 0.5 – – V/μs
Power = High
BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF
Load 0.7 – – MHz
Power = Low 0.7 – – MHz
Power = High
BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF
Load 200 – – kHz
Power = Low 200 – – kHz
Power = High

AC SAR10 ADC Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 42. AC SAR10 ADC Specifications

Symbol Description Min Typ Max Units Notes

FINSAR10 Input clock frequency for SAR10 ADC – – 2.7 MHz
FSSAR10 Sample rate for SAR10 ADC – – 192.6 ksps For 10-bit resolution, the
SAR10 ADC Resolution = 10 bits sample rate is the ADC's input
clock divided by 14.

AC External Clock Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 43. 5V AC External Clock Specifications

Symbol Description Min Typ Max Units Notes
FOSCEXT Frequency 0.093 – 24.6 MHz
– High Period 20.6 – 5300 ns
– Low Period 20.6 – – ns
– Power Up IMO to Switch 150 – – μs

Document Number: 001-48111 Rev. *D Page 54 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Table 44. 3.3V AC External Clock Specifications

Symbol Description Min Typ Max Units Notes
FOSCEXT Frequency with CPU Clock divide by 1[25] 0.093 – 12.3 MHz
FOSCEXT Frequency with CPU Clock divide by 2 or 0.186 – 24.6 MHz
greater[26]
– High Period with CPU Clock divide by 1 41.7 – 5300 ns
– Low Period with CPU Clock divide by 1 41.7 – – ns
– Power Up IMO to Switch 150 – – μs

AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 45. AC Programming Specifications

Symbol Description Min Typ Max Units Notes

TRSCLK Rise Time of SCLK 1 – 20 ns
TFSCLK Fall Time of SCLK 1 – 20 ns
TSSCLK Data Setup Time to Falling Edge of SCLK 40 – – ns
THSCLK Data Hold Time from Falling Edge of SCLK 40 – – ns
FSCLK Frequency of SCLK 0 – 8 MHz
TERASEB Flash Erase Time (Block) – 40 – ms
TWRITE Flash Block Write Time – 40 – ms
TDSCLK Data Out Delay from Falling Edge of SCLK – – 55 ns Vdd > 3.6
TDSCLK3 Data Out Delay from Falling Edge of SCLK – – 70 ns 3.0 ≤ Vdd ≤ 3.6
TERASEALL Flash Erase Time (Bulk) – 80 – ms Erase all blocks and protection
fields at once.
TPROGRAM_HOT Flash Block Erase + Flash Block Write Time – – 100[27] ms 0°C ≤ Tj ≤ 100°C
TPROGRAM_COLD Flash Block Erase + Flash Block Write Time – – 200[27] ms -40°C ≤ Tj ≤ 0°C

Notes
25. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
26. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent
duty cycle requirement is met.
27. For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note, AN2015 at http://ww.cypress.com under Application Notes for more information.

Document Number: 001-48111 Rev. *D Page 55 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.

Table 46. AC Characteristics of the I2C SDA and SCL Pins

Standard Mode Fast Mode
Symbol Description Units Notes
Min Max Min Max
FSCLI2C SCL Clock Frequency 0 100 0 400 kHz
THDSTAI2C Hold Time (repeated) START Condition. After 4.0 – 0.6 – μs
this period, the first clock pulse is generated.
TLOWI2C LOW Period of the SCL Clock 4.7 – 1.3 – μs
THIGHI2C HIGH Period of the SCL Clock 4.0 – 0.6 – μs
TSUSTAI2C Setup Time for a Repeated START Condition 4.7 – 0.6 – μs
THDDATI2C Data Hold Time 0 – 0 – μs
TSUDATI2C Data Setup Time 250 – 100[28] – ns
TSUSTOI2C Setup Time for STOP Condition 4.0 – 0.6 – μs
TBUFI2C Bus Free Time Between a STOP and START 4.7 – 1.3 – μs
Condition
TSPI2C Pulse Width of spikes are suppressed by the – – 0 50 ns
input filter.

Figure 17. Definition for Timing for Fast/Standard Mode on the I2C Bus

SDA
TLOWI2C TSPI2C
TSUDATI2C THDSTAI2C TBUFI2C

SCL

TSUSTAI2C TSUSTOI2C
S THDSTAI2C THDDATI2C THIGHI2C Sr P S

Note
28. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT Š 250 ns must then be met. This is automatically the case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

Document Number: 001-48111 Rev. *D Page 56 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Packaging Information
This section illustrates the packaging specifications for the CY8C28xxx PSoC devices, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the drawings at http://www.cypress.com/design/MR10161.

Packaging Dimensions
Figure 18. 20-Pin (210-Mil) SSOP

51-85077 *C

Document Number: 001-48111 Rev. *D Page 57 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Figure 19. 28-Pin (210-Mil) SSOP

51-85079*C

Figure 20. 44-Pin TQFP

51-85064 *C

Document Number: 001-48111 Rev. *D Page 58 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Figure 21. 48-Pin (7x7 mm) QFN

001-13191 *C

Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Figure 22. 56-Pin SSOP Package

51-85062 *C

Document Number: 001-48111 Rev. *D Page 59 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Thermal Impedances
Table 47. Thermal Impedances per Package

Package Typical θJA [29]

20 SSOP 80.8 °C/W
28 SSOP 45.4 °C/W
44 TQFP 24.0 °C/W
48 QFN 16.7 °C/W
56 SSOP 67.5 °C/W

Capacitance on Crystal Pins

Table 48. Typical Package Capacitance on Crystal Pins

Package Package Capacitance
20 SSOP Pin9 = 0.0056 pF
Pin11 = 0.006048 pF
28 SSOP Pin13 = 0.006796 pF
Pin15 = 0.006755 pF
44 TQFP Pin16 = 0.009428 pF
Pin18 = 0.008635 pF
48 QFN Pin17 = 0.008493 pF
Pin19 = 0.008742 pF
56 SSOP Pin27 = 0.007916 pF
Pin31 = 0.007132 pF

Solder Reflow Peak Temperature

Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 49. Solder Reflow Peak Temperature

Package Minimum Peak Temperature[30] Maximum Peak Temperature

20 SSOP 245 °C 260 °C
28 SSOP 245 °C 260 °C
44 TQFP 245 °C 260 °C
48 QFN 245 °C 260 °C
56 SSOP 245 °C 260 °C

Notes
29. TJ = TA + POWER x θJA
30. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.

Document Number: 001-48111 Rev. *D Page 60 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Development Tool Selection

This section presents the development tools available for all current PSoC device families including the CY8C28xxx family.

Software
PSoC Designer CY3210-ExpressDK PSoC Express Development Kit
At the core of the PSoC development software suite is PSoC The CY3210-ExpressDK is for advanced prototyping and devel-
Designer. Utilized by thousands of PSoC developers, this robust opment with PSoC Express (may be used with ICE-Cube
software has been facilitating PSoC designs for over half a In-Circuit Emulator). It provides access to I2C buses, voltage
decade. PSoC Designer is available free of charge at reference, switches, upgradeable modules and more. The kit
http://www.cypress.com/psocdesigner. includes:
PSoC Programmer ■ PSoC Express Software CD
Flexible enough to be used on the bench in development, yet ■ Express Development Board
suitable for factory programming, PSoC Programmer works
■ 4 Fan Modules
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is ■ 2 Proto Modules
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC Programmer is available free of charge ■ MiniProg In-System Serial Programmer
at http://www.cypress.com/psocprogrammer. ■ MiniEval PCB Evaluation Board
PSoC C Compilers ■ Jumper Wire Kit
CY3202 is the optional upgrade to PSoC Designer that enables ■ USB 2.0 Cable
the iMAGEcraft C compiler. It can be purchased from the
Cypress Online Store. At http://www.cypress.com, click the ■ Serial Cable (DB9)
Online Store shopping cart icon at the bottom of the web page,
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
and click PSoC (Programmable System-on-Chip) to view a
current list of available items. ■ 2 CY8C24423A-24PXI 28-PDIP Chip Samples
Development Kits ■ 2 CY8C27443-24PXI 28-PDIP Chip Samples
All development kits can be purchased from the Cypress Online ■ 2 CY8C29466-24PXI 28-PDIP Chip Samples
Store.
Evaluation Tools
CY3215-DK Basic Development Kit
All evaluation tools can be purchased from the Cypress Online
The CY3215-DK is for prototyping and development with PSoC Store.
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor CY3210-MiniProg1
and view the content of specific memory locations. Advanced The CY3210-MiniProg1 kit allows a user to program PSoC
emulation features are supported in PSoC Designer. The kit devices via the MiniProg1 programming unit. The MiniProg is a
includes: small, compact prototyping programmer that connects to the PC
■ PSoC Designer Software CD via a provided USB 2.0 cable. The kit includes:

■ ICE-Cube In-Circuit Emulator ■ MiniProg Programming Unit

■ Pod kit for CY8C29x66 PSoC Family ■ MiniEval Socket Programming and Evaluation Board

■ Cat-5 Adapter ■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample

■ Mini-Eval Programming Board ■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample

■ 110 ~ 240V Power Supply, Euro-Plug Adapter ■ PSoC Designer Software CD

■ ISSP Cable ■ Getting Started Guide

■ USB 2.0 Cable and Blue Cat-5 Cable ■ USB 2.0 Cable

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

Document Number: 001-48111 Rev. *D Page 61 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

CY3210-PSoCEval1 Device Programmers

The CY3210-PSoCEval1 kit features an evaluation board and All device programmers can be purchased from the Cypress
the MiniProg1 programming unit. The evaluation board includes Online Store.
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit CY3207ISSP In-System Serial Programmer (ISSP)
includes: The CY3207ISSP is a production programmer. It includes
■ Evaluation Board with LCD Module protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
■ MiniProg Programming Unit
Note: The CY3207ISSP programmer needs the PSoC ISSP
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) software. It is not compatible with the PSoC Programmer
software. The latest PSoC ISSP software for this kit can be
■ PSoC Designer Software CD downloaded from http://www.cypress.com. The kit includes:
■ Getting Started Guide ■ CY3207 Programmer Unit
■ USB 2.0 Cable ■ PSoC ISSP Software CD
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ USB 2.0 Cable

Accessories (Emulation and Programming)

Table 50. Emulation and Programming Accessories

Part # Pin Package Pod Kit[31] Foot Kit[32] Adapter[33]
CY8C28243-24PVXI 20 SSOP CY3250-28XXX CY3250-20SSOP-FK
CY8C28403-24PVXI 28 SSOP CY3250-28XXX CY3250-28SSOP-FK
CY8C28413-24PVXI
CY8C28433-24PVXI
CY8C28445-24PVXI
CY8C28452-24PVXI Adapters can be found at
http://www.emulation.com.
CY8C28513-24AXI 44 TQFP CY3250-28XXX CY3250-44TQFP-FK
CY8C28533-24AXI
CY8C28545-24AXI
CY8C28623-24LTXI 48 QFN CY3250-28XXXQFN CY3250-48QFN-FK
CY8C28643-24LTXI
CY8C28645-24LTXI

3rd-Party Tools Build a PSoC Emulator into Your Board

Several tools have been specially designed by the following For details on how to emulate your circuit before going to volume
3rd-party vendors to accompany PSoC devices during devel- production using an on-chip debug (OCD) non-production PSoC
opment and production. Specific details for each of these tools device, see Application Note “Debugging - Build a PSoC
can be found at http://www.cypress.com under DESIGN Emulator into Your Board - AN2323” at
RESOURCES >> Evaluation Boards. http://www.cypress.com/an2323.

Notes
31. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples.
32. Foot kit includes surface mount feet that can be soldered to the target PCB.
33. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.

Document Number: 001-48111 Rev. *D Page 62 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Ordering Information
The following table lists the CY8C28xxx PSoC devices key package features and ordering codes.

Regular Analog Blocks

Limited Analog Blocks

Temperature Range

10-bit SAR ADC

Analog Outputs
Digital I/O Pins
Ordering Code

Flash (KBytes)

RAM (KBytes)
Analog Inputs
Digital Blocks

Decimators
CapSense

XRES Pin
Package

HW I2C
28-Pin (210 Mil) SSOP CY8C28403-24PVXI -40 to 85 N 12 0 0 2 0 Y 24 8 0 16 1 Y

28-Pin (210 Mil) SSOP CY8C28403-24PVXIT -40 to 85 N 12 0 0 2 0 Y 24 8 0 16 1 Y

(Tape and Reel)

28-Pin (210 Mil) SSOP CY8C28413-24PVXI -40 to 85 Y 12 0 4 1 2 Y 24 24 0 16 1 Y

28-Pin (210 Mil) SSOP CY8C28413-24PVXIT -40 to 85 Y 12 0 4 1 2 Y 24 24 0 16 1 Y

(Tape and Reel)

44-Pin TQFP CY8C28513-24AXI -40 to 85 Y 12 0 4 1 2 Y 40 40 0 16 1 Y

44-Pin TQFP (Tape CY8C28513-24AXIT -40 to 85 Y 12 0 4 1 2 Y 40 40 0 16 1 Y

and Reel)

48-Pin Sawn QFN CY8C28623-24LTXI -40 to 85 N 12 6 0 2 2 N 44 10 2 16 1 Y

48-Pin Sawn QFN CY8C28623-24LTXIT -40 to 85 N 12 6 0 2 2 N 44 10 2 16 1 Y

(Tape and Reel)

28-Pin (210 Mil) SSOP CY8C28433-24PVXI -40 to 85 Y 12 6 4 1 4 Y 24 24 2 16 1 Y

28-Pin (210 Mil) SSOP CY8C28433-24PVXIT -40 to 85 Y 12 6 4 1 4 Y 24 24 2 16 1 Y

(Tape and Reel)

44-Pin TQFP CY8C28533-24AXI -40 to 85 Y 12 6 4 1 4 Y 40 40 2 16 1 Y

44-Pin TQFP (Tape CY8C28533-24AXIT -40 to 85 Y 12 6 4 1 4 Y 40 40 2 16 1 Y

and Reel)

20-Pin (210 Mil) SSOP CY8C28243-24PVXI -40 to 85 N 12 12 0 2 4 Y 16 16 4 16 1 Y

20-Pin (210 Mil) SSOP CY8C28243-24PVXIT -40 to 85 N 12 12 0 2 4 Y 16 16 4 16 1 Y

(Tape and Reel)

48-Pin Sawn QFN CY8C28643-24LTXI -40 to 85 N 12 12 0 2 4 Y 44 44 4 16 1 Y

48-Pin Sawn QFN CY8C28643-24LTXIT -40 to 85 N 12 12 0 2 4 Y 44 44 4 16 1 Y

(Tape and Reel)

28-Pin (210 Mil) SSOP CY8C28445-24PVXI -40 to 85 Y 12 12 4 2 4 Y 24 24 4 16 1 Y

28-Pin (210 Mil) SSOP CY8C28445-24PVXIT -40 to 85 Y 12 12 4 2 4 Y 24 24 4 16 1 Y

(Tape and Reel)

44-Pin TQFP CY8C28545-24AXI -40 to 85 Y 12 12 4 2 4 Y 40 40 4 16 1 Y

Document Number: 001-48111 Rev. *D Page 63 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Regular Analog Blocks

Limited Analog Blocks

Temperature Range

10-bit SAR ADC

Analog Outputs
Digital I/O Pins
Ordering Code

Flash (KBytes)

RAM (KBytes)
Analog Inputs
Digital Blocks

Decimators
CapSense

XRES Pin
Package

HW I2C
44-Pin TQFP (Tape CY8C28545-24AXIT -40 to 85 Y 12 12 4 2 4 Y 40 40 4 16 1 Y
and Reel)

48-Pin Sawn QFN CY8C28645-24LTXI -40 to 85 Y 12 12 4 2 4 Y 44 44 4 16 1 Y

48-Pin Sawn QFN CY8C28645-24LTXIT -40 to 85 Y 12 12 4 2 4 Y 44 44 4 16 1 Y

(Tape and Reel)

28-Pin (210 Mil) SSOP CY8C28452-24PVXI -40 to 85 Y 8 12 4 1 4 N 24 24 4 16 1 Y

28-Pin (210 Mil) SSOP CY8C28452-24PVXIT -40 to 85 Y 8 12 4 1 4 N 24 24 4 16 1 Y

(Tape and Reel)

56-Pin SSOP OCD CY8C28000-24PVXI -40 to 85 Y 12 12 4 2 4 Y 44 44 4 16 1 Y

Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).

Ordering Code Definitions

CY 8 C 28 xxx - SP xxxx

Package Type: Thermal Rating:

PX = PDIP Pb-free C = Commercial
SX = SOIC Pb-free I = Industrial
PVX = SSOP Pb-free E = Extended
LTX/LFX/LKX = QFN Pb-free
AX = TQFP Pb-free
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress

Document Number: 001-48111 Rev. *D Page 64 of 65

[+] Feedback
 PRELIMINARY
CY8C28xxx

Document History Page

Document Title: CY8C28243, CY8C28403, CY8C28413, CY8C28433, CY8C28445, CY8C28452, CY8C28513, CY8C28533,
CY8C28545, CY8C28623, CY8C28643, CY8C28645 PSoC® Programmable System-on-Chip
Document Number: 001-48111
Origin of Submission
Revision ECN No. Description of Change
Change Date
** 2593460 BTK/PYRS 10/20/08 New document (Revision **).
*A 2652217 BTK/PYRS 02/02/09 Extensive updates to content.
Added registers maps.
Updated Getting Started section
Updated Development Tools section
Added some SAR10 ADC specifications.
Added more analog system figures
*B 2675937 BTK 03/18/09 Updated DC Analog Reference Specifications tables
Minor content updates
*C 2679015 HMI 03/26/2009 Post to external web.
*D 2750217 TDU 08/10/09 Updates to Electrical Specificatons section
Minor content updates

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at www.cypress.com/sales.

Products
PSoC psoc.cypress.com
Clocks & Buffers clocks.cypress.com
Wireless wireless.cypress.com
Memories memory.cypress.com
Image Sensors image.cypress.com

© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-48111 Rev. *D Revised August 10, 2009 Page 65 of 65

PSoC Designer™ is a trademark and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective
corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C
system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their
respective holders.

[+] Feedback