ELEC 2607 Lab4 Updated 2024

Carleton University
Department of Electronics
ELEC 2607 Switching Circuits Fall 2024
Laboratory 4: Seven Segment Display

Introduction
A 7-segment display consists of seven segments, numbered a to g, which can be used to display
a character. Depending on the input type, a type conversion may be needed. If you want to
display a binary coded decimal (BCD) using 4-bit input, a BCD to 7-segment decoder is required.
Each of the eight digits is composed of seven segments arranged in a “figure 8” pattern (see Fig.
1), with an LED embedded in each segment. Segment LEDs can be individually illuminated, so
any one of 128 patterns can be displayed on a digit by illuminating certain LED segments and
leaving the others dark. Of these 128 possible patterns, the ten corresponding to the decimal
digits are the most useful.
Figure 1 - Seven-segment digit.
Objective
The objective in this lab is to create a 4-digit counter. An initial value can be passed with the 16
switches on the board. These 16 switches will correspond to 4 binary-coded decimal (BCD)
values. For simplicity, the displayed numbers will be in hexadecimal, in order to allow for all
possible combinations. A ‘load’ button will accept the initial value given by the switches and
display it on the seven-segment LEDs. Prior to the load button being pushed, the LEDs should
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ELEC 2607 – Lab 4 Switching Circuits Fall 2024
display an initial value of ‘000’. A ‘count-up’ button can be pushed to increase the value by 1
and a ‘count-down’ button can be pushed to decrease the value by 1. A reset button can be
pushed to reset the display to all 0s.
Pre-Lab
1. Based on Figure 1, create a table that takes a 4-bit BCD value as an input, and shows
which of the seven-segment LEDs (A-G) need to be asserted in order for the BCD value
to be properly displayed. NOTE: The board uses active-low as assertion. For example,
digit 8 needs all seven-segments to be turned on. This corresponds to all seven-
segment LEDs (A-G) to have a value of 0.
2. Complete the Verilog code for the binary to seven-segment converter.
3. Create a timing diagram that illustrates how the switch input values are captured by the
four 4-bit registers when pushing the ‘load’ button and the ‘reset’ button.
4. Similar to the previous timing diagram, show how the ‘count-up’ or ‘count-down’
buttons alter the four 4-bit data registers, demonstrating propagation between
registers.
5. Using the provided Verilog code for the seven-segment controller, create a simple
timing diagram that demonstrates how the following signals and registers interact to
refresh and light-up the seven segment LEDs: CLK100MHZ, segment_counter,
segment_state, routed_vals. If need be, you may assume your own initial values for
registers.
6. Write a pseudo-code module that implements the overall system and interconnects as
shown in Fig. 4. To achieve this, you may choose to instantiate the 4-bit registers or
declare them as part of the seven-segment controller. If they are instantiated, the
contents of these modules do not need to be shown in this question.
Department of Electronics Mackenzie Building 5170 Tel: 613-520-5755 Fax: 613- 2

Faculty of Engineering and 1125 Colonel By Drive, 520-5708
info@doe.carleton.ca
https://carleton.ca/doe/
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Seven-segment Display
The Nexys A7 board contains two four-digit common anode seven-segment LED displays,
configured to behave like a single eight-digit display. The anodes of the seven LEDs forming
each digit are tied together into one “common anode” circuit node, but the LED cathodes
remain separate, as shown in Fig 2. The common anode signals are available as eight “digit
enable” input signals to the 8-digit display. The cathodes of similar segments on all four displays
are connected into seven circuit nodes labeled CA through CG. For example, the eight “D”
cathodes from the eight digits are grouped together into a single circuit node called “CD.”
These seven cathode signals are available as inputs to the 8-digit display. This signal connection
scheme creates a multiplexed display, where the cathode signals are common to all digits, but
they can only illuminate the segments of the digit whose corresponding anode signal is
asserted. To illuminate a segment, the anode should be driven high while the cathode is driven
Figure 2 - Common Anode Circuit
low. However, since the Nexys A7 uses transistors to drive enough current into the common
anode point, the anode enables are inverted. Therefore, both the AN0...7 and the CA..G/DP
signals are driven low when active.
A scanning display controller circuit can be used to show an eight-digit number on this display.
This circuit drives the anode signals and corresponding cathode patterns of each digit in a
repeating, continuous succession at an update rate that is faster than the human eye can
detect. Each digit is illuminated just one-eighth of the time, but because the eye cannot
perceive the darkening of a digit before it is illuminated again, the digit appears continuously

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illuminated. If the update, or “refresh”, rate is slowed to around 45Hz, a flicker can be noticed
in the display.
For each of the four digits to appear bright and continuously illuminated, all eight digits should
be driven once every 1 to 16ms, for a refresh frequency of about 1 KHz to 60Hz. For example, in
a 62.5Hz refresh scheme, the entire display would be refreshed once every 16ms, and each digit
would be illuminated for 1/8 of the refresh cycle, or 2ms. The controller must drive low the
cathodes with the correct pattern when the corresponding anode signal is driven high. To
Figure 3 - Four Digit Scanning Display Controller Timing Diagram
illustrate the process, if AN0 is asserted while CB and CC are asserted, then a “1” will be
displayed in digit position 1. Then, if AN1 is asserted while CA, CB, and CC are asserted, a “7”
will be displayed in digit position 2. If AN0, CB, and CC are driven for 4ms, and then AN1, CA, CB,
and CC are driven for 4ms in an endless succession, the display will show “71” in the first two
digits. An example timing diagram for a four-digit controller is shown in Figure 3.
System Overview
An overview of the system can be seen in Fig. 4. Although not complete, count-down and reset
here are not shown, a good idea of the system can be appreciated. The 4 BCD values will take
the 16 switch values, and these will be stored internally only when the ‘load’ button has been
pushed. It can be thought of as D Flip-Flop that is triggered by the button push. This 16-bit value

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Figure 4 - System Overview
is partitioned into four 4-bit values, that will be used as the input to the seven-segment
controller. This control unit generates the needed cathode and anode signals that will display
the digits.
When the count-up or count-down buttons are pushed, the register containing the 4 least
significant bits is increased or decreased by 1, respectively. The system should consider when
this register overflows, that the signal is propagated throughout as required to the other
registers.
When a reset button is pushed, these 4 registers should be reset to 0.
Seven Segment Controller

The code for the seven-segment controller will be mostly provided, but ensure you understand
how it works in order to be able to implement the rest of the system. In order to refresh to
lights once every 1-16ms as explained in an earlier section, the 100MHz clock is used. Every
100,000 clock cycles a new light is displayed. Thus, for 4 seven-segment LEDs this corresponds
to a refresh rate of once every 4ms.

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Binary to Seven Segment Controller

As you have noticed in the previous code, the seven-segment controller instantiates a copy of a
module named ‘binary_2_seven_seg’. The code for this module is provided below but needs
completion.
General Procedure Suggestions

It is highly advised that a testbench is created for a module while it is developed. For this you
may create a test bench for the top module, or various smaller test benches for sub-modules.
Although this may seem time consuming, it is almost always faster to modify the design and
testbenches from simulation results than awaiting to see the errors the synthesis →
implementation → bitstream process generates.
It is always highly suggested that you try to implement one feature or operation at a time, to
allow for easier debug of any possible mistakes. For any new feature you should have specific

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input test vectors and know what the expected outputs to be, in order to compare them with
simulation/experimental results.
Push-Button Bouncing – What is it and how to approach this issue?

When an input button, or switch, is pressed two metal contacts come together. To the user this
seems to be an instantaneous state change, but that is not quite correct. As this involves
moving parts, these two terminals make an initial contact momentarily, come apart, make
contact again, and this process is repeated until the connection is fully closed. This is where the
term bouncing comes from. This is illustrated in Fig. 5. If this process is not considered, and
since most modern embedded hardware operates faster than the bouncing, the system may
interpret this as if the button or switch has been pressed several times.
Figure 5 - Button/Switch bouncing and two approaches to handle the state change.
There are many methods to handle this problem. You may find solutions including an S-R latch,
RC filter, Schmidt Trigger inverter, but we can also make use of a synchronizer module and the
internal 100MHz clock unit.
The push-button signal will contain glitches as discussed before and is asynchronous to any
clock signal in the system. For this reason, it may be mostly unusable as is. By synchronizing the
unstable push-button signal (PB), with the internal clock (Clk), three glitch-free outputs can be
produced: push-button state, push-button down, push-button up. A block diagram for this
module is shown in Fig. 6.

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Figure 6 - Synchronizer module.
The Verilog code for this synchronizer module is given below. Note: how long you should
assume the button may bounce would require extensive testing to assert with high confidence.
Thus, the size of PB_cnt may need to be modified accordingly.

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Bonus Question
An additional 25% bonus will be given to students that are able to implement the system such
that the counter only uses decimal numbers (0-9) and not hexadecimal numbers (0-F). In the
case of increase by 1, the least significant digit should increase from 0 to 9, and then this digit
should then be reset to 0, while incrementing the next significant digit by 1. Similar
implementation for the counting down operation. Note that no help will be provided to
implement this modification.


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Carleton University

ELEC 2607 Switching Circuits Fall 2024

Laboratory 4: Seven Segment Display

Figure 1 - Seven-segment digit.

Department of Electronics Mackenzie Building 5170 Tel: 613-520-5755 Fax: 613- 2

Figure 2 - Common Anode Circuit

Department of Electronics Mackenzie Building 5170 Tel: 613-520-5755 Fax: 613- 3

Figure 3 - Four Digit Scanning Display Controller Timing Diagram

Department of Electronics Mackenzie Building 5170 Tel: 613-520-5755 Fax: 613- 4

Figure 4 - System Overview

When a reset button is pushed, these 4 registers should be reset to 0.

Seven Segment Controller

Department of Electronics Mackenzie Building 5170 Tel: 613-520-5755 Fax: 613- 5

Department of Electronics Mackenzie Building 5170 Tel: 613-520-5755 Fax: 613- 6

Department of Electronics Mackenzie Building 5170 Tel: 613-520-5755 Fax: 613- 7

Binary to Seven Segment Controller

General Procedure Suggestions

Department of Electronics Mackenzie Building 5170 Tel: 613-520-5755 Fax: 613- 8

Push-Button Bouncing – What is it and how to approach this issue?

Department of Electronics Mackenzie Building 5170 Tel: 613-520-5755 Fax: 613- 9

Figure 6 - Synchronizer module.

Department of Electronics Mackenzie Building 5170 Tel: 613-520-5755 Fax: 613- 10

Department of Electronics Mackenzie Building 5170 Tel: 613-520-5755 Fax: 613- 11

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