DSD Da 2

DIGITAL SYSTEMS AND DESIGN
DIGITAL ASSIGNMENT 2
NAME: VAIBHAV GULATI

REGISTRATION NUMBER: 23BCE2053
[Question I]
AIM:
Write a code in Verilog model and verify using testbench for:
(i)Half adder
(ii)Half Sub-tractor
Material Required:
Text Editor or IDE:, Verilog simulator
Theory:
A half adder is a fundamental combinational circuit in digital electronics that performs the
addition of two single-bit binary numbers. It has two inputs, A and B, and produces two
outputs: Sum and Carry. The Sum output is the result of the XOR operation between the
inputs, while the Carry output is the result of the AND operation. This simple circuit is
essential for constructing more complex adders, such as full adders, which can handle multi-
bit binary numbers.
On the other hand, a half subtractor is a combinational circuit designed to perform the
subtraction of two single-bit binary numbers. It also has two inputs, A and B, and produces
two outputs: Difference and Borrow. The Difference output is obtained using the XOR
operation, similar to the Sum in a half adder, while the Borrow output is derived from the
AND operation of the inverted A input and B input. The half subtractor is a basic building
block for more complex subtractors, enabling the subtraction of larger binary numbers by
cascading multiple half subtractors.
Both the half adder and half subtractor are crucial in digital systems for performing basic
arithmetic operations, serving as the foundation for more advanced arithmetic circuits
Procedure:
1. Define the Module:
Every Verilog code starts with a module declaration. This includes the module name and
its input/output ports.
2. Declare Inputs and Outputs:
Specify the direction (input, output, or inout) and size of each port.
3. Declare Internal Signals:
• Define any internal wires or registers needed for the module.
4. Describe the Functionality:
Use one of the modeling techniques (Gate Level, Data Flow, or Behavioral) to describe
the logic.
5.End the Module:
Close the module with the endmodule keyword.
(I)Half Adder
Verilog Code:
Testbench Code:
Output:
Truth Table and Logic Circuit:
(II)Half Sub tractor:
Verilog Code:
Testbench:
Output:
Logic Circuit and Truth Table:
[Question 2]
AIM:
Design and Verify using testbench:
(i)1 bit Full adder
(ii)1 bit Full Sub-tractor
Material Required:
Theory:
A 1-bit full subtractor performs subtraction of two single-bit binary numbers, considering a
borrow-in bit. The output includes a difference bit and a borrow-out bit. The operation can
be expressed using the following formulas:
• Difference: Difference = A XOR B XOR Borrow-in
• Borrow-out: Borrow-out = (A AND B) OR (A AND Borrow-in) OR (B AND Borrow-in)
A 1-bit full adder performs addition of two single-bit binary numbers, considering a carry-in
bit. The output includes a sum bit and a carry-out bit. The operation can be expressed using
the following formulas:
• Sum: Sum = A XOR B XOR Carry-in
• Carry-out: Carry-out = (A AND B) OR (A AND Carry-in) OR (B AND Carry-in)
Procedure:
the logic.
5.End the Module:
Close the module with the endmodule keyword.
(II)1 Bit Full Adder:

Verilog Code:
Testbench:
Output:
Truth Table and Logic Circuit:
(II)1 Bit Full Sub Tractor:

Verilog Code:
TestBench:
Output:
Logic Circuit and Truth Table:
[Question III]
AIM:
Write a code in Verilog model and verify using testbench for:
(i)4 Bit Full Adder
(ii)4 Bit Full Sub-tractor
Material Required:
Theory:
A 4-bit full adder is a digital circuit that performs binary addition on two 4-bit numbers. It is
constructed using four 1-bit full adders connected in series. Each 1-bit full adder adds two
corresponding bits from the input numbers along with a carry bit from the previous stage.
The output consists of a 4-bit sum and a carry-out bit.
Similarly, a 4-bit full subtractor performs binary subtraction using four 1-bit full subtractors.
Each 1-bit full subtractor subtracts two bits, taking into account a borrow bit from the
previous stage. The result includes a 4-bit difference and a final borrow-out bit.
Procedure:
the logic.
5.End the Module:
Close the module with the endmodule keyword
Verilog Code(4 Bit Sub-tractor)

Testbench:
Output:
Logic Circuit:
4 Bit Full Adder:
Verilog code:
Test Bench:
Output:
Logic circuit:

DSD Da 2

Uploaded by

Copyright:

Available Formats

DSD Da 2

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

DSD Da 2

Uploaded by

Copyright:

Available Formats

DIGITAL SYSTEMS AND DESIGN

NAME: VAIBHAV GULATI

2. Declare Inputs and Outputs:

3. Declare Internal Signals:

• Define any internal wires or registers needed for the module.

4. Describe the Functionality:

5.End the Module:

Close the module with the endmodule keyword.

(i)1 bit Full adder

(ii)1 bit Full Sub-tractor

• Difference: Difference = A XOR B XOR Borrow-in

• Borrow-out: Borrow-out = (A AND B) OR (A AND Borrow-in) OR (B AND Borrow-in)

• Sum: Sum = A XOR B XOR Carry-in

• Carry-out: Carry-out = (A AND B) OR (A AND Carry-in) OR (B AND Carry-in)

2. Declare Inputs and Outputs:

3. Declare Internal Signals:

• Define any internal wires or registers needed for the module.

4. Describe the Functionality:

5.End the Module:

Close the module with the endmodule keyword.

(II)1 Bit Full Adder:

(II)1 Bit Full Sub Tractor:

(i)4 Bit Full Adder

(ii)4 Bit Full Sub-tractor

2. Declare Inputs and Outputs:

3. Declare Internal Signals:

• Define any internal wires or registers needed for the module.

4. Describe the Functionality:

5.End the Module:

Close the module with the endmodule keyword

Verilog Code(4 Bit Sub-tractor)

4 Bit Full Adder:

You might also like

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.