Kareem W

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Digital Design & Verification Diploma

Why this diploma?


1. Students previously enrolled in the diploma and graduated were technically more ready
for the market as per the industry’s feedback here
2. The instructor has ten years of teaching experience in addition to seven years of industry
experience that will be shared with the students.
3. The diploma adds the following to your CV
• Solid Knowledge of Siemens EDA simulation tool: QuestaSim
1. Basic simulation usage
2. Code Coverage
3. Functional Coverage
4. SystemVerilog Assertions
• Solid Knowledge in Digital/RTL Design Basics
• Solid Knowledge of Hardware Description Languages: Verilog & SystemVerilog
• Solid Knowledge of UVM based verification methodology
• Knowledge of one of the most used communication protocols (Diploma Project)
• Solid Knowledge of Testing Strategies, Test Planning and Testing Automation
• Solid Knowledge in assertion-based verification and functional coverage
• Knowledge in Clock Domain Crossing techniques & Low power design
implementations
• Knowledge in Formal Verification - Static Linting, Formal Property Checking &
Equivalence Checking
• Knowledge of FPGA design flow and architecture
• Knowledge of Vivado design flow
4. Learn what really matters in terms of basics and language constructs required to get
ready for the digital domain market.
5. Learn about the different job opportunities available in the digital industry market and
the role of each title to give the students a more robust idea of what to expect after
graduation.
6. Learn about the latest trends around the world in the design and verification industry.
Who is this diploma for?
1. Students in Communications/Electronics Engineering
2. Students in Computer/Software Engineering

Instructor
1. Basic Information & Education
• Name: Kareem Waseem
• Computer and System Engineering Master of Science - Ain Shams Uni
• Electronics and Communications Engineering Bachelor - Ain Shams Uni
▪ Ranked 1st
• Linkedin account: here, Facebook group: here

2. Work Experience
• Digital Verification Team Lead at Si-Vision, March 2024 - Present
• Staff Verification Engineer (Acting as team leader) at Si-Vision, March 2023 – March
2024
• Senior Hardware Modeling Engineer at Siemens EDA, June 2022 – March 2023
• Hardware Modeling Engineer at Siemens EDA, December 2017 – June 2022
3. Teaching Experience
• Si-Vision Academy instructor – 2023 & 2024
▪ SystemVerilog language basics & SystemVerilog Assertions
• Siemens EDA Diploma instructor – 2023
▪ Verilog HDL
▪ FPGA Design Concepts
▪ Verification using UVM
• Teacher Assistant for the Electronic Design Automation (EDA) course (Ain Shams
University) - Fall 2023
• Teacher Assistant for the Digital Verification elective course (Ain Shams University)
- Spring 2023
• Teacher Assistant for ASIC Design & Automation elective course (Ain Shams
University) - Fall 2022 & Fall 2023
• Lecturer and Teacher Assistant for the Digital Verification elective course (Ain
Shams University) - Spring 2021
DIGITAL DESIGN USING VERILOG AND FPGA FLOW USING
VIVADO
Topics Covered
1. Classical Digital Design flow – Truth tables/K-maps/Boolean Algebra/Logic Equivalence
2. History of HDLs & Intro to Verilog/Verilog Constructs [Modern Digital Design flow]
3. Combinational Logic basics & Verilog Essentials to model Combinational Logic circuits
4. Most Important Combinational Logic circuits & how to design them in Verilog
5. Verification using Verilog & testbench generation
6. Sequential circuits basics & Verilog essentials to model sequential circuits
7. Most important sequential circuits & how to design them in Verilog
8. Finite State Machine (FSM) basics/types & how to design them in Verilog
9. Memories basics/types & Verilog essentials to model memories
10. Most Important memory types & how to design them in Verilog
11. Verilog synthesis constructs
12. Tcl commands to automate QuestaSim simulation flow
13. Synthesis & Static Timing Analysis (STA)
14. Static Linting Checks & Clock Domain Crossing (CDC) techniques
15. Low power design implementations using clock gating
16. FPGA design flow & architecture basics
17. Vivado design flow using Basys 3 FPGA Board
18. Timing and physical design constraints
19. Integrate IP cores into design flow using IP Catalog
20. FPGA-based Prototyping & Partitioning Challenges
21. Course Project (mini project and final project)

Pre-requisite
1. Digital Logic Basics

Fees & Course duration


1. Course fees for students or unemployed: 3500 LE.
2. Course fees for employed graduates: 4500 LE.
3. Course fees include center fees, hard copy notes and certificate “Softcopy and hardcopy”
4. Course duration: 6 weeks (36 hours)
▪ Please note that the course duration may extend in case of emergency causing a
week to be cancelled during the course.
5. Course starts on Jan 25th, 2025
▪ One class per week (on Friday)
▪ The course will begin on Saturday (January 25th) rather than Friday (January 24th)
as an exception since some students have a final exam on January 24th.
6. Groups:
▪ Group 1 (available)
i. Friday 8 am – 12 pm (4 hours) then 1 hour break (Jumu’ah prayers) then (1 pm –
3 pm) (2 hours)
▪ Group 2 (available)
i. Friday 3 pm to 9 pm
▪ If the number of students can be merged into a single group, then the session will
take place 2 hours before Jummah prayers and resume for 4 hours afterward.
i. This will be decided after the deadline according to the number of
students

Reservation Rules
• Deadline for payment: Jan 20th, 2025
DIGITAL VERIFICATION USING SYSTEMVERILOG AND UVM
Topics Covered
1. Verification Trends, Planning & Latest Findings
2. SystemVerilog Data Types & Subroutines
3. Code Coverage
4. SystemVerilog Interfaces
5. SystemVerilog Assertions & Threads
6. SystemVerilog Scheduling Semantics
7. Basics of Object-Oriented Programming
8. Constrained Random Value Generation
9. Functional Coverage
10. UVM Structure overview
11. UVM Components and Phases
12. UVM Component Communication
13. UVM Sequence & Sequence item
14. UVM Configuration & Factory
15. Introduction to formal Verification using formal property checking & equivalence
checking
16. Introduction to hardware-assisted verification platforms (FPGA-based prototyping &
Emulators)
17. Course Project (SystemVerilog Project and UVM Project)

Pre-requisite
1. Verilog with basic understanding of designing and verifying a digital circuit.
2. Engineers with no Verilog knowledge are advised to enroll in the “Digital design using
Verilog and FPGA flow using Vivado” mentioned in the beginning of this document.

Note: You are not required to have object-oriented programming background.

Note: The verification course timeline might be extended due to the second semester midterm
exams and Eid al-Fitr vacations.
Fees & Course duration
1. Course fees for students or unemployed: 3500 LE.
2. Course fees for employed graduates: 4500 LE.
3. Course fees include center fees, hard copy notes and certificate “Softcopy and hardcopy”
4. Course duration: 7 weeks (42 hours)
▪ Please note that the course duration may extend in case of emergency causing a
week to be cancelled during the course.
5. Course starts on Feb 28th, 2025
▪ One class per week (on Friday)
6. Groups:
▪ Group 1 (available)
i. Friday 8 am – 12 pm (4 hours) then 1 hour break (Jumu’ah prayers) then
(1 pm – 3 pm) (2 hours)
▪ Group 2 (available)
i. Friday 3 pm to 9 pm
▪ If the number of students can be merged into a single group, then the session will
take place 2 hours before Jummah prayers and resume for 4 hours afterward.
i. This will be decided after the deadline according to the number of
students

Reservation Rules
• Deadline for payment: Jan 20th, 2025

GENERAL & COMMON LOGISTICS


1. You must Fill in this Google form (ignore if you have filled it).
• You will be contacted via the email you provided once submitting the form to complete
the payment.
• There are limited spots available for the diploma. Once these spots are filled, you will
receive another email informing you that you've been added to the waiting list.
2. Location
• VIP center
• ‫ر‬
‫ مدينة نص‬- ‫ بجوار ماكدونالدز‬- ‫ الدور األول‬- 1 ‫ مدخل‬- 1 ‫برج‬- ‫ الرساج مول‬:‫السنت‬ ‫عنوان‬
• Google Maps link here
3. Each Class will have the following
• Discuss real Interview Question/s from the industry to be better aware of the
questions/topics that the industry focuses on (Mostly from Interviews done in Egyptian
Companies)
• Labs to encourage on-time application of the topic.
• Assignment to be submitted.

DIPLOMA OFFER & GENERAL RULES


Diploma Offer
• Enroll in the two courses mentioned above as one diploma for 6000LE and save 1000LE,
as opposed to paying 3500 for the two courses separately.
• Diploma offer is for students or unemployed
• Deadline for diploma offer payment: Jan 20th, 2025

General Rules
1. Fees are 100% refundable until the fees deadline date
2. Fees are 90% refundable after the fees deadline and before the course starts
3. Fees are not refundable once the course starts
4. You cannot take just one course after paying for the diploma offer mentioned above.
5. In case you enrolled in the diploma offer you will attend the two courses right after each
other. You cannot postpone and attend the second course in later diplomas.
6. In case of missing a session, it is totally acceptable to attend it in the following diplomas.

Do not hesitate to contact me if you have any questions. Mobile number: 01009279775

Instructor: Kareem Waseem, LinkedIn link, Facebook group link Best of luck to you all ❤❤

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