ARM Processors

Dr. Sonali Chouhan

Embedded Systems EE312

© Sonali Chouhan 1
Outline
Introduction
ARM Instruction Set
ARM Registers
ARM Operating Modes
ARM Exception Handling

© Sonali Chouhan 2
ARM Processors

© Sonali Chouhan 3
ARM – What is it?
ARM stands for Advanced RISC Machines
An ARM processor is basically any 16/32bit
microprocessor designed and licensed by
ARM Ltd, a microprocessor design company
headquartered in England, founded in 1990
by Herman Hauser
A characteristic feature of ARM processors
is their low electric power consumption,
which makes them particularly suitable for
use in portable devices.
It is one of the most used processors
currently on the market

© Sonali Chouhan 4
Examples of ARM Based
Products

© Sonali Chouhan 5
ARM Architecture
RISC features incorporated by ARM
◦ A load-store Architecture
◦ Fixed-length 32-bit instructions
◦ 3-address instruction formats
RISC features not incorporated
into ARM
◦ Pipelining
 Delayed branches
 Later pipelining included, e.g., ARM7 has a
3 stage pipeline.
◦ Single-cycle execution of all
instructions
© Sonali Chouhan 6
ARM versions
ARM architecture has been extended
over several versions.
ARM1, ARM2, ARM7, StrongARM,
XScale, ARM7TDMI, ...

We will concentrate on ARM7.

© Sonali Chouhan 7
ARM assembly language
Fairly standard assembly language:

LDR r0,[r8] ; a comment

Label ADD r4,r0,r1

© Sonali Chouhan 8
 ARM Data Types
Word is 32 bits long.
Word can be divided into four 8-bit
bytes.
ARM addresses can be 32 bits long.
Address refers to byte. 8-bit
8-bit
◦ Address 4 starts at byte 4. 8-bit
Can be configured at power-up as 8-bit
8-bit
either little- or big-endian mode.

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ARM programming model

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ARM status bits
Every arithmetic, logical, or shifting
operation sets CPSR bits:
◦ N (negative), Z (zero), C (carry), V
(overflow).
Examples:
◦ -1 + 1 = 0 (0xFFFFFFFF + 0x1):NZCV =
0110
◦ 0 - 1 = -1 : NZCV=1000

© Sonali Chouhan 11
Outline
Introduction
ARM Instruction Set
ARM Registers
ARM Operating Modes
ARM Exception Handling

© Sonali Chouhan 12
ARM data instructions
• Basic format:
ADD r2,r0,r1
– Computes r0+r1, stores in r2.
• Immediate operand:
ADD r1,r0,#2
– Computes r0+2, stores in r1.

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 ARM data instructions
• ADD, ADC : add (w. carry(r0+r1+C))

• Examples:
• ADD r2, r0, r1
• ADC r2, r0, r1
 ARM data instructions
• SUB, SBC : subtract (w. carry(r0-r1+C-1))

• Examples:
• SUB r2, r0, r1
• SUC r2, r0, r1
 ARM data instructions
• RSB, RSC : reverse subtract (w. carry(r1-
r0+C-1))
• Examples:
• RSB r2, r0, r1
• RSB r4, r4, #12 (#12-r4)
• RSC r2, r0, r1
 ARM data instructions
• MUL, MLA : multiply (and accumulate
(r0*r1+r2))

• Examples:
• MUL r10, r2, r5
• MLA r10, r2, r1, r5
ARM data instructions
• AND, ORR, EOR (bit wise)
• BIC : Bit Clear, Logical AND NOT
– performs an AND operation on the
bits in Rn with the complements of
the corresponding bits in the value of
Operand2.
• Examples
• AND r9,r2,#0xFF00
• ORR r2,r0,r5
• BIC r0, r1, #0xab
ARM data instructions
r0: 01101001
r1: 11000111
_______________

ORR r3, r0, r1; r3 :11101111

AND r3,r0,r1; r3: 01000001
EOR r3, r0,r1; r3: 10101110
BIC r3, r0, r1; r3: 00101000
ARM data instructions
• LSL, LSR : logical shift left/right (0 fill)

• ASR : arithmetic shift right

ARM data instructions
• ROR : rotate right

• RRX : rotate right extended with C

Data operation varieties
• Logical shift:
– fills with zeroes.
– LSL: – multiplication by 2^n
– LSR: - unsigned division by 2^n
• Arithmetic shift:
– fills with sign bit.
– ASR: - signed division by 2^n
• RRX performs 33-bit rotate, including
C bit from CPSR above sign bit.
 ARM comparison
instructions
• CMP : compare (CMP r0,r1 => r0-r1,
r0<r1)
– Set status bit, discard result of sub
– Set Z=1 if r0=r1
– Set N=1 if r1>r0
• CMN : negated compare (=> r0+r1)
• Example:
• CMP r2, r9
• CMN r0, #64
 ARM comparison
instructions
• TST : bit-wise test (AND)
• TEQ : bit-wise test equivalence (ExOR)
• Example:
• TST r0, #0x3F8
• TEQEQ r10, r9

• CMP, CMN, TST, TEQ set only the

NZCV bits of CPSR.
 ARM move instructions
• MOV, MVN : move (negated)

MOV r0, r1 ; sets r0 to r1

© Sonali Chouhan
 ARM load/store instructions
• LDR, LDRH, LDRB : load (half-word, byte)
• STR, STRH, STRB : store (half-word, byte)
• Addressing modes:
– register indirect : LDR r0,[r1] (from the
address of r1)
– LDR r1,=0xffff ; loads 0xffff into r1
– LDR r2,=place ; loads the address of place
into r2

© Sonali Chouhan
 ARM ADR pseudo-op
ADR : set register to address
• If cannot refer to an address directly
in an instruction.
• Generate value by performing
arithmetic on PC.
• ADR pseudo-op generates instruction
required to calculate address:
ADR Rd, =label

© Sonali Chouhan
 ARM ADR pseudo-op

– ADR r1,FOO (FOO is the

desired location, e.g.,
0x1000)
*Pseudo-ops are like macros

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 Example: C assignments
• C:
x = (a + b) - c;

• Assembler:
ADR r4,a ; get address for a
LDR r0,[r4] ; get value of a
ADR r4,b ; get address for b, reusing r4
LDR r1,[r4] ; get value of b
ADD r3,r0,r1 ; compute a+b
ADR r4,c ; get address for c
LDR r2,[r4] ; get value of c
SUB r3,r3,r2 ; complete computation of x
ADR r4,x ; get address for x
STR r3,[r4]; store value of x
© Sonali Chouhan
 Example: C assignment
• C:
y = a*(b+c);

• Assembler:
ADR r4,b ; get address for b
LDR r0,[r4] ; get value of b
ADR r4,c ; get address for c
LDR r1,[r4] ; get value of c
ADD r2,r0,r1 ; compute (b+c)
ADR r4,a ; get address for a
LDR r0,[r4] ; get value of a
MUL r2,r2,r0 ; compute final value for y
ADR r4,y ; get address for y
STR r2,[r4] ; store y
© Sonali Chouhan
 Example: C assignment
• C:
z = (a << 2) | (b & 15);

• Assembler:
ADR r4,a ; get address for a
LDR r0,[r4] ; get value of a
MOV r0,r0,LSL 2 ; perform shift
ADR r4,b ; get address for b
LDR r1,[r4] ; get value of b
AND r1,r1,#15 ; perform AND
ORR r1,r0,r1 ; perform OR
ADR r4,z ; get address for z
STR r1,[r4] ; store value for z
© Sonali Chouhan
 Additional addressing
modes
• Base-plus-offset addressing:
LDR r0,[r1,#16]
– Loads from location r1+16, r1
unchanged
– Base + offset
– Offset may be
• Immediate value (<=4096)
• A register
• Two modes

© Sonali Chouhan
 Additional addressing
modes

Auto-indexing increments base
register:
LDR r0,[r1,#16]!
- Adds 16 to r1 then uses new
value
- ! causes base reg to be
updated
Post-indexing fetches, then does offset:
LDR r0,[r1],#16
Loads r0 from r1, then adds 16 to r1.
© Sonali Chouhan
 ARM flow of control
• All operations can be performed
conditionally, testing CPSR:
– EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE,
LT, GT, LE
• Branch operation:
B #100 (add 400 to current PC)
– Can be performed conditionally.
– Branches are PC relative
– branch specifies the offset (in word) from
current PC value to the branch target
© Sonali Chouhan
 Condition Codes
• EQ, NE : Equals zero (not) Z=1 (0)
• CS, CC : Carry set (clear) C=1 (0)
• MI, PL : Minus (Plus) N=1 (0)
• VS , VC : Overflow (no) V=1 (0)

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 Condition Codes
• HI, LS : Unsigned higher (lower or
same)
C=1 and Z=0 (C=0 or
Z=1)
• GE, LT : Signed greater than or
equal (less than) N=V (N!=V)
• GT, LE : Signed greater than (less
than or equal) Z=0 and N=V
(N!=V or Z=1)

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 Example: if statement
• C:
if (a > b) { x = 5; y = c + d; } else x = c - d;

• Assembler:
; compute and test condition
ADR r4,a ; get address for a
LDR r0,[r4] ; get value of a
ADR r4,b ; get address for b
LDR r1,[r4] ; get value for b
CMP r0,r1 ; compare a < b
BGE fblock ; if a >= b, branch to false block

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 If statement, cont’d.
; true block
MOV r0,#5 ; generate value for x
ADR r4,x ; get address for x
STR r0,[r4] ; store x
ADR r4,c ; get address for c
LDR r0,[r4] ; get value of c
ADR r4,d ; get address for d
LDR r1,[r4] ; get value of d
ADD r0,r0,r1 ; compute y
ADR r4,y ; get address for y
STR r0,[r4] ; store y
B after ; branch around false block

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 If statement, cont’d.
; false block
fblock ADR r4,c ; get address for c
LDR r0,[r4] ; get value of c
ADR r4,d ; get address for d
LDR r1,[r4] ; get value for d
SUB r0,r0,r1 ; compute a-b
ADR r4,x ; get address for x
STR r0,[r4] ; store value of x
after ...

© Sonali Chouhan
 Example: Conditional
instruction implementation
; true block
MOVLT r0,#5 ; generate value for x
ADRLT r4,x ; get address for x
STRLT r0,[r4] ; store x
ADRLT r4,c ; get address for c
LDRLT r0,[r4] ; get value of c
ADRLT r4,d ; get address for d
LDRLT r1,[r4] ; get value of d
ADDLT r0,r0,r1 ; compute y
ADRLT r4,y ; get address for y
STRLT r0,[r4] ; store y

© Sonali Chouhan
 Example: FIR filter
• C:
for (i=0, f=0; i<N; i++)
f = f + c[i]*x[i];

• Assembler
; loop initiation code
MOV r0,#0 ; use r0 for I
MOV r8,#0 ; use separate index for arrays
ADR r2,N ; get address for N
LDR r1,[r2] ; get value of N
MOV r2,#0 ; use r2 for f

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 FIR filter, cont’.d
ADR r3,c ; load r3 with base of c
ADR r5,x ; load r5 with base of x
; loop body
loop LDR r4,[r3,r8] ; get c[i]
LDR r6,[r5,r8] ; get x[i]
MUL r4,r4,r6 ; compute c[i]*x[i]
ADD r2,r2,r4 ; add into running sum
ADD r8,r8,#4 ; add one word offset to array
index
ADD r0,r0,#1 ; add 1 to i
CMP r0,r1 ; exit?
BLT loop ; if i < N, continue

© Sonali Chouhan
 ARM subroutine linkage
• Branch and link instruction:
BL foo
– Copies current PC to r14.
• To return from subroutine:
MOV r15,r14
• BX, Branch and eXchange
• Branch with instruction set
exchange
(ARM <-> Thumb) © Sonali Chouhan
Outline
Introduction
ARM Instruction Set
ARM Registers
ARM Operating Modes
ARM Exception Handling

© Sonali Chouhan 44
 The Registers
In all ARM processors, following registers are
available and accessible in any processor
mode:
– 13 general-purpose registers R0-R12
– 1 Stack Pointer (SP)
– 1 Link Register (LR)
– 1 Program Counter (PC)
– 1 Application Program Status Register
(APSR)
The Link Register can also be used as a
general-purpose register.
The Stack Pointer can be used as a general-
purpose register in ARM state© only.
Sonali Chouhan
 The Registers
ARM processors, except in ARMv6-M and
ARMv7-M based processors, have a total of 37 or
40 registers
Additional registers in ARM processors are:
•2 supervisor mode registers for banked SP and
LR
•2 abort mode registers for banked SP & LR
•2 undefined mode registers for banked SP & LR
•2 interrupt mode registers for banked SP & LR
•7 FIQ mode registers for banked R8-R12, SP & LR
•2 monitor mode registers for banked SP & LR
•6 Saved Program Status Register (SPSRs), one
for each exception mode.
© Sonali Chouhan
 Current Program Status Register

• Condition code flags

• Interrupt Disable bits.
• N = Negative result from ALU
• I = 1: Disables the IRQ.
• Z = Zero result from ALU
• F = 1: Disables the FIQ.
• C = ALU operation Carried out
• T Bit
• V = ALU operation oVerflowed
• Architecture xT only
• Sticky Overflow flag - Q flag
• • T = 0: Processor in ARM
Architecture 5TE/J only
state
• Indicates if saturation has
occurred • T = 1: Processor in
Thumb state
• J bit
•
• Mode bits
Architecture 5TEJ only
• J = 1: Processor in Jazelle
• Specify the processor
state mode

© Sonali Chouhan
Outline
Introduction
ARM Instruction Set
ARM Registers
ARM Operating Modes
ARM Exception Handling

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 ARM Processor Modes
CPSR[4:0] Mode Register set
10000 User PC, R14..R0,
CPSR
10001 FIQ PC,
R14_fiq..R8_fiq,
R7-R0, CPSR,
SPSR_fiq
10010 IRQ PC, R14_irq,
R13_irq, R12-R0,
CPSR, SPSR_irq
10011 SVC PC, R14_svc,
R13_svc, R12-
R0, CPSR,
SPSR_sv
10111 Abort PC, R14_abt,
© Sonali Chouhan
 ARM Operating Modes
• User : unprivileged mode under
which most tasks run
• FIQ: entered when a high priority
(fast) interrupt is raised
• IRQ: entered when a low priority
(normal) interrupt is raised
• Supervisor : entered on reset and
when a Software Interrupt instruction
is executed
© Sonali Chouhan
 ARM Operating Modes
(Contd.)
• Abort : used to handle memory
access violations
• Undef : used to handle undefined
instructions
• System : privileged mode using the
same registers as user mode

© Sonali Chouhan
 The Registers
• The current processor mode governs
which of several banks is accessible.
Each mode can access
• a particular set of r0-r12 registers
• a particular r13 (the stack pointer, sp)
and r14 (the link register, lr)
• the program counter, r15 (pc)
• the current program status register, cpsr
• Privileged modes (except System)
can also access
• a particular spsr (saved program status
register) © Sonali Chouhan
ARM Register Set

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Register Organization
Summary

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 ARM Thumb
• T (Thumb)-extension shrinks the
ARM instruction set to 16-bit word
length -> 35-40% memory saving
compared to 32-bit instruction set
• Extension enables simpler and
significantly cheaper realization of
processor system.
• Reduced memory without
significant decrease in performance
or increase in code size.
© Sonali Chouhan
 ARM Thumb
• Extension is made to instruction
decoder at the processor pipeline
• Registers are preserved as 32-bit but
only half of them are used

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 Jazelle
• A technique that allows Java
Bytecode to be executed directly in
the ARM architecture.

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 Program Counter (PC)
• When the processor is executing in
ARM state:
• All instructions are 32 bits wide
• All instructions must be word aligned
• Therefore the pc value is stored in bits
[31:2] with bits [1:0] undefined (as
instruction cannot be halfword or byte
aligned).

© Sonali Chouhan
 Program Counter (PC)
• When the processor is executing in Thumb
state:
• All instructions are 16 bits wide
• All instructions must be halfword aligned
• Therefore the pc value is stored in bits [31:1]
with bit [0] undefined (as instruction cannot be
byte aligned).
• Now bit [1] indicate the half word address
• When the processor is executing in Jazelle
state:
• All instructions are 8 bits wide
• Processor performs a word access to read 4
instructions at once © Sonali Chouhan
Outline
Introduction
ARM Instruction Set
ARM Registers
ARM Operating Modes
ARM Exception Handling

© Sonali Chouhan 60
 Exception handling
• When an exception occurs, the ARM:
• Copies CPSR into SPSR_<mode>
• Sets appropriate CPSR bits
• Change to ARM state
• Change to exception mode
• Disable interrupts (if appropriate)
• Stores the return address in
LR_<mode>
• Sets PC to vector address
© Sonali Chouhan
 Exception handling
• Vector Table
– This is a reserved area usually at the
bottom of the memory map.
– Within the table one word is allocated to
each of the various exception types.
– This word contains either a form of a
branch instruction or, in the case of ARMv7-
M and ARMv6-M, an address to the relevant
exception handler.
– Can write the exception handlers in either
ARM or Thumb code
© Sonali Chouhan
Exception handling (Contd.)
• To return, exception handler
needs to:
• Restore CPSR from SPSR_<mode>
• Restore PC from LR_<mode>
• This can only be done in ARM
state.

© Sonali Chouhan
Exception handling (Contd.)
Example ARM-based System

16 bit RAM 32 bit RAM

Interrupt
Controller
Peripherals I/O
nIRQ nFIQ

ARM
Core
8 bit ROM

© Sonali Chouhan
 Summary
• Load/store architecture
• Most instructions operate in single
cycle.
- Some multi-register operations take longer.
• All instructions can be executed
conditionally.
• Several interesting extensions
available or in development like Thumb
instruction set and Jazelle Java machine
© Sonali Chouhan 66