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Pipelining

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9 views

Pipelining

ntg

Uploaded by

saib12830
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Pipelining

Performance Issues
 Longest delay determines clock period
 Critical path: load instruction
 Instruction memory → register file → ALU →
data memory → register file
 Not feasible to vary period for different
instructions
 Violates design principle
 Making the common case fast
 We will improve performance by pipelining

Chapter 4 — The Processor — 2


§4.5 An Overview of Pipelining
Pipelining Analogy
 Pipelined laundry: overlapping execution
 Parallelism improves performance

 Four loads:
 Speedup
= 16/7 = 2.3
 Non-stop:
 Speedup
= 4n/n + 3 ≈ 4
= number of stages

Chapter 4 — The Processor — 3


MIPS Pipeline
 Five stages, one step per stage
1. IF: Instruction fetch from memory
2. ID: Instruction decode & register read
3. EX: Execute operation or calculate address
4. MEM: Access memory operand
5. WB: Write result back to register

Chapter 4 — The Processor — 4


Pipeline Performance
Single-cycle (Tc= 800ps)

Pipelined (Tc= 200ps)

Chapter 4 — The Processor — 5


Pipeline Speedup
 If all stages are balanced
 i.e., all take the same time
 Time between instructionspipelined
= Time between instructionsnonpipelined
Number of stages
 If not balanced, speedup is less
 Speedup due to increased throughput
 Latency (time for each instruction) does not
decrease

Chapter 4 — The Processor — 6


Hazards
 Situations that prevent starting the next
instruction in the next cycle
 Structure hazards
 A required resource is busy
 Data hazard
 Need to wait for previous instruction to
complete its data read/write
 Control hazard
 Deciding on control action depends on
previous instruction

Chapter 4 — The Processor — 7


Structure Hazards
 Conflict for use of a resource
 In MIPS pipeline with a single memory
 Load/store requires data access
 Instruction fetch would have to stall for that
cycle

Would cause a pipeline “bubble”
 Hence, pipelined datapaths require
separate instruction/data memories
 Or separate instruction/data caches

Chapter 4 — The Processor — 8


Data Hazards
 An instruction depends on completion of
data access by a previous instruction
 add $s0, $t 0, $t 1
sub $t 2, $s0, $t 3

Chapter 4 — The Processor — 9


Forwarding (aka Bypassing)
 Use result when it is computed
 Don’t wait for it to be stored in a register
 Requires extra connections in the datapath

Chapter 4 — The Processor — 10


Load-Use Data Hazard
 Can’t always avoid stalls by forwarding
 If value not computed when needed
 Can’t forward backward in time!

Chapter 4 — The Processor — 11


Code Scheduling to Avoid Stalls
 Reorder code to avoid use of load result in
the next instruction
 C code for A = B + E; C = B + F;

lw $t 1, 0( $t 0) lw $t 1, 0( $t 0)
lw $t 2, 4( $t 0) lw $t 2, 4( $t 0)
stall add $t 3, $t 1, $t 2 lw $t 4, 8( $t 0)
sw $t 3, 12( $t 0) add $t 3, $t 1, $t 2
lw $t 4, 8( $t 0) sw $t 3, 12( $t 0)
stall add $t 5, $t 1, $t 4 add $t 5, $t 1, $t 4
sw $t 5, 16( $t 0) sw $t 5, 16( $t 0)
13 cycles 11 cycles

Chapter 4 — The Processor — 12


Control Hazards
 Branch determines flow of control
 Fetching next instruction depends on branch
outcome
 Pipeline can’t always fetch correct instruction
 Still working on ID stage of branch
 In MIPS pipeline
 Need to compare registers and compute
target early in the pipeline
 Add hardware to do it in ID stage

Chapter 4 — The Processor — 13


Stall on Branch
 Wait until branch outcome determined
before fetching next instruction

Chapter 4 — The Processor — 14


Branch Prediction
 Longer pipelines can’t readily determine
branch outcome early
 Stall penalty becomes unacceptable
 Predict outcome of branch
 Only stall if prediction is wrong
 In MIPS pipeline
 Can predict branches not taken
 Fetch instruction after branch, with no delay

Chapter 4 — The Processor — 15


MIPS with Predict Not Taken

Prediction
correct

Prediction
incorrect

Chapter 4 — The Processor — 16


More-Realistic Branch Prediction
 Static branch prediction
 Based on typical branch behavior
 Example: loop and if-statement branches

Predict backward branches taken
 Predict forward branches not taken
 Dynamic branch prediction
 Hardware measures actual branch behavior

e.g., record recent history of each branch
 Assume future behavior will continue the trend

When wrong, stall while re-fetching, and update history

Chapter 4 — The Processor — 17


Pipelining and ISA Design
 MIPS ISA designed for pipelining
 All instructions are 32-bits
 Easier to fetch and decode in one cycle
 c.f. x86: 1- to 17-byte instructions
 Few and regular instruction formats

Can decode and read registers in one step
 Load/store addressing

Can calculate address in 3rd stage, access memory
in 4th stage
 Alignment of memory operands

Memory access takes only one cycle

Chapter 4 — The Processor — 18


Pipeline Summary
The BIG Picture
 Pipelining improves performance by
increasing instruction throughput
 Executes multiple instructions in parallel
 Each instruction has the same latency
 Subject to hazards
 Structure, data, control
 Instruction set design affects complexity of
pipeline implementation
Chapter 4 — The Processor — 19
§4.6 Pipelined Datapath and Control
MIPS Pipelined Datapath

MEM

Right-to-left WB
flow leads to
hazards

Chapter 4 — The Processor — 20


Pipeline registers
 Need registers between stages
 To hold information produced in previous cycle

Chapter 4 — The Processor — 21


IF for Load, Store, …

Chapter 4 — The Processor — 22


ID for Load, Store, …

Chapter 4 — The Processor — 23


EX for Load

Chapter 4 — The Processor — 24


MEM for Load

Chapter 4 — The Processor — 25


WB for Load

Wrong
register
number

Chapter 4 — The Processor — 26


Corrected Datapath for Load

Chapter 4 — The Processor — 27


EX for Store

Chapter 4 — The Processor — 28


MEM for Store

Chapter 4 — The Processor — 29


WB for Store

Chapter 4 — The Processor — 30


Pipelined Control (Simplified)

Chapter 4 — The Processor — 31


Pipelined Control

Chapter 4 — The Processor — 32

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