Jagadeesh CV1
Jagadeesh CV1
Jagadeesh CV1
• Programming Xilinx Artix A7 FPGA board for digital filter implementation in Vivado.
• Extracted filter coefficients from Matlab to form different lattice filters.
• Achieved hardware interface of FPGA to run synthesisable verilog filter modules.
AHB2APB Bridge RTL design using Verilog HDL | Maven Silicon May 2023 – Jul 2023
• Designed an RTL-based bridge that interfaces a High-performance AHB bus to a low-power APB bus.
• Successfully verified the timing diagrams of bridge module for various R/W, burst/wrap techniques.
• Top-level module is simulated in Modelsim and the final model is synthesized in Quartus prime to achieve the
netlist of working bridge module.
Implementation of FSM based Ideal vending machine Dec 2022
• Created a Verilog implementation of a change system in an FSM-based Vending Machine using State analysis.
• Tested the code integrity for various testbenches, ensuring code correctness and hardware reliability.
Certifications
VLSI Design Methodologies | Maven Silicon May 2023
• Certification in front end VLSI course which imparts the VLSI Design Flow, Digital Design and RTL programming
Technical Skills
Hardware Design Languages: Verilog HDL, VHDL.
Programming Languages: C, C++, Python (basics).
Simulation Tools: Quartus Prime, Xilinx Vivado, NI Multisim, Modelsim,Cadence tools, Proteus.
Softwares: MATLAB, VS Code, LaTEX.
Languages: English, Hindi, Telugu.