UNIT 4

Peripheral interfacing and

interrupt handling
 Content
 Interfacing Concept
 Interfacing with memory

 Interfacing of I/o Devices

 Programmable Peripheral Interface 8255

 Interrupt

 Programable interrupt control

 Timer IC 8155
Interfacing I/O devices with 8085

I/O I/O
Interface Devices

System Bus
8085

Memory Memory
Interface Devices
 Memory Interfacing
 The memory is made up of semiconductor
material used to store the programs and data.
Three types of memory is
1. Process memory
2. Primary or main memory
3. Secondary memory
TYPICAL EPROM AND STATIC RAM:
✓A typical semiconductor memory IC will have N address pins, M data pins (or
output pins).
✓Having two power supply pins (one for connecting required supply voltage (V and
the other for connecting ground).
✓The control signals needed for static RAM are chip select (chip enable), read
control (output enable) and write control (write enable).
✓The control signals needed for read operation in EPROM are chip select (chip
enable) and read control (output enable).
summarizes capacity with address

3FF

7FF
FFF

1FFF

3FFF

7FFF
FFFF
 Memory Interfacing
 The 8085 has 16 address lines. That means it can
address

 216 = 64K memory locations.

 Then it will need 1 memory chip with 64k

locations, or 2 chips with 32 K in each, or 4 with
16 K each, or 16 of the 4 K chips, etc.

 how would we use these address lines to control

the multiple chips?
 Memory Interfacing

o Memory interfacing required to:

o Select Chip
o Identify the register
o Enable the appropriate buffer
Chip Selection

 Usually, each memory chip has a CS (Chip

Select) input. The chip will only work if an active
signal is applied on that input.
 To allow the use of multiple chips in the make up
of memory, we need to use a number of the
address lines for the purpose of “chip selection”.
 These address lines are decoded to generate the 2n
necessary CS inputs for the memory chips to be used.
Memory Map and Addresses
 The memory map is a picture representation of
the address range and shows where the different
memory chips are located within the address
range.
Chip Selection using NAND
 The 8085 has 16 address lines. So, it can address
a total of 64K memory locations.
 If we use memory chips with 1K locations each,
then
 we will need 64 such chips.

 The 1K memory chip needs 10 address lines to

uniquely identify the 1K locations.
 That leaves 6 address lines which is the exact
number needed for selecting between the 64
different chips (log264 = 6).
Chip Selection using NAND
 Now, we can break up the 16-bit address of the
8085 into two pieces:

 Depending on the combination on the address

lines A15 - A10 , the address range of the
specified chip is determined.
Chip Select Example
 A chip that uses the combination A15 - A10 =
001000 would have addresses that range from
2000H to 23FFH.
 Keep in mind that the 10 address lines on the chip gives a
range of
 00 0000 0000 to 11 1111 1111 or 000H to 3FFH for each of
the chips.
 The memory chip in this example would require the
following circuit on its chip select input:
Chip selection using NAND
 if we change the above combination to the
following:

 Now the chip would have addresses ranging from:

2400 to 27FF.
 Changing the combination of the address bits
connected to the chip select changes the address
range for the memory chip.
Chip selection using Decoder
 DECODER
It is used to select the memory chip of processor during the execution of a
program. No of IC's used for decoder is
2-4 decoder (74LS139)
3-8 decoder (74LS138)

Fig - Block diagram and Truth table of 2-4 decoder

Fig - Block diagram and Truth table of 3-8 decoder
 EXAMPLE-1
Consider a system in which the full memory space 64kb is utilized for EPROM
memory. Interface the EPROM with 8085 processor.
In this system, the entire 16 address lines of the processor are connected to
address input pins of memory IC to address the internal locations of memory.

The chip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied to
ground). Since the processor is connected to EPROM, the active low RD pin
is connected to active low output enable pin of EPROM.
The range of address for EPROM is 0000H to FFFFH.
EXAMPLE-2
• Consider a system where the available 64kb memory space is equally
• divided between EPROM and RAM. Interface the EPROM and RAM with the 8085
• processor.
• Implement 32kb memory capacity of EPROM using single IC 27256.
• 32kb RAM capacity is implemented using single IC 62256.
• The 32kb memory requires 15 address lines and so the
• address lines A0 - A14 of the processor are connected to 15 address pins of
• both EPROM and RAM.
• The unused address line A15 is used as to chip select.
• If A15 is 1, it select RAM and If A15 is 0, it select EPROM.
• Inverter is used for selecting the memory.
• The memory used is both Ram and EPROM, so the low RD and
• WR pins of processor are connected to low WE and OE
• pins of memory respectively.
• The address range of EPROM will be 0000H to 7FFFH and that of
• RAM will be 7FFFH to FFFFH.
Example 3
• Consider a system in which 32kb memory space is
• implemented using 4 numbers of 8kb memory.
• Interface the EPROM and RAM with 8085 processor.
• The total memory capacity is 32Kb. So, let 2 number of
• 8kb n memory be EPROM and the remaining 2 numbers be RAM.
• Each 8kb memory requires 13 address lines and so the
• address lines A0- A12 of the processor are connected to 13 address pins
of all the memory.
• The address lines and A13 - A14 can be decoded using a
• 2-to-4 decoder to generate four chip select signals.
• These four chip select signals can be used to select one of
• the four memory IC at any one time.
• The address line A15 is used as enable for decoder.
• The simplified schematic memory organization is shown.
 The address allotted to each
memory IC is shown in following
table.
Example 4
• Consider a system in which the 64kb memory space is
• implemented using eight numbers of 8kb memory. Interface the EPROM
• and RAM with 8085 processor.
• The total memory capacity is 64Kb.
• So, let 4 numbers of 8Kb EPROM and 4 numbers of 8Kb RAM.
• Each 8kb memory requires 13 address lines.
• So the address line A0 - A12 of the processor are connected to 13address pins
• The address lines A13, A14 and A15 are decoded using a 3-to-8 dcoder
• to generate eight chip select signals.
• These eight chip select signals can be used to select one of the
• eight memories at any one time.
• The memory interfacing is shown in following figure.
 The address allocation for
Interfacing 4 no. 8Kb EPROM and
4 no. 8Kb RAM with 8085 is,
 Example 5
• Design an memory interface circuits for a given
4K ROM chip. Use all 16 address line . use any
combination of inverter ,NAND gate and
74LS138 decoder to generates the address.
 Example 6
• Draw the diagram for interfacing 8KB of
• ROM and 8KB of RAM with 8085 and
• also explain the number of pins used for
• interfacing .the starting address for ROM
• should be 0000H and starting address for
• Ram should be 8000H
 Example 7
• Draw the diagram for interfacing such that it
• should contain 16 Kbytes of EPROM and 4 KB
• Ram using 2 8KB EPROM and 2KB of RAM
Example 7
Example 7
 Example 8
• Design a memory system such that contains 8K
or EPROM and 4K of RAM with 8085 EPROM
memory address begins at 0000H and Ram
begins at 8000H.write memory address ranges
used for both memory.
 Example 9
• Design a memory system that contains 2K
bytes of EPROM ,immediately followed by 1K
bytes of RAM. The EPROM starts at address
0000H and it is implement using 1K of EPROM
and the RAM is implemented using 1K bytes
RAM chip.
Techniques for I/O Interfacing

◼ Memory-mapped I/O
◼ Peripheral-mapped I/O
 Memory-mapped I/O
◼ 8085 uses its 16-bit address bus to identify
a memory location
◼ Memory address space: 0000H to FFFFH
◼ 8085 needs to identify I/O devices also
◼ I/O devices can be interfaced using
addresses from memory space
◼ 8085 treats such an I/O device as a memory
location
◼ This is called Memory-mapped I/O
 Peripheral-mapped I/O
◼ 8085 has a separate 8-bit addressing scheme
for I/O devices
◼ I/O address space: 00H to FFH
◼ This is called Peripheral-mapped I/O or I/O-
mapped I/O
 Peripheral I/O Instructions
◼ IN Instruction
◼ Inputs data from input device into
the accumulator
◼ It is a 2-byte instruction
◼ Format: IN 8-bit port address
◼ Example: IN 01H
◼ OUT Instruction
◼ Outputs the contents of accumulator to
an output device
◼ It is a 2-byte instruction
◼ Format: OUT 8-bit port address
◼ Example: OUT 02H
 Memo ry Mapped vs I/O Mapped

FEATURES MEMORY MAPPED IO IO MAPPED IO

They cannot be accessed

IO devices are accessed like any other
Addressing like any other memory
memory location.
location.
They are assigned with 16-bit address They are assigned with 8-
Address Size
values. bit address values.
Instructions Used The instruction used are LDA and STA, The instruction used are IN
etc. and OUT.
Only Accumulator can
Registers Any register can communicate with the
communicate with IO
Communicatin g IO device in case of Memory Mapped IO.
devices in case of IO
Mapped IO.
216 IO ports are possible to be used for Only 256 I/O ports are
Space Involved interfacing in case of Memory Mapped available for interfacing in
IO. case of IO Mapped IO
 Memory Mapped vs I/O
Mapped
FEATURES MEMORY MAPPED IO IO MAPPED IO

During writing or read cycles

During writing or read cycles (IO/M` = 0
IO/M` signal (IO/M` = 1) in case of IO
) in case of Memory Mapped IO.
Mapped IO.
No separate control signal required Special control signals are
Control Signal since we have unified memory space in used in the case of IO
the case of Memory Mapped IO. Mapped IO.
Arithmetic and logical
Arithmetic and Arithmetic and logical operations are operations cannot be
Logical performed directly on the data in the case performed directly on the
operations of Memory Mapped IO. data in the case of IO
Mapped IO.
 8085 Communication with I/O
devices
◼ Involves the following three steps
1. Identify the I/O device (with address)
2. Generate Timing & Control signals
3. Data transfer takes place

◼ 8085 communicates with an I/O device only

if there is a Program Instruction to do so
 1.Identify the I/O device (with
address)
1. Memory-mapped I/O (16-bit address)
2. Peripheral-mapped I/O (8-bit address)

1. Absolute Decoding
Using All A7 to A0 address lines

2. Partial Decoding
Using Decoder
 2.Generate Timing & Control
Signals
◼ Memory-mapped I/O
◼ Reading Input: IO/M = 0, RD = 0
◼ Write to Output: IO/M = 0, WR = 0
◼ Peripheral-mapped I/O
◼ Reading Input: IO/M = 1, RD = 0
◼ Write to Output: IO/M = 1, WR = 0

3. Data transfer takes place

▪ By Enabling Latch
 1. Latch Enable

1. Use the I/O select pulse to activate the

interfacing device (Latch)
• Active Low (A Tri state buffer)
 8085 Communication with I/O
devices

• Problem statement: Decode logic for LED out the device

with address 01H.
• 01 ➔ 0 0 0 0 0 0 0 1
• → A7 A6 A5 A4 A3 A2 A1 A0

Step 1 : Generate I/O address pulse

 8085 Communication with I/O
devices

• Problem statement: Decode logic for LED out the device

with address 01H.
• 01 ➔ 0 0 0 0 0 0 0 1
• → A7 A6 A5 A4 A3 A2 A1 A0

2. Step 2 : Generate I/O select pulse

 8085 Communication with I/O
devices

• Problem statement: Decode logic for LED out the device

with address 01H.
• 01 ➔ 0 0 0 0 0 0 0 1
• → A7 A6 A5 A4 A3 A2 A1 A0

3. Step 3 : Use I/O select pulse to activate a latch

 8085 Communication with I/O
devices
• Problem statement : Decode logic for
LED out device with address 01H.
• 01 ➔ 0 0 0 0 0 0 0 1
• → A7 A6 A5 A4 A3 A2 A1 A0
 8085 Communication with I/O
devices
• Problem statement: Decode logic for LED out
device with address 01H using partial
decoding.
• A1 A0 replaced with WR and IO/M
• Output port latch can be access address
00,01,02,03 as A1 A0 = Don’t care
 8085 Communication with I/O
devices
• Problem statement : Interface a keyboard with
address FFH.
• Interfacing of 8- key input port FF
• G1 = A0 to A7 are decoded using an 8-bit input NAND
• G2 generates the device select plus

Device Select Signal is LOW

8085 Communication with I/O devices
• Complete Solution → Absolute Decoding
• FF ➔ 1 1 1 1 1 1 1 1
• → A7 A6 A5 A4 A3 A2 A1 A0
 8085 Communication with I/O
devices
• Complete Solution → Partial Decoding
Extend previous example by
interfacing 8 LED’s as well
Review of important concept
Basic I/O device Peripheral Interfacing

illustration: Seven Segment LED display as an

out put device
 Basic I/O device Peripheral
Interfacing
illustration: Seven Segment LED display as an
out put device
Seven Segment LED
 Basic I/O device Peripheral Interfacing
illustration: Seven Segment LED display as an
out put device
Port Address F5
 Basic I/O device Peripheral Interfacing
illustration: Seven Segment LED display as an
out put device
 Basic I/O device Peripheral Interfacing
illustration: Seven Segment LED display as an
out put device
 Basic I/O device Peripheral Interfacing
illustration: Seven Segment LED display as an
out put device
 Safety control system using memory
mapped I/O system
illustration:
 Safety control system using memory
mapped I/O system
illustration:
 Safety control system using memory
mapped I/O system
illustration:
 Safety control system using memory
mapped I/O system
illustration:
 Safety control system using memory
mapped I/O system
illustration:
 Content
 Interfacing Concept
 Interfacing with memory

 Interfacing of I/o Devices

 Interrupt

 Programmable Peripheral Interface 8255

 Programable interrupt control

 Timer IC 8155
 Content
 Interfacing Concept
 Interfacing with memory

 Interfacing of I/o Devices

 Programmable Peripheral Interface 8255

 Interrupt

 Programable interrupt control

 Timer IC 8155
8085
8085
IN 18H

8085

OUT 50H
8085

A
8086/
8085
Control Word
BSR Mode

8085
A
MOV A, 0F
OUT CWR

8085
A
Mode 0:
Simple Input or Output In this mode, ports A and B are
used as two simple 8-bit I/O ports, and port C as two 4-bit
ports. Each port can be programmed to function as either an
input port or an output port. The input/output features in
Mode 0 are as follows.
1. Outputs are latched.
2. Inputs are not latched.
3. Ports don’t have a handshake or interrupt capability.
Mode 0

Mode 1

Mode 2
0 0 1 1 0 0 0
0 0 0 1 0 0 0
Mode 1:
Input or Output with Handshake In this mode, handshake
signals are exchanged between the MPU and peripherals
before data transfer. The features of the mode include the
following:
1. Two ports (A and B) function as 8-bit I/O ports. They
can be configured as either as input or output ports.
2. Each port uses three lines from ort C as handshake
signals. The remaining two lines of Port C can be used
for simple I/O operations.
3. Input and Output data are latched. 4. Interrupt logic is
supported.
Write CW for
Port A input port
Port B as out put port
Port C upper –input
Port lower -output

8085
Write CW for
Port A input port
Port B as out put port
Port C upper –input
Port lower -output

0 1 1 1 1 1 0
Mode 2:
Bidirectional Data Transfer This mode is used primarily
in applications such as data transfer between two
computers.
In this mode,
Only Port A can be configured as the bidirectional
port
Port B either in Mode 0 or Mode 1.
The Pc3-Pc7 used to handshake signals for data transfer.
The remaining three signals from port C can be used
either as simple I/O or as handshake for port B.
Pc3-Pc7 used to handshake signals

8085
MVI A,E0
OUT CWR
MVI A, FF
OUT PART A

1
8085
E0 1
1
A
1
E0
1
FF
1