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USER DEFINED PRIMITIVE Verilog Codes

user defined primitive verilog codes

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14 views

USER DEFINED PRIMITIVE Verilog Codes

user defined primitive verilog codes

Uploaded by

mansi010504
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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USER DEFINED PRIMITIVE

1. And gate UDP

primitive andgate(y,a,b); module tb;


input a,b; reg a,b;
output y; wire y;

table andgate dut(y,a,b);


// a b : y;

0 ? : 0; initial begin
? 0 : 0; a=0 ; b =0;
1 1 : 1; #2;
endtable a=0 ; b=1;
endprimitive #2;

a=1 ; b=0;

time= 0 , a = 0 , b = 0 , y=0 #2;


time= 2 , a = 0 , b = 1 , y=0 a=1 ; b=1;
time= 4 , a = 1 , b = 0 , y=0
time= 6 , a = 1 , b = 1 , y=1 #2;

end

initial begin

$monitor("time=%d , a = %b , b = %b , y=%b "


, $time,a,b,y);

end

endmodule
2. OR gate UDP

primitive orgate(y,a,b); module tb;


input a,b; reg a,b;
output y; wire y;

table orgate dut(y,a,b);


//a b : y;

0 0 : 0; initial begin
? 1 : 1; a=0 ; b =0;
1 ? : 1; #2;
endtable a=0 ; b=1;
endprimitive #2;

a=1 ; b=0;

#2;

a=1 ; b=1;
time= 0 , a = 0 , b = 0 , y=0 #2;
time= 2 , a = 0 , b = 1 , y=1
time= 4 , a = 1 , b = 0 , y=1 end
time= 6 , a = 1 , b = 1 , y=1

initial begin

$monitor("time=%d , a = %b , b = %b , y=%b "


, $time,a,b,y);

end

endmodule
1. And gate UDP
USER DEFINED PRIMITIVE

1. And gate UDP


USER DEFINED PRIMITIVE

1. And gate UDP


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