Lab Manual ECLR-71 HDL Lab Bachelor of Technology in Electronics & Communication Engineering

Microprocessor/VLSI Laboratory
ECE Department, NIT Kurukshetra
Lab Manual
ECLR-71
HDL Lab
Bachelor of Technology
in
Electronics & Communication Engineering
Department of Electronics & Communication Engineering

National Institute of Technology
Kurukshetra-136119
Website: www.nitkkr.ac.in
1
Vision
To impart state-of-the-art Electronics and Communication Engineering

Education and Research responsive to global challenges.
Mission
 M1: To prepare students with strong theoretical and practical

knowledge by imparting quality education.
 M2: To produce comprehensively trained and innovative graduates in
Electronics and Communication Engineering through hands on practice
and research to encourage them for entrepreneurship.
 M3: To inculcate team work spirit and professional ethics in students.
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Program Educational Objectives (PEOs)
PEO – 1: Have a lead and successful role in their professional career.
PEO – 2: Be able to analyze real life problems and design socially accepted and
economically viable solutions in Electronics and Communication
Engineering area.
PEO –3: Be capable of lifelong learning and professional development by pursuing

higher education and participation in research and development activities.
PEO –4: Have appropriate human and technical communication skills to be a good
team-member/leaders and responsible human being
Program Outcomes (POs)

A graduate of the Electronics and Communication Engineering Program will:
PO1: Engineering knowledge: Possess knowledge of mathematics, science,
engineering fundamentals, and Electronics and Communication Engineering
specialization to solve the problems in Electronics and Telecommunication
Systems.
PO2: Problem analysis: Be able to analyze complex problems in Communication
systems, Analog &Digital Electronic Systems, & DSP based systems using
first principles of mathematics, science, and engineering sciences to reach
substantiated conclusions.
PO3: Design/development of solutions: Be able to design solutions for complex
Electronics and communication engineering problems and design system
components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and
environmental considerations.
PO4: Conduct investigations of complex problems: Be able to use research-based
knowledge and research methods including design of experiments, analysis
and interpretation of data, and synthesis of the information to provide valid
conclusions.
PO5: Modern tool usage: Be able to create, select, and apply appropriate
techniques, resources, and modern engineering and IT tools including
prediction and modeling to complex engineering activities with an
understanding of the limitations.
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PO6: The engineer and society: Be able to apply reasoning informed by the
contextual knowledge to assess societal, health, safety, legal and cultural
issues and the consequent responsibilities relevant to the professional
Electronics and Communication Engineering practice.
PO7: Environment and sustainability: Be able to understand the impact of
Electronics and communication engineering solutions in societal and
environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.
PO8: Ethics: Be able to apply ethical principles, commit to professional ethics in
context to Electronics and communication engineering practice.
PO9: Individual and team work: Be able to function effectively as an individual, as
a member or leader in diverse teams, and in multidisciplinary settings.
PO10: Communication: Be able to communicate effectively on complex Electronics
and communication engineering activities with the engineering community
and with society at large.
PO11: Life-long learning: Be able to recognize the need for, and have the
preparation and ability to engage in independent and life-long learning in the
broadest context of technological change.
PO12: Project management and finance: Have knowledge and understanding of the
engineering and management principles and apply these to one’s own work,
as a member/ leader in a team, to manage projects in multidisciplinary
environments.
Program Specific Outcomes (PSOs)

At the end of the program, the student will:
PSO1: Clearly understand the fundamental concepts of Electronics and

Communication Engineering.
PSO2: Formulate the real life problems and develop solutions in the area of
semiconductor technology, signal processing and communication systems.
PSO3: Posses the skills to communicate effectively in both oral and written forms,
demonstrating the practice of professional ethics, and responsive to societal
and environmental needs.
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ECLR-71
HDL Lab
L T P
0 0 2
The course explores the design aspects of various combinational circuits, counters,
Course
Objectives shift registers, multipliers, ALU, RAM and FSM. The experiments are related with
the design of digital circuits and simulation using Modelsim, Xilinx and verify the
waveforms. The students will get a wide knowledge to use various VLSI
simulation tools.
Course At the end of the course, the students will be able to:
Outcomes CO1 Understand EDA tools.
CO2 Develop VHDL architecture using different design flow.
CO3 Simulate and synthesize digital circuits.
CO4 Generate test-benches to verify functional and timing correctness of digital
circuit/system.
List of Experiments:
1. Write a VHDL Program to implement a 3:8 decoder.
2. Write a VHDL Program to implement a 8:1 multiplexer using behavioral modeling.
3. Write a VHDL Program to implement a 1:8 demultiplexer using behavioral modeling.
4. Write a VHDL Program to implement 4 bit addition/subtraction.
5. Write a VHDL Program to implement 4 bit comparator.
6. Write a VHDL Program to generate Mod- 10 up counter.
7. Write a VHDL Program to generate the 1010 sequence detector. The overlapping
patterns are allowed.
8. Write a program to perform serial to parallel transfer of 4 bit binary number.
9. Write a program to perform parallel to serial transfer of 4 bit binary number.
10. Write a program to design a 2 bit ALU containing 4 arithmetic & 4 logic operations.
Learning beyond Syllabus

1. Design memory using VHDL.
2. Four-Way Traffic Light Controller Designing.
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INTRODUCTION TO VHDL
Introduction to VHDL:
It is a hardware description language that can be used to model a digital system at many levels of
abstraction ranging from the algorithmic level to the gate level. The system may be a single gate to a
complete digital electronic system. VHDL is a hardware description language used in electronic
design automation to describe digital and mixed-signal system such as field-programmable gate
arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming
language. It can be considered a combination of following languages as:
a) Sequential language
b) Concurrent language
c) Net list language
d) Timing language
e) Waveform Generation language
Need of VHDL:
The requirement for it was generated in 1981 under VHSIC program. In this program a number of US
companies were involved in designing VHSIC chips for DoD (defense department). Most of the
companies were using different hardware description to describe and develop their IC, as a result
different vendors could not efficiently exchange designing with one another. Also they were provided
DoD, descriptions of their chips in different hardware description language. Reuse was also an issue,
thus a need for a standard language for design and documentation of the digital system was generated.
Capabilities of VHDL:
1. It is used as an exchange medium between different chip vendors and CAD tool users.
2. It can be used for communication medium between different CAD and CAE tools.
3. Digital system can be modeled a set of interconnected components. Each component in turn van be
modeled a s set of interconnected components further.
4. It supports flexible design methodologies: Top-down Bottom-up mixed
5. It is not technology specific but it is capable of supported technology specific features.
6. It supports both synchronous and asynchronous timing modules.
7. It is an IEEE and ANSI standard.
8. It supports three basic different description styles.
9. It supports a wide range of abstraction levels ranging from abstract behavioral descriptors to vary
precise gate level descriptions.
10. It has element that make large scale design modeling easier such as components, functions and
procedure and package.
11. It is publically available, human readable and above all, it is not proprietary.
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Steps to implement the design
Step 1: Start the Xilinx project navigator by Stat->programs->Xilinx ISE->Project Navigator Step 2:
In the project navigator window click on new project->give file name->next.
Step 3: In the projector window right click on project name-> new source->VHDL module->give file
name->define ports->finish.
Step 4: Write the VHDL code for any gate or circuit.
Step 5: Check Syntax and remove error if present.
Step 6: Simulate design using Modelsim/ISIM.
Step 7: In the project navigator window click on simulation->click on simulate behavioral model.
Step 8: Give inputs by right click on any input->force constant
Step 9: Run simulation
Step 10: Analyze the waveform.
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EXPERIMENT-1
Objective: Write a VHDL program to implement 3:8 decoder

Resources Required:
Hardware Requirement: Computer
Software Requirement: XILINX 8.2 Software
Theory:
A binary decoder is a combinational logic circuit that converts a binary integer value to an
associated pattern of output bits. They are used in a wide variety of applications, including
data de- multiplexing, seven segment display, and memory address decoding. Decoder is
with multiple data inputs and multiple outputs that converts every unique combination of
data input states into a specific combination of output states.
Example: Imagine you are a mall security guard. In your office is a very important and
unique public announcement (PA) phone. The phone has three dialing buttons (A, B, C) and
is connected to eight different speakers, as shown in Table 1. Consequently, you get to
choose which section of the mall hears your announcement based on the set of buttons you
press. For example, if you press A and B and start speaking into the phone (ABC = 110), the
Food Court (D6) is the only place that can hear you. However, if you press A and C (ABC =
101) then the Lady’s Room (D5) is the only place that can hear you.
Such a public announcement phone (or PA system) is an example of a 3-to-8 decoder. Since
the phone has three buttons each of which can either be in one of two possible states —
pressed (=1) or not pressed (= 0) — then the phone can dial eight possible different numbers
(23 = 2*2*2 = 8) as shown below
A B C MALL AREA
0 0 0 Security lunch room (D0)
0 0 1 Men's Room (D1)
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0 1 0 Footwear Stores (D2)
0 1 1 Jewelry Dealers (D3)
1 0 0 Appliance Stores (D4)
1 0 1 Lady's Room (D5)
1 1 0 Food Court (D6)
1 1 1 Bookstores (D7)
Application:The Decoders were used in analog to digital conversion in analog decoders,

Used in electronic circuits to convert instructions into CPU control signals, also used in
logical circuits, data transfer.
Truth Table:
Boolean Expression
Y0 = A’B’C’
Y1 = A’B’C
9
Y2 = A’BC’
Y3 = A’BC
Y4 = AB’C’
Y5 = AB’C
Y6 = ABC’
Y7 = ABC
VHDL Code:
Behavioral Modelling
entity decoder is
Port ( a : in STD_LOGIC_VECTOR(2 DOWNTO 0);
a1 : out STD_LOGIC_VECTOR(7 DOWNTO 0));
end decoder;
architecture Behavioral of decoder is

begin
process(a)
begin
case a is
when "000"=>a1<="10000000";
when "001"=>a1<="01000000";
when "010"=>a1<="00100000";
when "011"=>a1<="00010000";
when "100"=>a1<="00001000";
when "101"=>a1<="00000100";
when "110"=>a1<="00000010";
when "111"=>a1<="00000001";
when others=>null;
end case;
end process;
end Behavioral;
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Output:
RTL Schematic:
Results:VHDL codes of 3:8 decoder is simulated & synthesized

Question:
1. How many 3-line-to-8-line decoders are required for a 1-of-32 decoder?
2. How many data select lines are required for selecting eight inputs?
3. How many 1-of-16 decoders are required for decoding a 7-bit binary number?
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EXPERIMENT -2
Objective: Write a VHDL program to implement 8:1 multiplexerusing behavioral modeling

Resources Required:
Theory:
Multiplexer is simply a data selector. It has multiple inputs and one output. Any one of the
input line is transferred to output depending on the control signal. This type of operation is
usually referred as multiplexing. In 8:1 multiplexer, there are 8 inputs. Any of these inputs
are transferring to output, which depends on the control signal. For 8 inputs we need 3 bit
wide control signal If control signal is "000", then the first input is transferring to output line. If
control signal is "111", then the last input is transferring to output. Similarly, for all values of control
signals.
Figure 2.2 : Logical Diagram of 8:1 Mux
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Truth Table:
Simplified as:
Boolean Expression
Application: Communication systems for modulation purpose, telephone networks, parallel to serial
convertor.
VHDL Code:
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entity mux is
Port ( s : in STD_LOGIC_VECTOR (2 downto 0);
x : in STD_LOGIC_VECTOR (7 downto 0);
y : out STD_LOGIC);
end mux;
architectureBehavioral of mux is
begin
process(s,x)
begin
if s="000" then y<=x(0);
elsif s="001" then y<=x(1);
end if;
end process;
end Behavioral;
Output:
RTL Schematic
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Results:VHDL codes of 8:1 Multiplexer is simulated & synthesized.

Questions:
1. How many inputs in case of 4 to 1 MUX?
2. One multiplexer can take the place of which type of circuit and why?
3. What is data routing in a multiplexer?
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EXPERIMENT-3
Objective:Write a VHDL program to implement a 1:8 Demultiplexer using behavioural
modelling
Tools used:Xilinx-ISE 8.2i, ModelSim 6.2h.

Theory:Demultiplexer means one to many. A demultiplexer is a circuit with one input and
many output. By applying control signal, we can steer any input to the output. Few types of
demultiplexer are 1-to 2, 1-to-4, 1-to-8 and 1-to 16 demultiplexer. Following figure illustrate
the general idea of a demultiplexer with 1 input signal, m control signals, and n output
signals.
Applications:The main application area of demultiplexer is communication

system,ALU,serial to parallel converter.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vhdl_src is
PORT(x:IN STD_LOGIC;
s:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end vhdl_src;
architecture Behavioral of vhdl_src is

begin
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PROCESS (x,s)
BEGIN
case s IS
WHEN "000" => y<="0000000"&x;
WHEN "001" => y<="000000"&x&"0";
WHEN "010" => y<="00000"&x&"00";
WHEN "011" => y<="0000"&x&"000";
WHEN "100" => y<="000"&x&"0000";
WHEN "101" => y<="00"&x&"00000";
WHEN "110" => y<="0"&x&"000000";
WHEN "111" => y<=x&"0000000";
WHEN OTHERS=>NULL;
END CASE;
END PROCESS;
end Behavioral;
Output:
RTL Schematic
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ISE simulation
Results:VHDL codes of 1:8Demultiplexer is simulated & synthesized.
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EXPERIMENT-4
Objective:Write a VHDL program to implement 4 bit addition/subtraction
Tools Used:Xilinx-ISE 8.2i, ModelSim 6.2h
Theory:
A full adder is a combinational circuit that forms the arithmetic sum of three bits. It consists
of three inputs and two outputs. Two of the inputs variables represent the two significant bits
to be added. The third input represents the carry from the previous lower significant position.
The two outputs are designated by the symbols S for sum and C for carry. The binary
variable S gives the value of the least significant bit of the sum. The binary variable C gives
the output carry. The output variables are determined from the arithmetic sum of the input
bits. A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adder connected in cascade, the output carry from
each full adder connected to the input carry of the next full adder in the chain. Figure 4.1
shows the interconnection of four full adder (FA) circuits to provide a 4-bit binary ripple
carry adder. The augend bits of A and addend bits of B are designated by subscript numbers
from right to left, with subscript 0denoting the least significant bit. The carries are connected
in the chain through the full adders. The input carry to the adder is C0 and it ripples through
the full adder to the output carry C4.The S output generate the required sum bits.
Figure 4.14-Bit Adder
The 4bit adder is a typical example of a standard component. It can be used in many
applications involving arithmetic operations. Observe that the design of this circuit by the
classical method would require a truth table with 29 = 512 entries, since there are nine inputs
to the circuit. By using an iterative method of cascading a standard function, it is possible to
obtain a simple and straightforward implementation.
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BinarySubtractor
The subtraction of unsigned binary numbers can be done most conveniently by means of
complement. Subtraction A–B can be done by tacking the 2’s complement of B and adding it
to A. The 2’s complement can be obtained by taking the 1’s complement and adding one to
the least significant pair of bits. The 1’s complement can be implemented with the inverters
and a one can be added to the sum through the input carry as shown in figure4.2.
Figure 4.24-Bit Adder Subtractor
Application:
1) The ALU (arithmetic logic circuitry) of a computer uses half adder to compute the binary
addition operation on two bits.
2) Half adder is used to make full adder as a full adder requires 3 inputs, the third input being
an input carry i.e. we will be able to cascade the carry bit from one adder to the other.
3) Ripple carry adder is possible to create a logical circuit using multiple full adders to add
N-bit numbers. Each full adder inputs a C(in), which is the C(out) of the previous adder. This
kind of adder is called RIPPLE CARRY ADDER, since each carry bit "ripples" to the next
full adder. Note that the first full adder (and only the first) may be replaced by a half adder.
VHDL Code:
fulladder.vhd
library IEEE;
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entity fulladder is
port(
a,b,cin:in std_logic;
s,cout:out std_logic
);
end fulladder;
architecture fulladder of fulladder is
begin
process(a,b,cin)
begin
s <= a xor b xor cin;
cout <= (a and b) or (b and cin) or (cin and a);
end process;
end fulladder ;
fourbitadder.vhd
library IEEE;
entity fourbitadder is
port(
x,y:in std_logic_vector(3 downto 0);
carryin: in std_logic;
sum:out std_logic_vector(3 downto 0);
carryout: out std_logic
);
end fourbitadder;
architecture fourbitadder of fourbitadder is
signal c_int: std_logic_vector(2 downto 0);
component fulladder is
port(
a,b,cin:in std_logic;
s,cout:out std_logic
);
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end component;
begin
c1:fulladder port map(x(0),y(0),carryin,sum(0),c_int(0));
c2:fulladder port map(x(1),y(1),c_int(0),sum(1),c_int(1));
c3:fulladder port map(x(2),y(2),c_int(1),sum(2),c_int(2));
c4:fulladder port map(x(3),y(3),c_int(2),sum(3),carryout);
end fourbit adder;
Output:
RTL Schematic
22
ModelSim Simulation
Results: VHDL codes of implement 4 bit addition/subtraction is simulated &verified.
Questions:
1. What distinguishes the meanings of a half adder’s inputs and outputs from a full-adder’s?
2.How many basic binary subtraction operations are possible?
3. What are the two types of basic adder circuits?
4. What does minuend and subtrahend denotes in a subtractor?
5. What distinguishes the look-ahead-carry adder?
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EXPERIMENT–5
Objective: Write a program to implement 4- bit Comparator

Resources Required:
Theory:
A digital comparator is a hardware electronic device that takes two numbers as input
in binary form and determines whether one number is greater than, less than or equal to the
other number.
Figure 5: Logical Diagram of 4 bit Comparator

Truth Table:
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It can be used to compare two four-bit words. The two 4-bit numbers are A = A3 A2 A1 A0
and B3 B2 B1 B0 where A3 and B3 are the most significant bits.
It compares each of these bits in one number with bits in that of other number and produces
one of the following outputs as A = B, A < B and A>B. The output logic statements of this
converter are
Boolean Expression
 If A3 = 1 and B3 = 0, then A is greater than B (A>B). Or
 If A3 and B3 are equal, and if A2 = 1 and B2 = 0, then A > B. Or
 If A3 and B3 are equal & A2 and B2 are equal, and if A1 = 1, and B1 = 0, then A>B.
Or
 If A3 and B3 are equal, A2 and B2 are equal and A1 and B1 are equal, and if A0 = 1
and B0 = 0, then A > B.
 the output A > B logic expression can be written as
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 The equal output is produced when all the individual bits of one number are exactly
coincides with corresponding bits of another number. Then the logical expression for
A=B output can be written as
 E = (A3 Ex-NOR B3) (A2 Ex-NOR B2) (A1 Ex-NOR B1) (A0 Ex-NOR B0)
Application: Comparators are used in central processing unit s (CPUs) and microcontrollers
(MCUs). Examples of digital comparator include the CMOS 4063 and 4585 and the TTL
7485 and 74682-'89.
VHDL Code:
library IEEE;
entity jan12_1 is
Port ( a,b : in STD_LOGIC_vector(3 downto 0);
eq, ag, bg : out STD_LOGIC);
end jan12_1;
architecture Behavioral of jan12_1 is

begin
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eq<='1' when a=b else '0';

ag<='1' when a>b else '0';
bg<='1' when a<b else '0';
end Behavioral;
End process;
OUTPUT:
RTL Schematic
27
Results:VHDL codes of 4- bit Comparator is simulated &verified.

Questions:
1. In a comparator, if we get input as A>B then the output will be?
2. Which gate act as a basic comparator and why?
3. What is the purpose of digital comparator?
EXPERIMENT-6
Objective:To write a VHDL program to implement Up Counter
Resource Required:Xilinx ISE 8.2.

Theory:Counters are sequential logic devices that follow a predetermined sequence of
counting states which are triggered by an external clock (CLK) signal. The number of states
or counting sequences through which a particular counter advances before returning once
again back to its original first state is called the modulus (MOD). In other words, the
modulus (or just modulo) is the number of states the counter counts and is the dividing
number of the counter. The decade counter has four outputs producing a 4-bit binary number,
it receives an input clock pulse, one by one, and counts up from 0 to 9 repeatedly.
Application: It suitable for human interfacing where a digital display is required.
VHDL code:
library IEEE;
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entity UpCounter is
Port ( clk : in STD_LOGIC;
C : inout integer:=0);
end UpCounter;
architecture Behavioral of UpCounter is

begin
process (clk)
begin
if(clk'event and clk='1')
then if (C<9)
then C<=C+1;
else if(c=9)
then c<=0;
end if;
end if;
end if;
end process;
end Behavioral;
OUTPUT:
RTL Schematic
29
Results: VHDL codes of Mod-10 up counter is simulated &verified.
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EXPERIMENT-7
Objective: Write a VHDL Program to generate the 1010 sequence detector. The overlapping
patterns are allowed
Resources Required: Xilinx ISE 8.2.
Theory:
The objective of this experiment is to introduce the use of sequential logic. The sequence is a
sequential circuit. In sequential logic the output depends on the current input values and also the
previous inputs. When describing the behavior of a sequential logic circuit we talk about the state of
the circuit. The state of a sequential circuit is a result of all previous inputs and determines the
circuit’s output and future behavior. This is why sequential circuits are often referred to as state
machines. Most sequential circuits (including our sequence detector) use a clock signal to control
when the circuit changes states. The inputs of the circuit along with the circuit’s current state provide
the information to determine the circuit’s next state. The clock signal then controls the passing of this
information to the state memory. The output depends only on the circuit’s state, this is known as a
Moore Machine. Figure 7.1 shows the schematic of a Moore Machine.
Figure 7.1 Schematic of a clocked synchronous state machine (Moore Machine).
A sequential circuit’s behavior can be shown in a state diagram. The state diagram for our sequence
detector is shown in figure 7.2. Each circle represents a state and the arrows show the transitions to
the next state. Inside each circle are the state name and the value of the output. Along each arrow is
the input value that corresponds to that transition.
State Diagram:
Figure 7.2 Sequence Detector state diagram.
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A sequence detector accepts as input a string of bits: either 0 or 1. Its output goes to 1 when a target
sequence has been detected. There are two basic types: overlap and non-overlap. In a sequence
detector that allows overlap, the final bits of one sequence can be the start of another sequence.
Example:
11011 detector with overlap X 11011011011
Z 00001001001
11011 detector with no overlap Z 00001000001
Applications:
In a computer network like Ethernet, digital data is sent one bit at a time, at a very high rate. Such a
movement of data is commonly called a bit stream. One characteristic is unfortunate, particularly
that any one bit in a bit stream looks identical to many other bits. Clearly it is important that a
receiver can identify important features in a bit stream. As an example, it is important to identify the
beginning and ending of a message. This is the job of special bit sequences called flags. A flag is
simply a bit sequence that serves as a marker in the bit stream. To detect a flag in a bit stream a
sequence detector is used.
VHDL code:
library IEEE;
--Sequence detector for detecting the sequence "1010".
--Non overlapping type.
entity seq_det is
port( clk : in std_logic;
reset : in std_logic;
input : in std_logic; --input bit sequence
output : out std_logic --'1' indicates the pattern
"1010" is detected in the sequence.
);
end seq_det;
architecture Behavioral of seq_det is
type state_type is (s0,s1,s2,s3); --Defines the type for
states in the state machine
signal state : state_type := s0; --Declare the signal with
the corresponding state type.
begin
process(clk, reset)
begin
if( reset = '1' ) then --resets state and output
signal when reset is asserted.
output <= '0';
state <= s0;
elsif ( clk' event and clk='1' ) then --at rising edge
of clock
case state is
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when s0 => --when the current state is s0

output <= '0';
if ( input = '0' ) then
state <= s0;
else
state <= s1;
end if;
state <= s2;
output<='0';
else
state <= s1;
output<='0';
end if;
state <= s0;
output<='0';
else
state <= s3;
output<='0';
end if;
output<='1';
state <= s1;
else
state <= s2;
output <= '1'; --Output is 1 when the
pattern "1010" is found in the sequence.
end if;
when others =>
NULL;
end case;
end if;
end process;
end Behavioral;
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OUTPUT:
RTL Schematic:
34
ISIM Simulation:
Results:
Thus,the VHDL code for the 1010 sequence detector circuit was simulated and verified.
Questions:
1. The major difference between a moore and mealy machine.
2. How do we decide which and when to use a moore FSM or a mealy FSM for a circuit.
35
EXPERIMENT –8
Objective: Write a VHDL code to implement serial to parallel of 4 bit binary number
Resources Required: Xilinx-ISE 8.2i,ModelSim 6.2h
Theory:
Figure 8.1 4-bit Serial-in to Parallel-out Shift Register

The operation is as follows. Let’s assume that all the flip-flops ( FFA to FFD ) have just been
RESET ( CLEAR input ) and that all the outputs QA to QD are at logic level “0” ie, no
parallel data output.
If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the
output of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the other
outputs still remaining LOW at logic “0”. Assume now that the DATA input pin of FFA has
returned LOW again to logic “0” giving us one data pulse or 0-1-0.
The second clock pulse will change the output of FFA to logic “0” and the output of FFB
and QB HIGH to logic “1” as its input D has the logic “1” level on it from QA. The logic “1”
has now moved or been “shifted” one place along the register to the right as it is now at QA.
36
When the third clock pulse arrives this logic “1” value moves to the output of FFC ( QC ) and
so on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again
to logic level “0” because the input to FFA has remained constant at logic level “0”.
The effect of each clock pulse is to shift the data contents of each stage one place to the right,
and this is shown in the following table until the complete data value of 0-0-0-1is stored in
the register. This data value can now be read directly from the outputs of QAto QD.
Then the data has been converted from a serial data input signal to a parallel data output. The
truth table and following waveforms show the propagation of the logic “1” through the
register from left to right as follows.
Basic Data Movement Through A Shift Register:
Clock Pulse No QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 0 0 0 0
37
Note that after the fourth clock pulse has ended the 4-bits of data ( 0-0-0-1 ) are stored in the
register and will remain there provided clocking of the register has stopped. In practice the
input data to the register may consist of various combinations of logic “1” and “0”.
Commonly available SIPO IC’s include the standard 8-bit 74LS164.
VHDL CODE:
library IEEE;
entity sipo is
port( y:inout std_logic_vector( 3 downto 0);
x: in std_logic;
clr:in std_logic;
clk:in std_logic);
end sipo;
architecture Behavioral of sipo is
begin
process(clk)
begin
if(clr='1')then
y<="0000";
elsif(clk'event and clk='1')then
y(3)<=x;
y(2)<=y(3);
y(1)<=y(2);
y(0)<=y(1);
end if;
end process;
end Behavioral;
38
Output:
RTL Schematic
39
ISE Simulation
Results: VHDL code to implement serial to parallel of 4 bit binary number is simulated and
verified.
40
EXPERIMENT-9
Objective:Write a VHDL program to perform parallel to serial transfer of 4 bit binary

number
Resources Required:Xilinx-ISE 8.2i, ModelSim 6.2h
Theory:
Parallel-in/ serial-out shift registers do everything that the previous serial-in/ serial-out
shift registers do plus input data to all stages simultaneously. The parallel-in/ serial-out
shift register stores data, shifts it on a clock by clock basis, and delays it by the number of
stages times the clock period. In addition, parallel-in/ serial-out really means that we can
load data in parallel into all stages before any shifting ever begins. This is a way to convert
data from a parallel format to a serial format. By parallel format we mean that the data bits
are present simultaneously on individual wires, one for each data bit as shown below. By
serial format we mean that the data bits are presented sequentially in time on a single wire
or circuit as in the case of the “data out” on the block diagram below.
.
Application:
1.Bit serial operations can be performed quickly through device iteration
2. Iteration (a purely combinational approach) is expensive (in terms of # of transistors, chip
area, power, etc).
3. A sequential approach allows the reuse of combinational functional units throughout the
multi-cycle operation
41
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity parallel_in_serial_out is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
load : in STD_LOGIC;
din : in STD_LOGIC_VECTOR(3 downto 0);
dout : out STD_LOGIC
);
end parallel_in_serial_out;
architecture piso_arc of parallel_in_serial_out is
begin
piso : process (clk,reset,load,din) is
variable temp : std_logic_vector (din'range);
begin
if (reset='1') then
temp := (others=>'0');
elsif (load='1') then
temp := din ;
elsif (rising_edge (clk)) then
dout <= temp(3);
temp := temp(2 downto 0) & '0';
end if;
end process piso;
end piso_arc;
42
Output:
RTL Schematic
43
ModelSim simulation
Results: VHDL program to perform parallel to serial transfer of 4 bit binary number is
simulated and verified.
Questions:
1.What type of register would have a complete binary number shifted in one bit at a time and
have all the stored bits shifted out one at a time?
2. What is the difference between shift-left register and shift-right register?
3. How much storage capacity does require in each stage of shift register?
44
EXPERIMENT–10
Objective:Write a program to design a 2 bit ALU containing 4 arithmetic & 4 logic
operations
Resources Required:Xilinx-ISE 8.2i, ModelSim SE PLUS 6.2h
Theory: An ALU stands for arithmetic logic unit ALU is a digital circuit used to perform
arithmetic and logic operations. It represents the fundamental building block of the central
processing unit of CPU. Modern CPUs contains very powerful and complex ALUs. In some
processors ALU is divided into two units an arithmetic unit and a logic unit.
VHDL code:
library IEEE;
entity ALU is
port(
inputA,inputB:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
output:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
sel:IN STD_LOGIC_VECTOR(2 DOWNTO 0)
);
end ALU;
architecture alu of ALU is

begin
PROCESS(inputA,inputB,sel)
BEGIN
case sel is
when "000" => output<=inputA+inputB;
when "001" => output<=inputA-inputB;
when "010" => output<=inputA-1;
when "011" => output<=inputA+1;
when "100" => output<=inputA and inputB;
when "101" => output<=inputA or inputB;
when "110" => output<=not inputA;
when "111" => output<=inputA xor inputB;
when others => output<=NULL;
45
end case;
END PROCESS;
end alu;
Output:
RTL Schematic
ISE Simulation
Results:Design of 2 bit ALU containing 4 arithmetic & 4 logic operations is simulated and
verified.
46
Learning beyond Syllabus
Objective:Write a VHDL program for memory
Resources Required: Xilinx ISE 8.1 software
Theory:
The RAM's address is used as an index into the memory array. The array is declared as an
integer-indexed array, but the address port is modelled as a std_logic_vector signal. Type
mismatch! To get round this we use the to_integer function from IEEE package numeric_std.
But this requires an argument of either signed or unsigned type, so we first convert the
std_logic_vector value to unsigned.This memory also displays write-before-read behaviour,
common in static memories. What is that? It means that during a write-cycle the data being
returned is the same as that being written. Without this, the data returned through the dataout
port would be the data just being overwritten. Not ideal.
This model synthesises into internal block memories in the majority of FPGA architectures.
To summarise the key code points from this RAM model, we have:
 Unconstrained ports
 std_logic_vector to integer conversion
 Write-before-read
VHDL code:
library IEEE;
use IEEE.Numeric_Std.all;
entity sync_ram is
port (
clock : in std_logic;
we : in std_logic;
address : in std_logic_vector;
datain : in std_logic_vector;
dataout : out std_logic_vector
);
end entity sync_ram;
architecture RTL of sync_ram is
type ram_type is array (0 to (2**address'length)-1) of

std_logic_vector(datain'range);
signal ram : ram_type;
47
signal read_address : std_logic_vector(address'range);
begin
RamProc: process(clock) is
begin
if rising_edge(clock) then
if we = '1' then
ram(to_integer(unsigned(address))) <= datain;
end if;
read_address <= address;
end if;
end process RamProc;
dataout <= ram(to_integer(unsigned(read_address)));
end architecture RTL;
48
Objective: Four-Way Traffic Light Controller Designing
Resources Required: Xilinx ISE 8.1 software
Theory:
It is often useful to be able to sequence through an arbitrary number of states, staying in each
state an arbitrary amount of time. For example, consider the set of traffic lights shown in
Figure 2. The lights are assumed to be at a four-way intersection with one street going north-
south and the other road going east-west.
Figure 2 Six colored LEDs can represent a set of traffic lights
A state diagram for controlling these traffic lights is shown in Figure3. If we use a 3 Hz clock
to drive this state diagram then a delay of 1 second is achieved by staying in a state for three
clock cycles. Similarly, a delay of 5 second is achieved by staying in a state for fifteen clock
cycles. The count variable in Figure 3will be reset to zero when moving to the next state after
a timeout. Table 1 is a VHDL program that implements the state diagram in Figure 3and its
simulation is shown in Figure 4. Because we need a counter for the delay count it is more
convenient in this case to combine the state register and combinational modules C1 in the
Moore machine in Figure 3 into a single sequential process as shown in Table 1. Note in this
case we use only a single state variable. To generate the 3 Hz signal we will use the version
of clkdiv.
49
Table 1 Traffic Light States
Figure 3: State diagram for controlling traffic lights
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_unsigned.all;
entity traffic is
port (clk: in STD_LOGIC;
clr: in STD_LOGIC;
lights: out STD_LOGIC_VECTOR(5 downto 0));
end traffic;
architecture traffic of traffic is
type state_type is (s0, s1, s2, s3, s4, s5);
signal state: state_type;
50
signal count: STD_LOGIC_VECTOR(3 downto 0);

constant SEC5: STD_LOGIC_VECTOR(3 downto 0) := "1111";
constant SEC1: STD_LOGIC_VECTOR(3 downto 0) := "0011";
begin
process(clk, clr)
begin
if clr = '1' then
state <= s0;
count <= X"0";
elsif clk'event and clk = '1' then
case state is
when s0 =>
if count < SEC5 then
state <= s0;
count <= count + 1;
else
state <= s1;
count <= X"0";
end if;
when s1 =>
state <= s1;
count <= count + 1;
else
state <= s2;
count <= X"0";
end if;
when s2 =>
state <= s3;
count <= count + 1;
else
state <= s3;
count <= X"0";
end if;
when s3 =>
state <= s3;
count <= count + 1;
else
state <= s4;
count <= X"0";
end if;
when s4 =>
state <= s4;
count <= count + 1;
else
state <= s5;
count <= X"0";
51
end if;
when s5 =>
state <= s5;
count <= count + 1;
else
state <= s0;
count <= X"0";
end if;
when others =>
state <= s0;
end case;
end if;
end process;
C2: process(state)
begin
case state is
when s0 => lights <= "100001";
when s1 => lights <= "100010";
when s2 => lights <= "100100";
when s3 => lights <= "001100";
when s4 => lights <= "010100";
when s5 => lights <= "100100";
when others => lights <= "100001";
end case;
end process;
end traffic;
clock divider
library IEEE;
use IEEE.STD_LOGIC_unsigned.all;
entity clkdiv is
port(
mclk : in STD_LOGIC;
clr : in STD_LOGIC;
clk190 : out STD_LOGIC;
clk3 : out STD_LOGIC
);
end clkdiv;
architecture clkdiv of clkdiv is
signal q:STD_LOGIC_VECTOR(24 downto 0);
begin
-- clock divider
process(mclk, clr)
begin
if clr = '1' then
q <= X"000000" & '0';
elsif mclk'event and mclk='1' then
q <= q + 1;
end if;
52
end process;
clk3 <= q(24); -- 3 Hz
clk190 <= q(18); -- 190 H
end clkdiv;
traffic_lights_top
library IEEE;
entity traffic_lights_top is
port(
clk : in STD_LOGIC;
btn : in STD_LOGIC_VECTOR(3 downto 3);
ld : out STD_LOGIC_VECTOR(7 downto 2)
);
end traffic_lights_top;
architecture traffic_lights_top of traffic_lights_top is
component clkdiv is
port(
mclk : in STD_LOGIC;
clr : in STD_LOGIC;
clk190 : out STD_LOGIC;
clk3 : out STD_LOGIC
);
end component;
component traffic is
port (clk: in STD_LOGIC;
clr: in STD_LOGIC;
lights: out STD_LOGIC_VECTOR(5 downto 0));
end component;
signal clr, clk3: STD_LOGIC;
begin
clr <= btn(3);
U1: clkdiv
port map (
mclk=>clk,
clr=>clr,
clk3=>clk3
);
U2: traffic
port map (
clk=>clk3,
clr=>clr,
lights=>ld
);
end traffic_lights_top;
53
OUTPUT:
Figure 4: Simulation of the VHDL program
54

Lab Manual ECLR-71 HDL Lab Bachelor of Technology in Electronics & Communication Engineering

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Microprocessor/VLSI Laboratory

ECE Department, NIT Kurukshetra

Department of Electronics & Communication Engineering

To impart state-of-the-art Electronics and Communication Engineering

 M1: To prepare students with strong theoretical and practical

Program Educational Objectives (PEOs)

PEO – 1: Have a lead and successful role in their professional career.

PEO –3: Be capable of lifelong learning and professional development by pursuing

Program Outcomes (POs)

Program Specific Outcomes (PSOs)

PSO1: Clearly understand the fundamental concepts of Electronics and

Learning beyond Syllabus

Steps to implement the design

Objective: Write a VHDL program to implement 3:8 decoder

0 0 0 Security lunch room (D0)

0 0 1 Men's Room (D1)

0 1 0 Footwear Stores (D2)

0 1 1 Jewelry Dealers (D3)

1 0 0 Appliance Stores (D4)

1 0 1 Lady's Room (D5)

1 1 0 Food Court (D6)

Application:The Decoders were used in analog to digital conversion in analog decoders,

architecture Behavioral of decoder is

Results:VHDL codes of 3:8 decoder is simulated & synthesized

Objective: Write a VHDL program to implement 8:1 multiplexerusing behavioral modeling

Figure 2.2 : Logical Diagram of 8:1 Mux

Results:VHDL codes of 8:1 Multiplexer is simulated & synthesized.

Tools used:Xilinx-ISE 8.2i, ModelSim 6.2h.

Applications:The main application area of demultiplexer is communication

architecture Behavioral of vhdl_src is

Results:VHDL codes of 1:8Demultiplexer is simulated & synthesized.

Objective:Write a VHDL program to implement 4 bit addition/subtraction

Tools Used:Xilinx-ISE 8.2i, ModelSim 6.2h

Figure 4.14-Bit Adder

Figure 4.24-Bit Adder Subtractor

Results: VHDL codes of implement 4 bit addition/subtraction is simulated &verified.

2.How many basic binary subtraction operations are possible?

3. What are the two types of basic adder circuits?

4. What does minuend and subtrahend denotes in a subtractor?

5. What distinguishes the look-ahead-carry adder?

Objective: Write a program to implement 4- bit Comparator

Figure 5: Logical Diagram of 4 bit Comparator

architecture Behavioral of jan12_1 is

eq<='1' when a=b else '0';

Results:VHDL codes of 4- bit Comparator is simulated &verified.

Resource Required:Xilinx ISE 8.2.

architecture Behavioral of UpCounter is

Results: VHDL codes of Mod-10 up counter is simulated &verified.

Figure 7.1 Schematic of a clocked synchronous state machine (Moore Machine).

Figure 7.2 Sequence Detector state diagram.

when s0 => --when the current state is s0

Resources Required: Xilinx-ISE 8.2i,ModelSim 6.2h

Figure 8.1 4-bit Serial-in to Parallel-out Shift Register

Basic Data Movement Through A Shift Register:

architecture Behavioral of sipo is

Objective:Write a VHDL program to perform parallel to serial transfer of 4 bit binary

2. What is the difference between shift-left register and shift-right register?

architecture alu of ALU is

Learning beyond Syllabus