Special Memory (SM) Bits C

Special memory bits provide a variety of status and control functions, and also
serve as a means of communicating information between the CPU and your
program. Special memory bits can be used as bits, bytes, words, or double words.

SMB0: Status Bits

As described in Table C-1, SMB0 contains eight status bits that are updated by the
S7-200 CPU at the end of each scan cycle.

Table C-1 Special Memory Byte SMB0 (SM0.0 to SM0.7)

SM Bits Description
SM0.0 This bit is always on.
SM0.1 This bit is on for the first scan cycle. One use is to call an initialization
subroutine.
SM0.2 This bit is turned on for one scan cycle if retentive data was lost. This bit can
be used as either an error memory bit or as a mechanism to invoke a special
startup sequence.
SM0.3 This bit is turned on for one scan cycle when RUN mode is entered from a
power-up condition. This bit can be used to provide machine warm-up time
before starting an operation.
SM0.4 This bit provides a clock pulse that is on for 30 seconds and off for 30
seconds, for a duty cycle time of 1 minute. It provides an easy-to-use delay, or
a 1-minute clock pulse.
SM0.5 This bit provides a clock pulse that is on for 0.5 seconds and then off for 0.5
seconds, for a duty cycle time of 1 second. It provides an easy-to-use delay
or a 1-second clock pulse.
SM0.6 This bit is a scan cycle clock which is on for one scan cycle and then off for
the next scan cycle. This bit can be used as a scan counter input.
SM0.7 This bit reflects the position of the Mode switch (off is TERM position, and on
is RUN position). If you use this bit to enable Freeport mode when the switch
is in the RUN position, normal communication with the programming device
can be enabled by switching to the TERM position.

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SMB1: Status Bits

As described in Table C-2, SMB1 contains various potential error indicators. These
bits are set and reset by instructions at execution time.

Table C-2 Special Memory Byte SMB1 (SM1.0 to SM1.7)

SM Bits Description
SM1.0 This bit is turned on by the execution of certain instructions when the result of
the operation is zero.
SM1.1 This bit is turned on by the execution of certain instructions either when an
overflow results or when an illegal numeric value is detected.
SM1.2 This bit is turned on when a negative result is produced by a math operation.
SM1.3 This bit is turned on when division by zero is attempted.
SM1.4 This bit is turned on when the Add to Table instruction attempts to overfill the
table.
SM1.5 This bit is turned on when either LIFO or FIFO instructions attempt to read
from an empty table.
SM1.6 This bit is turned on when an attempt to convert a non-BCD value to binary is
made.
SM1.7 This bit is turned on when an ASCII value cannot be converted to a valid
hexadecimal value.

SMB2: Freeport Receive Character

SMB2 is the Freeport receive character buffer. As described in Table C-3, each
character received while in Freeport mode is placed in this location for easy access
from the ladder logic program.

Table C-3 Special Memory Byte SMB2

SM Byte Description
SMB2 This byte contains each character that is received from Port 0 or Port 1 during
Freeport communication.

SMB3: Freeport Parity Error

SMB3 is used for Freeport mode and contains a parity error bit that is set when a
parity error is detected on a received character. As shown in Table C-4, SM3.0
turns on when a parity error is detected. Use this bit to discard the message.

Table C-4 Special Memory Byte SMB3 (SM3.0 to SM3.7)

SM Bits Description
SM3.0 Parity error from Port 0 or Port 1 (0 = no error; 1 = error was detected)
SM3.1 to
Reserved
SM3.7

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SMB4: Queue Overflow

As described in Table C-5, SMB4 contains the interrupt queue overflow bits, a
status indicator showing whether interrupts are enabled or disabled, and a
transmitter-idle memory bit. The queue overflow bits indicate either that interrupts
are happening at a rate greater than can be processed, or that interrupts were
disabled with the global interrupt disable instruction.

Table C-5 Special Memory Byte SMB4 (SM4.0 to SM4.7)

SM Bits Description
SM4.01 This bit is turned on when the communication interrupt queue has overflowed.
SM4.11 This bit is turned on when the input interrupt queue has overflowed.
SM4.21 This bit is turned on when the timed interrupt queue has overflowed.
SM4.3 This bit is turned on when a run-time programming problem is detected.
SM4.4 This bit reflects the global interrupt enable state. It is turned on when
interrupts are enabled.
SM4.5 This bit is turned on when the transmitter is idle (Port 0).
SM4.6 This bit is turned on when the transmitter is idle (Port 1).
SM4.7 This bit is turned on when something is forced.
1 Use status bits 4.0, 4.1, and 4.2 only in an interrupt routine. These status bits are reset when
the queue is emptied, and control is returned to the main program.

SMB5: I/O Status

As described in Table C-6, SMB5 contains status bits about error conditions that
were detected in the I/O system. These bits provide an overview of the I/O errors
detected.

Table C-6 Special Memory Byte SMB5 (SM5.0 to SM5.7)

SM Bits Description
SM5.0 This bit is turned on if any I/O errors are present.
SM5.1 This bit is turned on if too many digital I/O points have been connected to the
I/O bus.
SM5.2 This bit is turned on if too many analog I/O points have been connected to the
I/O bus.
SM5.3 to
Reserved.
SM5.6
SM5.7 This bit is turned on if a DP standard bus fault is present

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SMB6: CPU ID Register

As described in Table C-7, SMB6 is the CPU identification register. SM6.4 to
SM6.7 identify the type of CPU. SM6.0 to SM6.3 are reserved for future use.

Table C-7 Special Memory Byte SMB6

SM Bits Description
Format MSB LSB
7 0
CPU ID register
x x x x r r r r

SM6.4 to xxxx = 0000 = CPU 212/CPU 222

SM6.7 0010 = CPU 214/CPU 224
0110 = CPU 221
1000 = CPU 215
1001 = CPU 216
SM6.0 to
Reserved
SM6.3

SMB7: Reserved
SMB7 is reserved for future use.

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SMB8 to SMB21: I/O Module ID and Error Registers

SMB8 through SMB21 are organized in byte pairs for expansion modules 0 to 6.
As described in Table C-8, the even-numbered byte of each pair is the
module-identification register. These bytes identify the module type, the I/O type,
and the number of inputs and outputs. The odd-numbered byte of each pair is the
module error register. These bytes provide an indication of any errors detected in
the I/O for that module.

Table C-8 Special Memory Bytes SMB8 to SMB21

SM Byte Description
Format Even-Number Byte: Module ID Register Odd-Number Byte: Module Error Register
MSB LSB MSB LSB
7 0 7 0
M t t A i i Q Q C ie 0 b r P f t

M: Module present 0 = Present C: Configuration error

1 = Not present ie intelligent module error
tt: 00 Non-intelligent I/O module 0 = no error
01 Intelligent module 1 = error
10 Reserved b: bus fault or parity error
11 Reserved
r: Out-of-range error
A I/O type 0 = Discrete
1 = Analog P: No user power error
ii 00 No inputs f: Blown fuse error
01 2 AI or 8 DI t: Terminal block loose error
10 4 AI or 16 DI
11 8 AI or 32 DI
QQ 00 No outputs
01 2 AQ or 8 DQ
10 4 AQ or 16 DQ
11 8 AQ or 32 DQ
SMB8 Module 0 ID register
SMB9 Module 0 error register
SMB10 Module 1 ID register
SMB11 Module 1 error register
SMB12 Module 2 ID register
SMB13 Module 2 error register
SMB14 Module 3 ID register
SMB15 Module 3 error register
SMB16 Module 4 ID register
SMB17 Module 4 error register
SMB18 Module 5 ID register
SMB19 Module 5 error register
SMB20 Module 6 ID register
SMB21 Module 6 error register

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SMW22 to SMW26: Scan Times

As described in Table C-9, SMW22, SMW24, and SMW26 provide scan time
information: minimum scan time, maximum scan time, and last scan time in
milliseconds.

Table C-9 Special Memory Words SMW22 to SMW26

SM Word Description
SMW22 This word provides the scan time of the last scan cycle.
SMW24 This word provides the minimum scan time recorded since entering the RUN
mode.
SMW26 This word provides the maximum scan time recorded since entering the
RUN mode.

SMB28 and SMB29: Analog Adjustment

As described in Table C-10, SMB28 holds the digital value that represents the
position of analog adjustment 0. SMB29 holds the digital value that represents the
position of analog adjustment 1.

Table C-10 Special Memory Bytes SMB28 and SMB29

SM Byte Description
SMB28 This byte stores the value entered with analog adjustment 0. This value is
updated once per scan in STOP/RUN.
SMB29 This byte stores the value entered with analog adjustment 1. This value is
updated once per scan in STOP/RUN.

SMB30 and SMB130: Freeport Control Registers

SMB30 controls the Freeport communication for port 0; SMB130 controls the
Freeport communication for port 1. You can read and write to SMB30 and
SMB130. As described in Table C-11, these bytes configure the respective
communication port for Freeport operation and provide selection of either Freeport
or system protocol support.

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Table C-11 Special Memory Byte SMB30

Port 0 Port 1 Description

Format of Format of MSB LSB
7 0
SMB30 SMB130 Freeport mode control byte
p p d b b b m m

SM30.6 SM130.6 pp Parity select

and and 00 = no parity
SM30.7 SM130.7 01 = even parity
10 = no parity
11 = odd parity
SM30.5 SM130.5 d Data bits per character
0= 8 bits per character
1= 7 bits per character
SM30.2 to SM130.2 bbb Freeport Baud rate
SM30.4 to 000 = 38,400 baud
SM130.4 001 = 19,200 baud
010 = 9,600 baud
011 = 4,800 baud
100 = 2,400 baud
101 = 1,200 baud
110 = 600 baud
111 = 300 baud
SM30.0 SM130.0 mm Protocol selection
and and 00 = Point-to-Point Interface protocol (PPI/slave mode)
SM30.1 SM130.1 01 = Freeport protocol
10 = PPI/master mode
11 = Reserved (defaults to PPI/slave mode)
Note: When you select code mm = 10 (PPI master), the PLC will
become a master on the network and allow the NETR and
NETW instructions to be executed. Bits 2 through 7 are ignored
in PPI modes.

SMB31 and SMW32: Permanent Memory (EEPROM) Write Control

You can save a value stored in V memory to permanent memory (EEPROM) under
the control of your program. To do this, load the address of the location to be
saved in SMW32. Then, load SMB31 with the command to save the value. Once
you have loaded the command to save the value, you do not change the value in V
memory until the CPU resets SM31.7, indicating that the save operation is
complete.
At the end of each scan, the CPU checks to see if a command to save a value to
permanent memory was issued. If the command was issued, the specified value is
saved to permanent memory.

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As described in Table C-12, SMB31 defines the size of the data to be saved to
permanent memory and also provides the command that initiates the execution of
a save operation. SMW32 stores the starting address in V memory for the data to
be saved to permanent memory.

Table C-12 Special Memory Byte SMB31 and Special Memory Word SMW32

SM Byte Description
Format SMB31: MSB LSB
7 0
Software
command c 0 0 0 0 0 s s

MSB LSB
SMW32:
15 0
V memory
address V memory address

SM31.0 ss: Size of the value to be saved

and 00 = byte
SM31.1 01 = byte
10 = word
11 = double word
SM31.7 c: Save to permanent memory (EEPROM)
0 = No request for a save operation to be performed
1 = User program requests that the CPU save data to permanent
memory.
The CPU resets this bit after each save operation.
SMW32 The V memory address for the data to be saved is stored in SMW32. This
value is entered as an offset from V0. When a save operation is executed, the
value in this V memory address is saved to the corresponding V memory
location in the permanent memory (EEPROM).

SMB34 and SMB35: Time Interval Registers for Timed Interrupts

As described in Table C-13, SMB34 specifies the time interval for timed interrupt 0,
and SMB35 specifies the time interval for timed interrupt 1. You can specify the
time interval (in 1-ms increments) from 1 ms to 255 ms. The time-interval value is
captured by the CPU at the time the corresponding timed interrupt event is
attached to an interrupt routine. To change the time interval, you must reattach the
timed interrupt event to the same or to a different interrupt routine. You can
terminate the timed interrupt event by detaching the event.

Table C-13 Special Memory Bytes SMB34 and SMB35

SM Byte Description
SMB34 This byte specifies the time interval (in 1-ms increments from 1 ms to
255 ms) for timed interrupt 0.
SMB35 This byte specifies the time interval (in 1-ms increments from 1 ms to
255 ms) for timed interrupt 1.

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SMB36 to SMB65: HSC0, HSC1, and HSC2 Register

As described in Table C-14, SMB36 through SM65 are used to monitor and control
the operation of high-speed counters HSC0, HSC1, and HSC2.

Table C-14 Special Memory Bytes SMB36 to SMB65

SM Byte Description
SM36.0 to
Reserved
SM36.4
SM36.5 HSC0 current counting direction status bit: 1 = counting up
SM36.6 HSC0 current value equals preset value status bit: 1 = equal
SM36.7 HSC0 current value is greater than preset value status bit: 1 = greater than
SM37.0 Active level control bit for Reset:
0= Reset is active high, 1 = Reset is active low
SM37.1 Reserved
SM37.2 Counting rate selection for quadrature counters:
0 = 4x counting rate; 1 = 1 x counting rate
SM37.3 HSC0 direction control bit: 1 = count up
SM37.4 HSC0 update the direction: 1 = update direction
SM37.5 HSC0 update the preset value: 1 = write new preset value to HSC0 preset
SM37.6 HSC0 update the current value: 1 = write new current value to HSC0 current
SM37.7 HSC0 enable bit: 1 = enable
SMB38 HSC0 new current value
SMB39 SMB38 is most significant byte, and SMB41 is least significant byte.
SMB40
SMB41
SMB42 HSC0 new preset value
SMB43 SMB42 is most significant byte, and SMB45 is least significant byte.
SMB44
SMB45
SM46.0 to
Reserved
SM46.4
SM46.5 HSC1 current counting direction status bit: 1 = counting up
SM46.6 HSC1 current value equals preset value status bit: 1 = equal
SM46.7 HSC1 current value is greater than preset value status bit: 1 = greater than
SM47.0 HSC1 active level control bit for reset: 0 = active high, 1 = active low
SM47.1 HSC1 active level control bit for start: 0 = active high, 1 = active low
SM47.2 HSC1 quadrature counter rate selection: 0 = 4x rate, 1 = 1x rate
SM47.3 HSC1 direction control bit: 1 = count up
SM47.4 HSC1 update the direction: 1 = update direction
SM47.5 HSC1 update the preset value: 1 = write new preset value to HSC1 preset
SM47.6 HSC1 update the current value: 1 = write new current value to HSC1 current

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Table C-14 Special Memory Bytes SMB36 to SMB65

SM Byte Description
SM47.7 HSC1 enable bit: 1 = enable
SMB48 HSC1 new current value
SMB49 SMB48 is most significant byte, and SMB51 is least significant byte.
SMB50
SMB51
SMB52 to HSC1 new preset value
SMB55 SMB52 is most significant byte, and SMB55 is least significant byte.
SM56.0 to
Reserved
SM56.4
SM56.5 HSC2 current counting direction status bit: 1 = counting up
SM56.6 HSC2 current value equals preset value status bit: 1 = equal
SM56.7 HSC2 current value is greater than preset value status bit: 1 = greater than
SM57.0 HSC2 active level control bit for reset: 0 = active high, 1 = active low
SM57.1 HSC2 active level control bit for start: 0 = active high, 1 = active low
SM57.2 HSC2 quadrature counter rate selection: 0 = 4x rate, 1 = 1x rate
SM57.3 HSC2 direction control bit: 1 = count up
SM57.4 HSC2 update the direction: 1 = update direction
SM57.5 HSC2 update the preset value: 1 = write new preset value to HSC2 preset
SM57.6 HSC2 update the current value: 1 = write new current value to HSC2 current
SM57.7 HSC2 enable bit: 1 = enable
SMB58 HSC2 new current value
SMB59 SMB58 is the most significant byte, and SMB61 is the least significant byte.
SMB60
SMB61
SMB62 HSC2 new preset value
SMB63 SMB62 is the most significant byte, and SMB65 is the least significant byte.
SMB64
SMB65

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SMB66 to SMB85: PTO/PWM Registers

As described in Table C-15, SMB66 through SMB85 are used to monitor and
control the pulse train output and pulse width modulation functions. See the
information on high-speed output instructions in Section 9.5 in Chapter 9 for a
complete description of these bits.

Table C-15 Special Memory Bytes SMB66 to SMB85

SM Byte Description
SM66.0 to
Reserved
SM66.3
SM66.4 PTO0 profile aborted;
0 = no error, 1 = aborted due to a delta calculation error
SM66.5 PTO0 profile aborted;
0 = not aborted by user command, 1 = aborted by user command
SM66.6 PTO0 pipeline overflow (cleared by the system when using external profiles,
otherwise must be reset by user); 0 = no overflow, 1 = pipeline overflow
SM66.7 PTO0 idle bit: 0 = PTO in progress, 1 = PTO idle
SM67.0 PTO0/PWM0 update the cycle time value: 1 = write new cycle time
SM67.1 PWM0 update the pulse width value: 1 = write new pulse width
SM67.2 PTO0 update the pulse count value: 1 = write new pulse count
SM67.3 PTO0/PWM0 time base: 0 = 1 µs/tick, 1 = 1 ms/tick
SM67.4 Update PWM0 synchronously:
0 = asynchronous update, 1 = synchronous update
SM67.5 PTO0 operation: 0 = single segment operation (cycle time and pulse count
stored in SM memory), 1 = multiple segment operation (profile table stored in
V memory)
SM67.6 PTO0/PWM0 mode select: 0 = PTO, 1 = PWM
SM67.7 PTO0/PWM0 enable bit: 1 = enable
SMB68 PTO0/PWM0 cycle time value (2 to 65,535 units of time base);
SMB69 SMB68 is most significant byte, and SMB69 is least significant byte.
SMB70 PWM0 pulse width value (0 to 65,535 units of the time base);
SMB71 SMB70 is most significant byte, and SMB71 is least significant byte.
SMB72 PTO0 pulse count value (1 to 232 -1);
SMB73 SMB72 is most significant byte, and SMB75 is least significant byte.
SMB74
SMB75
SM76.0 to
Reserved
SM76.3
SM76.4 PTO1 profile aborted;
0 = no error, 1 = aborted because of delta calculation error
SM76.5 PTO1 profile aborted;
0 = not aborted by user command, 1 = aborted by user command

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Table C-15 Special Memory Bytes SMB66 to SMB85

SM Byte Description
SM76.6 PTO1 pipeline overflow (cleared by the system when using external profiles,
otherwise must be reset by the user); 0 = no overflow, 1 = pipeline overflow
SM76.7 PTO1 idle bit: 0 = PTO in progress, 1 = PTO idle
SM77.0 PTO1/PWM1 update the cycle time value: 1 = write new cycle time
SM77.1 PWM1 update the pulse width value: 1 = write new pulse width
SM77.2 PTO1 update the pulse count value: 1 = write new pulse count
SM77.3 PTO1/PWM1 time base: 0 = 1 µs/tick, 1 = 1 ms/tick
SM77.4 Update PWM1 synchronously:
0 = asynchronous update, 1 = synchronous update
SM77.5 PTO1 operation: 0 = single segment operation (cycle time and pulse count
stored in SM memory), 1 = multiple segment operation (profile table stored in
V memory)
SM77.6 PTO1/PWM1 mode select: 0 = PTO, 1 = PWM
SM77.7 PTO1/PWM1 enable bit: 1 = enable
SMB78 PTO1/PWM1 cycle time value (2 to 65,535 units of the time base);
SMB79 SMB78 is most significant byte, and SMB79 is least significant byte.
SMB80 PWM1 pulse width value (0 to 65,535 units of the time base);
SMB81 SMB80 is most significant byte, and SMB81 is least significant byte.
SMB82 PTO1 pulse count value (1 to 232 -1);
SMB83 SMB82 is most significant byte, and SMB85 is least significant byte.
SMB84
SMB85

SMB86 to SMB94, and SMB186 to SMB194: Receive Message Control

As described in Table C-16, SMB86 through SMB94 and SMB186 through
SMB194 are used to control and read the status of the Receive Message
instruction.

Table C-16 Special Memory Bytes SMB86 to SMB94, and SMB186 to SMB194

Port 0 Port 1 Description

SMB86 SMB186 MSB
7
LSB
0

n r e 0 0 t c p Receive Message status byte

n: 1 = Receive message terminated by user disable command

r: 1 = Receive message terminated: error in input parameters or
missing start or end condition
e: 1 = End character received
t: 1 = Receive message terminated: timer expired
c: 1 = Receive message terminated: maximum character count achieved
p 1 = Receive message terminated because of a parity error

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Table C-16 Special Memory Bytes SMB86 to SMB94, and SMB186 to SMB194

Port 0 Port 1 Description

SMB87 SMB187 MSB LSB
7 0

n x y z m t bk 0 Receive Message control byte

n: 0 = Receive Message function is disabled.

1 = Receive Message function is enabled.
The enable/disable receive message bit is checked each time the
RCV instruction is executed.
x: 0 = Ignore SMB88 or SMB188.
1 = Use the value of SMB88 or SMB188 to detect start of
message.
y: 0 = Ignore SMB89 or SMB189.
1 = Use the value of SMB89 or SMB189 to detect end of
message.
z: 0 = Ignore SMW90 or SMB190.
1 = Use the value of SMW90 to detect an idle line condition.
m: 0 = Timer is an inter-character timer.
1 = Timer is a message timer.
t: 0 = Ignore SMW92 or SMW192.
1 = Terminate receive if the time period in SMW92 or SMW192
is exceeded.
bk: 0 = Ignore break conditions
1 = Use break condition as start of message detection
The bits of the message interrupt control byte are used to define the
criteria by which the message is identified. Both start of message and
end of message criteria are defined. To determine the start of a
message, either of two sets of logically ANDed start of message
criteria must be true and must occur in sequence (idle line followed
by start character, or break followed by start character). To determine
the end of a message, the enabled end of the message criteria is
logically ORed. The equations for start and stop criteria are given
below:
Start of Message = il * sc + bk * sc
End of Message = ec + tmr + maximum character count
reached
Programming the start of message criteria for:
1. Idle line detection: il=1, sc=0, bk=0, SMW90>0
2. Start character detection: il=0, sc=1, bk=0, SMW90
is a don’t care
3. Break Detection: il=0, sc=0, bk=1, SMW90
is a don’t care
4. Any response to a request: il=1, sc=0, bk=0, SMW90=0
(Message timer can be used to terminate receive if there is no
response.)
5. Break and a start character: il=0, sc=1, bk=1, SMW90
is a don’t care
6. Idle line and a start character: il=1, sc=1, bk=0, SMW90 >0
7. Idle line and start character (Illegal): il=1, sc=1, bk=0, SMW90=0
Note: Receive will automatically be terminated by an overrun or a
parity error (if enabled).
SMB88 SMB188 Start of message character

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Table C-16 Special Memory Bytes SMB86 to SMB94, and SMB186 to SMB194

Port 0 Port 1 Description

SMB89 SMB189 End of message character
SMB90 SMB190 Idle line time period given in milliseconds. The first character received
SMB91 SMB191 after idle line time has expired is the start of a new message. SM90
(or SM190) is the most significant byte and SM91 (or SM191) is the
least significant byte.
SMB92 SMB192 Inter-character/message timer time-out value (in milliseconds). If the
SMB93 SMB193 time period is exceeded, the receive message is terminated.
SM92 (or SM192) is the most significant byte, and SM93 (or SM193)
is the least significant byte.
SMB94 SMB194 Maximum number of characters to be received (1 to 255 bytes).
Note: This range must be set to the expected maximum buffer size,
even if the character count message termination is not used.

SMB98 and SMB99

As described in Table C-17, SMB98 and SMB99 give you information about the
number of errors on the expansion I/O bus.

Table C-17 Special Memory Bytes SMB98 and SMB99

SM Byte Description
SMB98 This location is incremented each time a parity error is detected on the
SMB99 expansion I/O bus. It is cleared upon power up, and by the user writing zero.
SMB98 is the most significant byte.

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SMB131 to SMB165: HSC3, HSC4, and HSC5 Register

As described in Table C-18, SMB131 through SMB165 are used to monitor and
control the operation of high-speed counters HSC3, HSC4, and HSC5.

Table C-18 Special Memory Bytes SMB130 to SMB165

SM Byte Description
SMB131 to
Reserved
SMB135
SM136.0 to
Reserved
SM136.4
SM136.5 HSC3 current counting direction status bit: 1 = counting up
SM136.6 HSC current value equals preset value status bit: 1 = equal
SM136.7 HSC3 current value is greater than preset value status bit: 1 = greater than
SM137.0 to
Reserved
SM137.2
SM137.3 HSC3 direction control bit: 1 = count up
SM137.4 HSC3 update direction: 1 = update direction
SM137.5 HSC3 update preset value: 1 = write new preset value to HSC3 preset
SM137.6 HSC3 enable bit: 1 = enable
SM138 to HSC3 new current value: SM138 is most significant byte and SM141 is
SM141 least significant byte
SM142 to HSC3 new preset value: SM142 is most significant byte and SM145 is the
SM145 least significant byte
SM146.0 to
Reserved
SM146.4
SM146.5 HSC4 current counting direction status bit: 1 = counting up
SM146.7 HSC4 current value is greater than preset value status bit: 1 = greater than
SM147.0 Active level control bit for Reset:
0 = Reset is active high, 1 = Reset is active low
SM147.1 Reserved
SM147.2 Counting rate selection for quadrature counters:
0 = 4x counting rate, 1 = 1x counting rate
SM147.3 HSC4 direction control bit: 1 = count up
SM147.4 HSC4 update direction: 1 = update direction
SM147.5 HSC4 update preset value: 1 = write new preset value to HSC4 preset
SM147.6 HSC4 update current value: 1 = write new current value to HSC4 current
SM147.7 HSC4 enable bit: 1 = enable
SMB148 to HSC4 new current value: SM148 is most significant byte and SM151 is
SMB151 least significant byte
SMB152 to HSC4 new preset value: SM152 is most significant byte and SM155 is least
SMB155 significant byte

S7-200 Programmable Controller System Manual

C79000-G7076-C233-01 C-15
Special Memory (SM) Bits

Table C-18 Special Memory Bytes SMB130 to SMB165

SM Byte Description
SM156.0 to
Reserved
SM156.4
SM156.5 HSC5 current counting direction status bit: 1 = counting up
SM156.6 HSC5 current value equals preset value status bit: 1 = equal
SM156.7 HSC5 current value is greater than preset value status bit: 1 = greater than
SM157.0 to
Reserved
SM157.2
SM157.3 HSC5 direction control bit: 1 = count up
SM157.4 HSC5 update direction: 1 = update direction
SM157.5 HSC5 update preset value: 1 = write new preset value to HSC5 preset
SM157.6 HSC5 update current value: 1 = write new current value to HSC5 current
SM157.7 HSC5 enable bit: 1 = enable
SMB158 to HSC5 new current value: SM158 is most significant byte and SM161 is
SMB161 least significant byte
SMB162 to HSC5 new preset value: SM162 is most significant byte and SM165 is least
SMB165 significant byte

SMB166 to SMB194: PTO0, PT1 Profile Definition Table

As described in Table C-19, SMB166 through SMB194 are used to show the
number of active profile steps and the address of the profile table in V memory.

Table C-19 Special Memory Bytes SMB166 to SMB194

SM Byte Description
SMB166 Current entry number of the active profile step for PTO0
SMB167 Reserved
SMB168 V memory address of the profile table for PTO0 given as an offset from V0.
SMB169 SM168 is the most significant byte of the address offset
SMB170 to
Reserved
SMB175
SMB176 Current entry number of the active profile step for PTO1
SMB177 Reserved
SMB178 to V memory address of the profile table for PTO1 given as an offset from V0.
SMB179 SM178 is the most significant byte of the address offset
SMB180 to
Reserved
SMB194

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