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    BITS Pilani 2nd year digital design handout

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    BITS Pilani 2nd year digital design handout

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    BITS Pilani 2nd year digital design handout

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    3 views3 pages

    DD

    Uploaded by

    Ujjwal Jain
    BITS Pilani 2nd year digital design handout

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 3

    BITS, Pilani- K.K.

    Birla Goa Campus


    First Semester 2024-25
    Course Handout (Part-II)

    In addition to Part I (General Handout for all the courses appended to the time table), this portion
    gives further specific details regarding the course.

    Course No. : ECE/EEE/INSTR F215


    Course Title : Digital Design
    Instructor-In-charge : Anita Agrawal
    Team of Instructors : Tushar Sakorikar, Souvik Ghosh
    Course Description: This course covers the topics on logic circuits and
    minimization, Digital ICs, Combinational and Sequential logic
    circuits, State table and State diagrams, Programmable Logic
    devices, Algorithmic State Machines.

    Scope and Objective: The objective of the course is to impart knowledge of the
    tools for the design of digital circuits and to provide methods and
    procedures suitable for a variety of digital design applications.
    The course introduces fundamental concepts of Computer
    Organization too. It also includes laboratory practice using
    for combinational and sequential circuits. The course involves
    simulation of combinational and sequential circuits using Verilog
    HDL.

    Text Books:
    T1: M.Morris Mano and Michael D.Ciletti, “ Digital Design”, PHI, 4th Edition

    Reference Books:
    R1 Donald D. Givone , “Digital Principles and Design”, TMH 2003
    R2 Samir Palnitkar, “Verilog HDL”, Pearson Education.

    Course Plan:
    Lect. Reference to Text
    Learning Objectives Topics to be covered
    No. Book
    Introduction to Digital
    Systems and Digital Systems, Digital ICs 1.1; 1.9; 2.8, 2.9,
    1
    Characteristics of Digital 10.1, 2
    ICs.
    Boolean functions, Canonical
    Boolean algebra and logic forms, Standard forms,
    2-4 2.2-2.7, 3.8
    gates conversion between different
    forms
    Different Number systems such 1.2-7
    Codes, Number Systems as binary, octal etc. and codes To be covered in
    such as BCD, Excess-3 etc.. tut
    K-Maps (2,3,4 & 5 variables),
    5-7 Simplification of Boolean
    Different types & levels of 3.1 to 3.7, 3.9
    functions
    implementations.
    Simulation and Synthesis Hardware Description
    8 3.11
    basics Language (HDL)
    Combinational Logic,
    9-10 Adders, Subtractors Multipliers 4.1 - 4-7
    Arithmetic circuits
    Comparators, Decoders,
    11-13 MSI Components 4.8 to 4.11
    Encoders, MUXs, DEMUXs
    4.12 to be covered
    HDL HDL for combinational logic
    in tut
    14-15 Sequential Logic Latches, Flip-Flops & 5.1 to 5.4
    Characteristic tables
    Analysis of clocked sequential
    Clocked Sequential
    16-19 circuits, state diagram and 5.5, 5.7, 5.8
    Circuits
    reduction
    Shift registers, Synchronous & 6.1 to 6.5
    20-23 Registers & Counters
    Asynchronous counters
    5.6 to be covered
    HDL HDL for sequential circuits
    in tut
    24-27 Memory and PLDs RAM, ROM, PLA, PAL, FPGA 7.1-7.3 7.5 to 7.7
    TTL, MOS Logic families and
    Digital Integrated 10.3-10.5, 10.7 to
    28-31 their characteristics
    Circuits 10.9
    Design of Asynchronous Asynchronous Sequential Logic 9.1 – 9.4
    32-35
    Circuits.
    Design of Digital Algorithmic State Machines
    36-39 Systems using software R1: Chapter 8
    approach
    Multiplication and division
    40-42 Algorithms Class notes
    Algorithm

    Evaluation Scheme:
    Component Duration Weightage Date & Time CB/OB
    Midsem 1.5 hrs. 25% 3/10/24 (9:30 to 11:00 AM) CB
    Quiz ** 10% 26/10/24 CB
    Comprehensive Examination 3 hrs. 35% 02/12/24 (FN) CB
    Lab:
    scheduled
    20% Verilog Quiz on 16/11/24
    Laboratory+Verilog Quiz hrs.as per OB
    timing 9:00 AM.-1 PM.
    time-table,
    Verilog: **
    Lab Comprehensive ** 10% Refer Lab Schedule CB

    ** To be announced later

    Laboratory
    S.No. Name of Experiment
    1. FAMILIARIZATION WITH BENCH EQUIPMENTS
    2. IMPLEMENTATION OF BOOLEAN FUNCTIONS USING LOGIC GATES
    3. ADDERS AND SUBTRACTORS
    4. BCD ADDER AND BCD-7-SEGMENT DECODER/DRIVER
    5. DECODERS/ DEMULTIPLEXERS, MULTIPLEXERS AND COMPARATORS
    6. LATCHES & FLIP-FLOPS
    7. STUDY OF COUNTERS
    8. SHIFT REGISTERS
    9. SEQUENCE DETECTOR

    Chamber Consultation Hour: To be announced in class

    Notices: All notices and announcements will be posted in the course folder on moodle.

    Make-up Policy: Make-up in any of the components may be granted only in extremely genuine
    cases (admitted to hospital) and with prior permission.
    INSTRUCTOR-IN-CHARGE

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