MIT Open Access Articles

Design Methodology for a Very High

Frequency Resonant Boost Converter

The MIT Faculty has made this article openly available. Please share
how this access benefits you. Your story matters.

Citation: Burkhart, Justin M., Roman Korsunsky, and David J. Perreault. “Design Methodology
for a Very High Frequency Resonant Boost Converter.” IEEE Trans. Power Electron. 28, no. 4
(n.d.): 1929–1937.

As Published: http://dx.doi.org/10.1109/TPEL.2012.2202128

Publisher: Institute of Electrical and Electronics Engineers (IEEE)

Persistent URL: http://hdl.handle.net/1721.1/87098

Version: Author's final manuscript: final author's manuscript post peer review, without
publisher's formatting or copy editing

Terms of use: Creative Commons Attribution-Noncommercial-Share Alike

 IEEE Transactions on Power Electronics, Vol. 28, No. 4, pp. 1929-1937, April 2013.

Design Methodology for a Very High Frequency

Resonant Boost Converter
Justin M. Burkhart∗ , Roman Korsunsky† , and David J. Perreault‡
∗ MassachusettsInstitute of Technology
Laboratory for Electromagnetic and Electronic Systems
77 Massachusetts Avenue
Cambridge, Massachusetts 02139
Email: justin.burkhart@gmail.com

† Texas
Instruments
Email: roman korsunsky@ti.com

‡ Massachusetts Institute of Technology

Email: djperrea@mit.edu

Special Issue on Power Electronics, 2012 and/or through transistor layout optimization [16]. Resonant
rectification can be employed to mitigate rectifier switching
Abstract—This document introduces a design methodology for loss [8], [9], and [18]. Once these frequency dependent device
a resonant boost converter topology that is suitable for operation losses have been minimized, the converter can then be operated
at very high frequencies. The topology we examine features a low
parts count and fast transient response, but suffers from higher at a frequency high enough to use air core or low permeability
device stresses compared to other topologies that use a larger RF core inductors to avoid the losses from high permeability
number of passive components. A numerical design procedure magnetic materials.
is developed for this topology that does not rely on time-domain This concept has been successfully demonstrated for boost
simulation sweeps across parameters. This allows the optimal conversion at frequencies up to 110MHz using a resonant
converter design to be found for a particular main semiconductor
switch. If an integrated power process is used where the designer boost Φ2 converter topology in [6], [7], and [10]. This topol-
has control over layout of the semiconductor switch, the optimal ogy uses a multi-resonant network to shape the switch’s drain-
combination of converter design and semiconductor layout can to-source voltage waveform to approximate a square wave with
be found. To validate the proposed converter topology and a peak value of 2VIN (under ideal conditions). In this paper an
design approach, a 75 MHz prototype converter is designed and alternative resonant boost converter topology is explored that
experimentally demonstrated. The performance of the prototype
closely matches that predicted by the design procedure, and uses fewer passive components but suffers from a higher peak
the converter achieves good efficiency over a wide input voltage drain-to-source voltage. We develop a design procedure for
range. this topology that readily yields necessary component values.
Index Terms - DC-DC power converters, Power transistors, Unlike previous design methodologies for similar topologies
RLC circuits, Tuned circutis, Schottky diodes. [11],[12], the procedure introduced here is based on direct
analysis of the topology and does not rely on lengthy time-
I. I NTRODUCTION domain simulation sweeps across circuit parameters to identify
Increasing the switching frequency of DC/DC converters desirable design points.
has the benefits of requiring less passive energy storage Section II of the paper presents an overview of the topology
and providing improved transient performance. Since passive and how it relates to previous RF converter designs. Section III
components typically dominate converter size, increasing the of the paper details the proposed design method and illustrates
switching frequency is a crucial step in the development of how it is applied to design a converter. Section IV validates
a fully integrated or co-packaged power converter [1] and the proposed design methodology and presents experimental
[3]. Among the challenges standing in the way of such results from a 75 MHz converter. The performance of the
developments, however, are loss mechanisms that grow with prototype design is shown to closely match that predicted by
switching frequency [2]. Switching loss can be mitigated by the design procedure. Finally, section V concludes the paper.
using a circuit topology that operates with zero-voltage soft-
switching to avoid both capacitive discharge and the overlap II. R ESONANT B OOST C ONVERTER T OPOLOGY
of voltage and current at the switching instants. Gating loss A schematic of the power stage of the proposed converter
that arises from charging and discharging the gate capacitor is shown in Figure 1, and idealized waveforms illustrating
each cycle can be reduced by using a resonant gate driver to its operation are shown in Figure 2. This converter topology
recover a portion of the energy stored in the gate [2],[4]-[6], operates with zero voltage switching by tuning the resonant
 IEEE Transactions on Power Electronics, Vol. 28, No. 4, pp. 1929-1937, April 2013.

elements (LF , LR , CE , and CR ) such that when the switch is vC (t) vD(t)
opened, the drain-to-source voltage of the switch will naturally 3

Normalized Voltage
ring up and then back to zero half of a switching period later.
The converter is designed to operate with fixed switching 2
frequency and duty cycle. This makes available the use of 1
highly efficient resonant gate drivers when desired. While
varying the frequency or duty cycle is not used for control, an 0
on-off modulation scheme can be employed in which the entire −1
converter is switched on and off at a modulation frequency that 0 5 10 15 20 25 30
Time (ns)
is much less than the switching frequency of the converter [4]-
[7],[12],[13], and [24]. i L (t) i R (t)

It should be noted that aside from the important aspects 2

Normalized Current
of component values and control, the circuit of Figure 1
is topologically equivalent to the ZVS multiresonant boost 1

converter of [14] and to the resonant boost converter of [13].

0
The difference in design between the converter of [14] and
here is quite large owing to major differences in control
−1
(constant on-time variable frequency vs. burst mode control) 0 5 10 15 20 25 30
and the resulting difference in the choice of component values. Time (ns)

The design here is more similar to that of [13], but differs

substantially from both [14] and [13] in that the inductor Fig. 2. Idealized steady-state waveforms illustrating the operation of the
LF in Figure 1 is a resonant inductor rather than a simple converter shown in Figure 1. vC (t) is normalized to the VIN , vD (t) is
normalized to VOUT , and the currents are normalized to the converter’s input
choke as in [14] and [13]. This design choice provides much DC current.
faster response under on-off control than is achievable with a
choke inductor and results in different design considerations
and component selections. for a particular converter design [16]. However, previous
design methods for such circuits have not been sufficiently
LF LR simple that one can easily vary both the device layout and the
converter design to find the best possible combination. Enabled
+ +
by the simplicity of this converter topology, a design procedure
+ iL(t) iR(t) +
vC(t) vD(t) is developed here that aims to address these challenges.
VIN − CE CR − VOUT With four energy storage elements, the converter is de-
- - scribed by fourth order differential equations. Additionally,
since the converter contains two switching devices, there are
a four different circuit configurations possible. Thus, a com-
Fig. 1. Power section schematic of the proposed boost converter prehensive mathematical description of the converter requires
four sets of fourth order differential equations. This is further
complicated by the fact that the switching times of the diode
III. D ESIGN M ETHODOLOGY are unknown. Clearly, deriving a complete set of closed form
Here we develop a design procedure for the proposed equations to directly describe the converter is a cumbersome
converter circuit that both provides insight into the converter’s and unfruitful task. For this reason, the simplifying assumption
operation and is straight forward to use. Single-switch resonant is made that the rectifier’s LC tank, formed by LR and CR ,
power converters have often been designed through an iterative is high Q and the current in inductor LR , labeled iRECT , is
modeling approach, in which one starts from some approxi- sinusoidal with a DC offset.
mate component values and searches for good designs through
a series of time-domain simulations sweeping parameters (e.g. POUT
iRECT = IAC sin (ωs t + φ1 ) + (1)
using SPICE simulations [12],[13],[24]). This approach is VOUT
workable, especially for an experienced designer with good This allows the inverter and rectifier to be separated for
knowledge of a particular topology. However, due to the large analysis. The inverter design is then found by replacing the
number of parameters that can be varied, it is difficult for the rectifier with a sinusoidal current source. Similarly, the rectifier
designer to know if they have reached the optimal design. We design can then be found by replacing the inverter with a
seek to remedy this issue here. Additionally, when designing a sinusoidal voltage source. Making this assumption simplifies
converter where the main switching device will be fabricated the problem to the point where a converter solution is readily
from an integrated power process, the designer has the ability obtained, but at the cost of the accuracy. Since the current
to change the layout of the device to vary the parasitics. iRECT is actually not purely sinusoidal, there will be some
Methods have been developed to find the optimal device layout error in the solution. Typically the rectifier has a modest
 IEEE Transactions on Power Electronics, Vol. 28, No. 4, pp. 1929-1937, April 2013.

loaded Q, and the error is small enough such that the designer where
can easily make small corrections to the resulting component r 2
values when simulating the converter in SPICE. 1 LF (ωs /ωo )
ωo = √ , Zo = , and ro = 2
LF CE CE (ωs /ωo ) − 1

LF iRECT From Equation 4 we see that there are five unknown

quantities that must be found: the resonant angular frequency
+
iC(t) and characteristic impedance of LF and CE (ωo and Zo ), the
iL(t) magnitude and phase of the rectifier current (IAC and φ1 ), and
+ v C(t) the initial current in LF (iL (0)). (Hereafter, we refer to angle
VIN − CE φ1 as the “outphasing angle”.) To solve for these unknowns,
design constraints are applied to the system:
- 1) Since average power is only delivered by DC current
from the source, the DC current in LF is constrained
by conservation of energy. (Averages are denoted with
Fig. 3. Schematic of the inverter used for analysis with the rectifier modeled
as a current source of value iRECT angled brackets, hi.)

POUT
hiL (t)i = (5)
A. Inverter Analysis VIN
In this analysis, the duty cycle of the inverter is set to 50% (a
common design choice). This is not a fundamental limit, and where
is imposed in part to simplify the converter’s equations. The 1
Z t
reader can easily expand the design approach to accommodate iL (t) = (VIN − vC (t)) dt + iL (0) (6)
LF 0
arbitrary duty cycles. A schematic of the inverter is shown
in Figure 3. With the duty cycle of a half, the time period 2) The inverter must operate in periodic-steady-state
0 ≤ t < TS /2 is defined as the period with the switch turned
• The average voltage across LF must be 0.
off, and TS /2 ≤ t < TS as the period with the switch on.
The analysis starts at t = 0, when the switch has just turned
off. The node equations in this time period (with the switch hvC (t)i = VIN (7)
off) form a second order differential equation for the voltage
vC (t) . • The average current through CE must be 0.

d2 vC (t) hiC (t)i = 0 (8)

LF CE + vC (t) = VIN − ωs IAC LF cos (ωs t + φ1 ) (2)
dt2
The general solution to this equation is: where

ωs LF IAC 
vC (t) = 2
cos (ωs t + φ1 ) iL (t) − iRECT 0 ≤ t < TS /2
ωs LF CE − 1 (3) iC (t) = (9)
√ √ 0 TS /2 ≤ t < TS
+ C1 e−jt/ LF CE + C2 ejt/ LF CE + VIN
Since the capacitor does not conduct any current
where C1 and C2 are constants. To solve for these constants,
when the switch is on and had an initial voltage of 0,
two initial conditions are required. The capacitor voltage at
this constraint is equivalent to setting the capacitor
t = 0+ is known to be 0 since the switch was turned on at
voltage to 0 at the switching instant. Thus, a separate
t = 0− . The initial inductor current is not known, and the
constraint for zero-voltage switching is not required.
constants are found in terms of the initial inductor current,
iL (0) , resulting in the following equation. Application of these constraints to the circuit node equations
results in three non-linear equations. Since there are five

POUT
 unknown quantities and only three constraints, the system has
vC (t) = Zo (ro − 1) IAC sin φ1 + iL (0) − sin (ωo t) two free variables. An intuitive choice to illuminate of the
VOUT
  design space is to leave ωo and φ1 unconstrained, and solve
Zo ωs for the remaining unknown quantities (LF , CE , and iL (0))
− ro IAC cos φ1 + VIN cos (ωo t)
ωo numerically in MATLAB. Figure 4 shows the solved values
Zo ωs of LF and CE as a function of the current out-phasing angle φ1
+ ro IAC cos (ωs t + φ1 ) + VIN
ωo and the inverter’s resonant frequency ωo for a converter with
for 0 ≤ t ≤ TS /2 input and output voltages of 12 and 30 Volts, an output power
(4) of 7 Watts, and a switching frequency of 75 MHz.
 IEEE Transactions on Power Electronics, Vol. 28, No. 4, pp. 1929-1937, April 2013.

ωo/ωs=0.2 ωo/ωs=0.6 ωo/ωs=0.85 ωo/ωs=0.95 For analysis the times that the diode turns on and off in a
5
10 cycle are labeled ton and toff .
4
The following differential equation describes the rectifier
10 voltage, vD (t) , for the time period with the diode off, toff ≤
L F (nH)

3
10
t < ton + TS :
2
10
d2 vD (t)
1 LR CR + vD (t) = VIN + VAC sin (ωs t + φ) (11)
10 dt2
−1 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1
Ф1 − Outphasing Angle (rad) The general solution to this differential equation is:
3
10 VAC
vD (t) = 2 sin (ωs t + φ)
1 − (ωs /ωr ) (12)
2
10 + C1 e(−jωr t) + C2 e(jωr t) + VIN
C E (pF)

1
where C1 and C2 are constants. With the rectifier, there are
10
two known initial conditions that occur when the diode turns
off.
0
10 VD (toff ) = VOUT (13)
−1 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1
Ф1 − Outphasing Angle (rad)
IR (toff ) = 0 (14)
Fig. 4. Solved values of LF and CE as a function of the current out-phasing Upon applying these initial conditions the rectifier voltage
angle φ1 and the inverter’s resonant frequency ωo for a converter with an becomes:
input and output voltage of 12 and 30 Volts, an output power of 7 Watts, and
a switching frequency of 75 MHz. vD (t) = (rVAC sin (ωs toff + φ) + VOUT − VIN ) cos (ωr (t − toff ))
+ r (ωs /ωr ) VAC cos (ωs toff + φ) sin (ωr (t − toff ))
B. Rectifier Analysis − rVAC sin (ωs t + φ) + VIN
(15)
Similar to the approach taken for the inverter, the rectifier
design is determined by replacing the inverter with a sinusoidal where
voltage source with a DC offset, labeled vINV and shown in
r
1 LR 1
Figure 5. ωr = √ , ZR = , and r = 2
LR CR CR (ωs /ωr ) − 1
vINV = VAC sin(ωs t + φ) + VIN (10)
From equation 15 it is found that the rectifier has four
VAC and φ are the fundamental component and phase of unknown quantities: the resonant frequency and characteristic
vC (t) (the drain-to-source voltage of the inverter). impedance of LR and CR (ωr and ZR ), and the times that the
diode turns on and off (ton , and toff ). As with the inverter,
design constraints are applied to the voltages and currents in
LR the circuit to solve for the unknown values.
1) Since average power is only delivered to the load by
iCR(t) + DC current, the DC current in LR is constrained by
iR(t) conservation of energy.
v D(t) + POUT
v INV CR − hiR (t)i =
VOUT
(16)
VOUT
where
- Z t
1
iR (t) = (VAC − vD (t)) dt
LR toff (17)
Fig. 5. Schematic of the rectifier used for analysis with the inverter modeled for toff < t < toff + TS
as a voltage source of value vINV .
2) The rectifier must operate in Periodic Steady State
Unlike the inverter, the rectifier’s duty cycle is unknown. • The average inductor voltage must be 0.
When the diode turns on, the voltage vD (t) is held at VOUT ,
and there is no current in the capacitor CR . The diode turns hvD (t)i = VIN (18)
off when iR (t) crosses zero, reversing the direction of current • The average capacitor current must be 0.
in the diode. While the diode is off the resonant circuit rings
until vD (t) reaches VOUT again and the diode turns back on. hiCR (t)i = 0 (19)
 IEEE Transactions on Power Electronics, Vol. 28, No. 4, pp. 1929-1937, April 2013.

where ωo/ωs=0.2 ωo/ωs=0.6 ωo/ωs=0.85 ωo/ωs=0.95

d
iCR (t) = CR vD (t) (20) 3.5
dt
3) The phase of the fundamental component of iR (t) is 3
constrained by the inverter
Application of these constraints results in four non-linear
2.5

RMS AC Normalized Current

equations. Unlike the inverter, the rectifier has no free vari-
ables, and the resulting equations are solved using numerically LR Cu
2 rrent
in MATLAB for each inverter solution. Figure 6 shows the
solved values of LR and CR that correspond with the inverter
solution of Figure 4. 1.5

ωo/ωs=0.2 ωo/ωs=0.6 ωo/ωs=0.85 ωo/ωs=0.95 1

3
10
LF Curr
0.5 ent
L R (nH)

2
10
0
−1 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2
Ф1 − Outphasing Angle (rad)
1
10
−1 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1
Ф1 − Outphasing Angle (rad) Fig. 7. RMS of the AC component of the current carried by the converter’s
inductors. LF current is normalized to the converter’s input DC current and
2 LR current is normalized to the converter’s output DC current.
10

has a significant series resistance component, and as a result,

C R (pF)

1
10 represent a non-negligible loss component in converter’s effi-
ciency budget. From these figures we see that it is desirable to
operate the inverter as in-phase with the rectifier as possible
0 to reduce circulating currents.
10
−1 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1
Ф1 − Outphasing Angle (rad) Furthermore, in addition to zero-voltage switching, a de-
sirable characteristic of the so-called “Class-E” switching
waveform is for the switch’s drain-to-source voltage have zero
Fig. 6. Solved values of LR and CR that correspond with the inverter solution
of Figure 4 for a converter with an input and output voltage of 12 and 30
derivative at the switching turn-on instant. This is occurs when
Volts, an output power of 7 Watts, and a switching frequency of 75 MHz. the capacitor CE has zero current at the switching instant.
Using the direct converter solution outlined here, this condition
is easily plotted across the entire design space as shown
C. Converter Solution in Figure 10. From this plot we observe that increasing
A major advantage to having a mathematical description of the resonant frequency of the inverter, ωo , has the effect of
the converter is visibility of the entire design space. In addition allowing this condition to be met with the inverter tuned more
to the component values plotted in the previous sections, the in-phase with the rectifier. This is an important aspect of the
converter solution also includes all of the converter’s currents converter design space which implies that there is a value of ωo
and voltages. that optimizes efficiency. Therefore using a resonant inductor
Figure 7 shows the current carried by the converter’s in- rather than a simple choke inductor (as in a conventional Class-
ductors. From this plot we make a few observations: first, E circuit) results in a more efficient converter design. Figure 10
tuning the inverter more in-phase with the rectifier allows the also shows us that tuning the inverter further in-phase than the
power to be delivered with a smaller currents, thus implying a point where the “Class-E” switching waveforms are obtained
more efficient transfer, and second, increasing the resonant results in substantial increases in peak voltage stress. This,
frequency of the inverter increases the AC component of combined with the fact that the derivative of the drain-to-
current in LF and reduces the rectifier current which indicates source voltage is positive at the switching instant demands
there will be an optimal value where losses are minimized. that the drain-to-source voltage be negative for a portion of
Figures 8 and 9 show the device and capacitor currents. the switching period. Practical switching devices are unable to
Currents carried by devices in their on-state are labeled block negative voltages and these tuning points are not used.
conduction currents, and currents carried by capacitors are Additionally, the sinusoidal assumption that was utilized
labeled displacement currents. Displacement currents are at to separate the inverter and rectifier into tractable problems
least partially carried by device parasitic capacitance which does so at the cost of solution accuracy. To demonstrate this
 IEEE Transactions on Power Electronics, Vol. 28, No. 4, pp. 1929-1937, April 2013.

ωo/ωs=0.2 ωo/ωs=0.6 ωo/ωs=0.85 ωo/ωs=0.95

ωo/ωs=0.2 ωo/ωs=0.6 ωo/ωs=0.85 ωo/ωs=0.95 0.5

Capacitor Current @ ton

1.6
0

1.4
−0.5

1.2
Normalized RMS Current

−1
−1 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2
Ф1 − Outphasing Angle (rad)
1 Conduc
tio n Curren
t

Normalized Peak Voltage Stress

5

0.8
4.5

Dis
pla 4
0.6 cem
en
tC
urr
en 3.5
t
0.4
3
−1 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2
Ф1 − Outphasing Angle (rad)
0.2
−1 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2
Ф1 − Outphasing Angle (rad)
Fig. 10. The upper figure shows the current through CE at the switching
turn on instant normalized to the input DC current. The lower figure shows
Fig. 8. Inverter switch and capacitor RMS currents normalized to the the peak device voltage normalized to the converter’s input voltage.
converter’s input DC current. Conduction current is carried by the device’s
channel (an through its on-state resistance), and displacement current is carried
by the parallel combination of the switch’s drain-to-source capacitance and
any additional capacitance in parallel with it.
effect, a converter design is selected from Figures 4 and 6
and simulated in SPICE. The SPICE output is plotted with
the solved waveforms in Figure 11. While the two waveform
sets do not match exactly, the error is small enough such that
ωo/ωs=0.2 ωo/ωs=0.6 ωo/ωs=0.85 ωo/ωs=0.95
it can be easily corrected through a narrow parameter sweep
while simulating in SPICE.
3

50
V C(t)
2.5 40
V D(t)
30
Normalized RMS Current

2 20
Voltage (Volts)

10
Conducti
on Current
1.5 0
Dis
pla −10
cem
e nt C
u rre
nt −20 SPICE
1
−30 Methodology

−40
0 5 10 15 20 25
0.5 Time (ns)
−1 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2
Ф1 − Outphasing Angle (rad)
Fig. 11. Comparison of converter waveforms as calculated from the design
methodology (solid) and as simulated in SPICE (dashed).
Fig. 9. Rectifier diode and capacitor RMS currents normalized to the
converter’s output DC current. Conduction current is carried by the diode’s
forward voltage, and displacement current is carried by the parallel combi-
nation of the diode’s junction capacitance and any additional capacitance in
D. Device Layout Optimization
parallel with it. Additionally, with all of the converter’s voltage and current
waveforms described mathematically, the losses in the circuit
 IEEE Transactions on Power Electronics, Vol. 28, No. 4, pp. 1929-1937, April 2013.

can be estimated. A loss model for each component in the ωo/ωs=0.2 ωo/ωs=0.6 ωo/ωs=0.85 ωo/ωs=0.95
circuit must be compiled. With these models the converter 0.1

Normalized Device Loss

losses can then be calculated for the entire design space and 0.08
then the best design chosen. If the semiconductor devices are Hard Gating
0.06
integrated, then their layout can be optimized for a particular
converter design. Thus, it is not necessary to use a single 0.04
switch design to calculate loss. Rather, for each design point, Resonant Gating
0.02
the optimal switch layout can be calculated, and then the
0
converter losses evaluated. −1 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2
Ф1 − Outphasing Angle (rad)
For example, a simplified model of a MOSFET that includes
the parasitic components that are important to RF operation is

Optimal Device Width (mm)

shown in Figure 12 [16]. 50

40 Resonant Gating

30

20 Hard Gating

−1 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2

Ф1 − Outphasing Angle (rad)

Fig. 13. Device optimization result across the entire converter design space.
The upper figure shows the total transistor device loss normalized to output
power for hard gating (solid) and sinusoidal resonant gating (dashed). The
lower figure shows the optimal device width. Results are for a representative
integrated BCD transistor process suited to the design space in question.
Fig. 12. Simplified MOSFET model showing device parasitics that are
important to converter operation at radio frequencies.
IV. E XPERIMENTAL R ESULTS
To optimize the device, its parasitic components are pa-
rameterized by its geometry, and then space bounded by the A prototype power stage was constructed to evaluate this
process design rules and the available chip area is searched converter topology and design approach. The design was
to find the device layout that results in the least amount of targeted at the general requirements of an LED driver for au-
loss. (Reference [16] explores this approach in detail, but tomotive applications, but as a first-generation test system was
without the analytical models of converter behavior available not held to all applicable specifications. LCD Backlights and
here.) When varying the device size, three primary device other LED applications often have similar drive requirements.
losses trade with each other: gating loss, conduction loss, and Aiming to validate the design methodology, the prototype was
displacement loss. For sinusoidal resonant gating, the total constructed with the same specifications used in the converter
device loss is given by: solution presented in the previous section, summarized in
Table I. The switching frequency of 75MHz was chosen to
demonstrate the highest switching frequency that the converter
PTOT =2RISS (πVG,AC fSW CISS )2
2 architecture can achieve while meeting a target efficiency near
(21)

IDISP,RMS 85%, given the semiconductor process that was used; this
+ C2OSS ROSS + I2COND,RMS RDS
CTOT general frequency range has been found to be effective in other
Thus, by increasing the size of the device, the conduction designs as well (e.g., [2], [6], and [19]).
loss is reduced, but the gating loss and displacement loss
Vin Vout Pout Fs
are increased. When designing a converter using the typical 12V 30V 7W 75MHz
iterative modeling approach in which converter designs are
TABLE I
found using time-domain simulations sweeping parameters, TARGET CONVERTER SPECIFICATIONS FOR THE EXPERIMENTAL
the designer would use values of IDISP,RMS and ICOND,RMS that IMPLEMENTATION .
were found from simulation for the device optimization (as
developed in [16]). With the design methodology proposed
here, IDISP,RMS and ICOND,RMS are described mathematically. A custom LDMOS device was optimized and fabricated for
This enables the design optimization to be run for each design the prototype. It has an equivalent drain-to-source capacitance
point with little added effort. Figure 13 shows the result of of approximately 34 pF and an on-state resistance of approx-
such an optimization: transistor device losses (normalized as imately 330 mOhms. Additionally, it was chosen to used the
a fraction of the output power) and optimal device size are Fairchild S310 silicon Schottky diode for the rectifier device.
plotted across the entire design space. This device is relatively oversized for the current rating of
 IEEE Transactions on Power Electronics, Vol. 28, No. 4, pp. 1929-1937, April 2013.

the converter, owing to limits on available device sizes among based on the ripple at the on/off modulation frequency. The
discrete Schottky diodes that have been found to operate well size of this filter capacitor can still be significantly smaller
under resonant operation at very high frequencies. (It has been than for conventional converters having switching frequencies
observed in our laboratory that a degree of over-sizing is often on the order of the modulation frequency, because the ca-
needed to preserve low diode conduction losses under VHF pacitor in the VHF converter needn’t be sized for absorbing
operation [17], but this represents a much greater degree of inductor energy or supporting the output during transients [2].
over-sizing than we would ideally select.) Likewise, for simplicity we have employed coreless inductors.
It is important to note that device parasitics can greatly With recently-available high-frequency magnetic materials and
constrain the available design space. In this case, the S310 has designs, however, significant miniaturization of the inductors
an equivalent reverse biased junction capacitance of approxi- is likely possible [20], [21], and [22]. Nonetheless, as recent
mately 55 pF. This capacitance is effectively in parallel with work in a similar design space has shown, even with coreless
CR at AC, since the output capacitor acts as an AC short. Note magnetics, resonant VHF designs can achieve considerable
that with all capacitance provided by the parasitic capacitance reductions in overall passive component size and mass as
of the diode, any diode package parasitic inductance can compared to conventional PWM converters [2].
effectively be absorbed into LR . From Figure 6 we see that For experimental simplicity, the prototype converter em-
this limits our choice of φ1 , the converter’s out-phasing angle, ployed a hard-switched gate drive based on the Fairchild
to be less than around -1 radian. Had a diode of the same NC7WZ04 discrete inverter, as indicated in Figure 16. We
characteristic as the S310 with a smaller device area been did not focus on the details of optimizing the gate drive,
available, then the converter could have been designed with as successful low-loss resonant VHF gate drivers have been
the inverter and rectifier more in phase. This would allow the demonstrated in many of the cited references, including [4],
converter to deliver the same power with smaller currents and [6], [7], [10], [11], [12], [17], and [23].
achieve an overall reduction in loss. This suggests that over- Figure 17 shows measured converter waveforms and a com-
sizing of devices, whether due to availability or conservatism, parison to simulated SPICE waveforms. The close agreement
has a major penalty on performance, and that there is an of the waveforms validates the operation of the prototype.
advantage to using integrated devices whose size can be Output power and open loop efficiency over the input voltage
optimized for a given design. range are presented in Figure 18. Based on these results, one
Due to the limits imposed by the S310, we chose to design can observe that the proposed topology and design approach
the converter with φ1 = −1 radian to tune the inverter as lend themselves to good performance at very high frequencies.
in phase to the rectifier as possible to minimize the con-
verter’s losses. At this tuning point, the rectifier capacitor CR is
composed entirely of the diode parasitic junction capacitance.
This allows parasitic inductance in the rectifier package to
be absorbed into LR , leading to more ideal performance. We
additionally chose to design the converter with ωo = 0.85ωs .
An optimal value of ωo was introduced in the design method-
ology of the previous section, however, since the S310 is
heavily constraining the usable values of φ1 , the optimal is
unreachable for this design. Instead, ωo was chosen to be
high enough to provide good transient response under on/off Fig. 14. Power Stage schematic of the experimental implementation. The
modulation and not so high to incur excessive loss. With these inductors are from the midi-spring family from Coilcraft, and the Diode is a
S310. The MOSFET is a LDMOS device fabricated from an integrated power
design choices, the component values are read from Figures 4 process. The converter operates at 75MHz with a 50% duty cycle.
and 6. Small adjustments are made to accommodate standard
component values and to correct the small error in the solution
due to the sinusoidal current approximation, resulting in the
values shown in the schematic of the converter presented
in Figure 14. The capacitor CE is made up of the parallel
combination of the transistor output capacitance ( 34pF) and
a discrete 51.7pF capacitor.
A photograph of the converter is shown in Figure 15.
The component sizes, packages, and layout were chosen for
construction convenience to validate the design approach and
do not necessarily represent the best method of achieving a
minimum-sized design. In particular, the size of the output
filter capacitor was sized much larger than strictly necessary
Fig. 15. Photograph of the converter prototype PCB.
for experimental expedience. Generally in this type of VHF
design, the minimum sizing of the output filter capacitor is
 IEEE Transactions on Power Electronics, Vol. 28, No. 4, pp. 1929-1937, April 2013.

V. C ONCLUSION
VDD
NC7WZ04
This document presents a resonant boost converter topology
that is suitable for operation at very high frequencies. The
VDD topology uses a small number of passive components and ab-
Modulate Gate sorbs device and packaging paracitics. Moreover, only small-
NC7SZ08
VDD
valued resonant inductors are used, enabling fast response
Clock under on-off control.
VDD The paper further introduces a procedure to design the
proposed resonant boost converter. Unlike previous design
NC7WZ04 methods for similar converter types, the method here does
1uF
not require extensive time-domain simulation sweeps across
circuit parameters. Rather, the procedure is based on numerical
Fig. 16. Schematic of the gate drive circuit used in the experimental solutions to closed-form circuit equations. This enables the
implementation. Output power is controlled by modulating the gate driver
at frequency lower than the converter’s switching frequency. These control designer to rapidly find the optimal converter design given a
and drive elements are placed on the back of the board, and cannot be particular semiconductor switch, or the optimal combination
seen in the photograph of Figure 15. The oscillator and modulation signal of converter design and switch layout if an integrated power
were provided externally for exprimental simplicity. For testing operating
points having specified average power levels, the modulation duty ratio was process is used.
controlled manually; closed-loop control of such systems is straightforward To validate the converter topology and design procedure, an
and has been extensively demonstrated in the past (e.g., [5], [6], [15], and experimental implementation has been constructed. Measured
[24])
waveforms from the prototype are in close agreement to sim-
ulated waveforms, and the converter achieves good efficiency
over a wide input voltage range. It may be concluded that
the proposed converter topology and design method yields
effective converter designs at VHF frequencies.

R EFERENCES
[1] J.M. Burkhart, R. Korsunsky, D.J. Perreault, “Design Methodology for a
Very High Frequency Resonant Boost Converter,” in 2010 International
Power Electronics Conference, pp.1902-1909, June 2010.
[2] D.J. Perreault, J. Hu, J.M. Rivas, Y. Han, O. Leitermann, R.C.N. Pilawa-
Podgurski, A. Sagneri, and C.R. Sullivan, “Opportunities and Challenges
in Very High Frequency Power Conversion,”, in 2009 IEEE Applied
Power Electronics Conference, pp. 1-14, Feb. 2009.
[3] R. Redl and N. Sokal, “A New Class-E DC/DC Converter Family with Re-
duced Parts Count: Derivation, Topologies, and Design Considerations,”
in Technical Papers of the Fourth International High Frequency Power
Conversion Conference, pp.395-415, 1989.
[4] J. Rivas, D. Jackson, O. Leitermann, A. Sagneri, Y. Han, and D. Per-
Fig. 17. Measured converter waveforms compared to simulated waveforms reault, “Design Considerations for Very High Frequency DC-DC Con-
in SPICE. verters,” in Power Electronics Specialists Conference, 2006 PESC 06 37th
IEEE, pp.1-11, 18-22 June 2006.
[5] J. Rivas, R. Wahby, J. Shafran, and D. Perreault, “New Architectures
for Radio-Frequency DC/DC Power Conversion,” IEEE Transactions on
Power Electronics, vol. 21, pp. 380-393, March 2006.
[6] R. C. Pilawa-Podgurski, A. D. Sagneri, J. M. Rivas, D. I. Ander-
sion, and D. J. Perreault, “Very High Frequency Resonant Boost
Converters,” in IEEE Transactions on Power Electronics, Vol. 24, Is-
sue 6, pp. 1654-1665, 2009.
[7] A. D. Sagneri, “Design of a Very High Frequency DC-DC Boost
Converter,” Master’s thesis, Massachusetts Institute of Technology, Cam-
bridge, MA, February 2007.
[8] W. Nitz, W. Bowman, F. Dickens, F. Magal-
haes, W. Strauss, W. Suiter, and N. Zeisse, “A New Family of
Resonant Rectifier Circuits for High Frequency DC-DC Converter
Applications,” in Third Annual Applied Power Electronics Conference
Proceedings,,pp.12-22, 1988.
[9] S. Birca-Galateanu and J.-L. Cocquerelle, “Class E Half-Wave Low dv/dt
Rectifier Operating in a Range of Frequencies Around Resonance,” IEEE
Transactions on Circuits and Systems-I: Fundamental Theory and Appli-
cations, Vol. 42, No. 2, February 1995.
Fig. 18. Converter output power and measured efficiency (not including gate [10] R. C. Pilawa-Podgurski, “Design and Evaluation of a Very High Fre-
drive loss). Output power is controlled by on-off modulating the converter with quency DC/DC Converter,” Master’s thesis, Dept. of Electrical Engineer-
a PWM signal at 1 MHz ing and Computer Science, Massachusetts Institute of Technology, Febru-
ary 2007.
 IEEE Transactions on Power Electronics, Vol. 28, No. 4, pp. 1929-1937, April 2013.

[11] J.R. Warren, “Cell Modulated DC/DC Converter” Master’s the-

sis, Dept. of Electrical Engineering and Computer Science, Mas-
sachusetts Institute of Technology, September 2005.
[12] J. Hu, A.D. Sagneri, J.M. Rivas, Y. Han, S.M. Davis, and D.J. Per-
reault, “High-Frequency Resonant SEPIC Converter with Wide Input
and Output Voltage Ranges,” IEEE Transaction on Power Electron-
ics, Vol. 27,No. 1 pp. 189-200, Jan 2012.
[13] J.R Warren, K.A. Rosowski, and D.J. Perreault, “Transistor Selection
and Design of a VHF DC-DC Power Converter,” IEEE Transactions on
Power Electronics,, No. 4, pp. 1531-1542, July 2007.
[14] W.A. Tabisz, and F.C. Lee, “DC Analysis and Design of Zero-Voltage-
Swiched Multi-Resonant Converters,” Power Electronics Specialists Con-
ference, Vol.1 pp 243-251 June 1989.
[15] N.O.Socal and A.D.Sokal,“Class E-A New Class of High-Efficiency
Tuned Single-Ended Switching Power Amplifiers,” IEEE J. Solid-State
Circ., vol. SC-10, no. 3, pp 168-176, Jun. 1975.
[16] A.D. Sagneri, D.I. Anderson, and D.J. Perreault, “Optimization of
Transistors for Very High Frequency DC-DC Converters,” 2009 IEEE
Energy Conversion Congress and Exposition, Sept. 2009, pp. 1590-1602.
[17] A.D. Sagneri, “Design of a Very High Frequency DC-DC Boost Con-
verter,” Master’s Thesis, Massachusetts Institute of Technology, 2005.
[18] K. Koizumi, M. Iwandare, and S. Mori, “Class E2 DC-DC Con-
verter with Second Harmonic Resonant Class E Inverter and Class
E Rectifier,” in Proc. 3rd Annual Applied Power Electronics Confer-
ence, 1994, pp. 1012-1018
[19] A.D. Sagneri, D.I.Anderson, and D.J.Perreault, “Transformer Synthesis
for VHF Converters,” 2010 International Power Electronics Confer-
ence, June 2010, pp. 2347-2353.
[20] Y. Han, A. Li, G. Cheung, C.R. Sullivan, and D.J. Perreault, “Evalu-
ation of Magnetic Materials for Very High Frequency Power Applica-
tions,” IEEE Transactions on Power Electronics, Vol. 27, No. 1, pp. 425-
435,January 2012.
[21] Y. Han, and D.J. Perreault, “Inductor Design Methods with Low-
Permeability RF Core Materials,” 2010 IEEE Energy Conversion
Congress and Exposition, pp. 4376-4383, September 2010.
[22] Di Yao, C.G. Levey, and C.R. Sullivan, “Microfabricated V-Groove
Power Inductors Using Multilayer Co-Zr-O Thin Films for Very-High-
Frequency DC-DC Converters,” IEEE Energy Conversion Congress and
Exposition, 2011.
[23] T.M. Andersen, S.K. Christensen, A. Knott, and M.A.E. Anderson, “A
VHF Class E DC-DC Converter with Self-Oscillating Gate Driver,” Ap-
plied Power Electronic Conference and Exposition, 2011, pp. 885-891.
[24] J.M. Rivas, O. Leitermann, Y. Han, and D.J. Perreault, “A Very High Fre-
quency DC-DC Converter Based on a Class Φ2 Resonant Inverter,” IEEE
Transactions on Power Electronics, Vol. 26, No. 10, pp. 2980-2992, Oc-
tober 2011.