5EC3-01: Computer Architecture

Dr. S. K. Singh, Professor, ECE,

JECRC.
UNIT-3

Contents:
 Control Design Instruction sequencing Interpretation
 Hard wired control Design methods and CPU control unit.
 Micro programmed Control - Basic concepts, minimizing
microinstruction size, multiplier control unit.
 Micro programmed computers - CPU control unit

# Classification of instruction types

 Data processing: Arithmetic and logic instructions (e.g. ADD, SUB, AND, XOR etc.)
 Data storage: Movement of data into or out of register and or memory locations ( MOV, LOAD, etc)
 movement: I/O instructions ( IN, OUT etc)
 Control: Test and branch instructions (JMP, JNZ etc)

# MICRO-OPERATIONS
Execution of a program consists of a sequence of instruction cycles, with one machine instruction per cycle.
Each instruction cycle is made up of a number of smaller units e.g. , fetch, indirect, execute, and
interrupt, with only fetch and execute cycles always occurring.
To design a control unit, however, it needs to break down the description further. In fact, each of the smaller
cycles involves a series of steps, each of which involves the four processor registers.

 Memory address register (MAR): Is connected to the address lines of the system bus. It specifies the
address in memory for a read or write operation.
 Memory buffer register (MBR): Is connected to the data lines of the system bus. It contains the value
to be stored in memory or the last value read from memory.
 Program counter (PC): Holds the address of the next instruction to be fetched.
 Instruction register (IR): Holds the last instruction fetched.

To summarize, the execution of a program consists of the sequential execution of instructions. Each
instruction is executed during an instruction cycle made up of shorter sub-cycles (e.g., fetch, indirect, execute,
interrupt).The execution of each sub-cycle involves one or more shorter operations, that is, micro-operations
shown in figure below.

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The concept of micro-operations serves as a guide to the design of the control unit.

Fetch Cycle:
The fetch cycle occurs at the beginning of each instruction cycle and causes an instruction to be
fetched from memory.
The sequence of events for the fetch cycle from the point of view of its effect on the processor registers.
An example shown in Figure, at the beginning of the fetch cycle, the address of the next instruction to be
executed is in the program counter (PC); in this case, the address is 1100100.
The first step is to move that address to the memory address register (MAR) because this is the only
register connected to the address lines of the system bus.
The second step is to bring in the instruction. The desired address (in the MAR) is placed on the address
bus, the control unit issues a READ command on the control bus, and the result appears on the data bus and is
copied into the memory buffer register (MBR). It also needs to increment the PC by the instruction length to get
ready for the next instruction. Because these two actions (read word from memory, increment PC) do not
interfere with each other and do simultaneously to save time.
The third step is to move the contents of the MBR to the instruction register (IR).This frees up the
MBR for use during a possible indirect cycle.

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Each micro-operation involves the movement of data into or out of a register. So long as these movements do
not interfere with one another, several of them can take place during one step, saving time.
Symbolically, it can be writing this sequence of events as follows:

Where I is the instruction length.

Each micro-operation can be performed within the time of a single time unit. The t1, t2, t3 represents successive
time units. In words,
 First time unit: Move contents of PC to MAR.
 Second time unit: Move contents of memory location specified by MAR to MBR. Increment by I the
contents of the PC.
 Third time unit: Move contents of MBR to IR.

Indirect Cycle:
Once an instruction is fetched, the next step is to fetch source operands. Let us assume a one-address
instruction format, with direct and indirect addressing allowed.
If the instruction specifies an indirect address, then an indirect cycle must precede the execute cycle.

The address field of the instruction is transferred to the MAR. This is then used to fetch the address of the
operand. Finally, the address field of the IR is updated from the MBR, so that it now contains a direct rather than
an indirect address. The IR is now in the same state as if indirect addressing had not been used, and it is ready
for the execute cycle.

Interrupt Cycle:
At the completion of the execute cycle, a test is made to determine whether any enabled interrupts have
occurred. If so, the interrupt cycle occurs. The nature of this cycle varies greatly from one machine to another.

In the first step, the contents of the PC are transferred to the MBR, so that they can be saved for return from the
interrupt.
Then the MAR is loaded with the address at which the contents of the PC are to be saved, and the PC is
loaded with the address of the start of the interrupt-processing routine. These two actions may each be a single
micro-operation. However, it may take one or more additional micro-operations to obtain the Save _Address and
the Routine_Address before they can be transferred to the MAR and PC, respectively.
In any case, once this is done, the final step is to store the MBR, which contains the old value of the PC,
into memory. The processor is now ready to begin the next instruction cycle.

Execute Cycle:
The fetch, indirect, and interrupt cycles are simple and predictable. Each involves a small, fixed sequence of
micro-operations and, in each case, the same micro-operations are repeated each time around.
This is not true of the execute cycle. Because of the variety opcodes, there are a number of different
sequences of micro-operations that can occur.
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 First, consider an add instruction:
ADD R1, X
Which adds the contents of the location X to register R1. The following sequence of micro-operations might
occur:

We begin with the IR containing the ADD instruction.

In the first step, the address portion of the IR is loaded into the MAR.
Then the referenced memory location is read.
Finally, the contents of R1 and MBR are added by the ALU.

# CONTROL OF THE PROCESSOR

All elementary operations of processor are called micro-operations which fall into one of the following
categories:
 Transfer data from one register to another.
 Transfer data from a register to an external interface (e.g., system bus).
 Transfer data from an external interface to a register.
 Perform an arithmetic or logic operation, using registers for input and output.
The control unit performs two basic tasks:
 Sequencing: The control unit causes the processor to step through a series of micro
operations in the proper sequence, based on the program being executed.
 Execution: The control unit causes each micro-operation to be performed.
The control unit operates is the use of control signals.

Control Signals: For the control unit to perform its function, it must have inputs that allow it to determine
the status of the system and outputs that allow it to control the activities of the system. These are the
external specifications of the control unit. Internally, the control unit must have the logic required to perform its
sequencing and execution functions.

Fig. - Block Diagram of the Control Unit

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Figure shows a general model of the control unit, showing all of its inputs and outputs.

The inputs are as follows:

Clock: The control unit causes one micro-operation (or a set of simultaneous micro-operations) to be
performed for each clock pulse. This is referred to as the processor cycle time, or the clock cycle time.
Instruction register: The opcode and addressing mode of the current instruction are used to
determine which micro-operations to perform during the execute cycle.
Flags: These are required by the control unit to determine the status of the processor and the outcome
of previous ALU operations. For example, for the increment-and-skip-if-zero (ISZ) instruction, the control
unit will increment the PC if the zero flag is set.
Control signals from control bus: The control bus portion of the system bus provides signals to the
control unit.

The outputs are as follows:

Control signals within the processor: These are two types: one is cause data to be moved from one register to
another, and second is to activate specific ALU functions.
Control signals to control bus: These are also of two types: control signals to memory, and control signals
to the I/O modules.

Three types of control signals are used:

 To activate an ALU function,
 To activate a data path,
 Signals on the external system bus or other external interface.
All of these signals are ultimately applied directly as binary inputs to individual logic gates.

Let us consider the fetch cycle to see how the control unit maintains control. The control unit keeps
track of where it is in the instruction cycle. At a given point, it knows that the fetch cycle is to be performed
next.
The first step is to transfer the contents of the PC to the MAR. The control unit does this by activating
the control signal that opens the gates between the bits of the PC and the bits of the MAR.
The next step is to read a word from memory into the MBR and increment the PC.
The control unit does this by sending the following control signals simultaneously:
 A control signal that opens gates, allowing the contents of the MAR onto the address bus
 A memory read control signal on the control bus
 A control signal that opens the gates, allowing the contents of the data bus to be stored in the MBR
 Control signals to logic that add 1 to the contents of the PC and store the result back to the PC
Following this, the control unit sends a control signal that opens gates between the MBR and the IR.
This completes the fetch cycle except for one thing: The control unit must decide whether to perform an
indirect cycle or an execute cycle next. To decide this, it examines the IR to see if an indirect memory reference
is made.
The indirect and interrupt cycles work similarly. For the execute cycle, the control unit begins by
examining the opcode and, on the basis of that, decides which sequence of micro-operations to perform for the
execute cycle.

Types of Control Unit :

There are two types of control units:
 Hardwired Control Unit
 Microprogrammed Control Unit.

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Hardwired Control Unit :
In the Hardwired control unit, the control signals that are important for instruction execution control
are generated by specially designed hardware logical circuits, in which we cannot modify the signal generation
method without physical change of the circuit structure.
The operation code of an instruction contains the basic ddata for control signal generation.
generation In the
instruction decoder,, the operation code is decoded. The instruction decoder constitutes a set of many decoders
that decode different fields of the instruction opcode.
As a result, few output lines going out from th thee instruction decoder obtains active signal values. These
output lines are connected to the inputs of the matrix that generates control signals for executive units of the
computer. This matrix implements logical combinations of the decoded signals from the instruction opcode with
the outputs from the matrix that generates signals representing consecutive control unit states and with signals
coming from the outside of the processor, e.g. interrupt signals. The matrices are built in a similar way as a
programmable logic arrays.

Control signals for an instruction execution have to be generated not in a single time point but during the entire
time interval that corresponds to the instruction execution cycle. Following the structure of this cycle, the
suitable sequence of internal states is organized in the control unit.
A number of signals generated by the control signal generator matrix are sent back to inputs of the next
control state generator matrix.. This matrix combines these signals with the timing signal
signals,
s, which are generated
by the timing unit based on the rectangular patterns usually supplied by the quartz generator. When a new
instruction arrives at the control unit is in the initial state of new instruction fetching. Instruction decoding
allows the control
ntrol unit enters the first state relating execution of the new instruction, which lasts as long as the
timing signals and other input signals as flags and state information of the computer remain unaltered. A change
of any of the earlier mentioned signals stimulates the change of the control unit state.
This causes that a new respective input is generated for the control signal generator matrix. When an
external signal appears, (e.g. an interrupt) the control unit takes entry into a next control state that is the state
concerned with the reaction to this external signal (e.g. interrupt processing). The values of flags and state
variables of the computer are used to select suitable states for the instruction execution cycle.
The last states in the cycle are control states that commence fetching the next instruction of the program:
sending the program counter content to the main memory address buffer register and next, reading the
instruction word to the instruction register of computer. When the ongoing instr
instruction
uction is the stop instruction that
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ends program execution, the control unit enters an operating system state, in which it waits for a next user
directive.

Microprogrammed Control Unit

Unit:
The fundamental difference between these unit structures and the structure of the hardwired control unit
is the existence of the control store that is used for storing words containing encoded control signals mandatory
for instruction execution.
In microprogrammed
ogrammed control unitsunits,, subsequent instruction words are fetched into the instruction
register in a normal way. However, the operation code of each instruction is not directly decoded to enable
immediate control signal generation but it consists of the initial
tial address of a microprogram contained in the
control store.
1. With a single-level control store:
In this, the instruction opcode from the instruction register is sent to the control store address register.
Based on this address, the first microinstruction of a microprogram that interprets execution of this instruction
is read to the microinstruction register
register. This microinstruction contains in its operation part encoded control
signals, normally as few bit fields. In a set microinstruction ffield ield decoders, the fields are decoded. The
microinstruction also contains the address of the next microinstruction of the given instruction microprogram
and a control field used to control activities of the microinstruction address generator.

The last mentioned

entioned field decides the addressing mode (addressing operation) to be applied to the address
embedded in the ongoing microinstruction. In microinstructions along with conditional addressing mode, this
address is refined by using the processor condition fflags
lags that represent the status of computations in the current
program. The last microinstruction in the instruction of the given microprogram is the microinstruction that
fetches the next instruction from the main memory to the instruction register.

2. With a two-level control store:

In this, in a control unit with a two two-level
level control store, besides the control memory for
microinstructions, a nano-instruction
instruction memory is included. In such a control unit, microinstructions do not
contain encoded control signals. The operation part of microinstructions contains the address of the word in the
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nano-instruction
instruction memory, which contains encoded control signals. The nano
nano-instruction
ction memory contains all
combinations of control signals that appear in microprograms that interpret the complete instruction set of a
given computer, written once in the form of nano
nano-instructions.

In this way, unnecessary storing of the same operation parts of microinstructions is avoided. In this case,
microinstruction word can be much shorter than with the single level control store store.. It gives a much smaller
size in bits of the microinstruction memory and, as a result, a much smaller size of the entire control memory.
The microinstruction memory contains the control for selection of consecutive microinstructions, while those
control signals are generated at the basis of nano
nano-instructions. In nano-instructions,
instructions, control signals are frequently
encoded usingg 1 bit/ 1 signal method that eliminate decoding.

Difference between Hardwired and Micro

Micro-programmed
programmed Control Unit
HARDWIRED CONTROL UN
UNIT MICROPROGRAMMED CONTROL
CONT UNIT

Hardwired control unitt generates the control signals Micrprogrammed control unit generates the control

needed for the processor using logic circuits signals with the help of micro instructions stored in

control memory

Hardwired control unit is faster when compared to This is slower than the other as micro instructions are

microprogrammed control unit as the required control used for generating signals here

signals are generated

ted with the help of hardwares

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Difficult to modify as the control signals that need to be Easy to modify as the modification need to be done

generated are hard wired only at the instruction level

More costlier as everything has to be realized in terms Less costlier than hardwired control as only micro

of logic gates instructions are used for generating control signals

It cannot handle complex instructions as the circuit It can handle complex instructions

design for it becomes complex

Only limited number of instructions are used due to the Control signals for many instructions can be

hardware implementation generated

Used in computer that makes use of Reduced Used in computer that makes use of Complex

Instruction Set Computers(RISC) Instruction Set Computers(CISC)

References:
1. Computer Organization and Architecture: Designing for Performance, 8th Edition, Authors: William
Stallings Publisher: Prentice-Hall India.

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