UNIT - IV

Sequential logic Circuits

By
MVenkatesh
 One bit memory cell
 One Bit memory cell is also called Basic Bistable element. It
has two cross-coupled inverters, 2 outputs Q and Q’. It is called
“Bistable” as the basic bistable element circuit has two stable
states logic 0 and logic 1.

Some key points:

 The 2 outputs are always complementary.

 The circuit has 2 stable states. when Q=1,

it is Set state. when Q=0, it is Reset state.
(A) when A=0,
(i) In inverter1, Q = A'= B= 1  The circuit can store 1-bit of digital
(ii)In inverter2, Q' = B' = A = 0
(B) when A=1, information and so it is called one-bit
(i) In inverter1, Q = A'= B= 0
(ii)In inverter2, Q' = B' = A = 1 memory cell.
 Sequential Circuits

 This sequential circuit contains a set of inputs and output(s).

 The output(s) of sequential circuit depends not only on the
combination of present inputs but also on the previous output(s).
 Therefore, sequential circuits contain combinational circuits along
with memory (storage) elements.
 Some sequential circuits may not contain combinational circuits,
but only memory elements.
Types of Sequential Circuits
Asynchronous sequential circuits
 If some or all the outputs of a sequential circuit do not change (affect)
with respect to active transition of clock signal, then that sequential
circuit is called as Asynchronous sequential circuit.
Synchronous sequential circuits
 If all the outputs of a sequential circuit change (affect) with respect to
active transition of clock signal, then that sequential circuit is called as
Synchronous sequential circuit.
 That means, all the outputs of synchronous sequential circuits change
(affect) at the same time.
 Therefore, the outputs of synchronous sequential circuits are in
synchronous with either only positive edges or only negative edges of
clock signal.
 Clock signal
 Clock signal is a periodic signal and its ON time and OFF
time need not be the same. We can represent the clock signal
as a square wave, when both its ON time and OFF time are
same..
 Types ofTriggering

Level triggering
Edge triggering

 Level triggering
There are two levels, namely logic High and logic Low in clock signal.
Positive level triggering
Negative level triggering

Edge triggering
There are two types of transitions that occur in clock signal.That means,
the clock signal transitions either from Logic Low to Logic High or Logic
High to Logic Low.
Positive edge triggering
Negative edge triggering
There are two types of memory elements based on the type
of triggering that is suitable to operate it.
 Latches
 Flip-flops
Latches operate with enable signal, which is level sensitive.
Whereas, flip-flops are edge sensitive.
 SR Latch
SR Latch is also called as Set Reset Latch. This latch
affects the outputs as long as the enable, E is
maintained at 1

Positive EdgeTriggered SR Flipflop

SR Latch
SR Flip Flop Timing Diagram
 Points to be Remembered
 RS latch with cross-coupled NORs has the following
features:
 When R = 0 and S = 0, the output of SR latch does
not change.
 When S = 0 and R = 1, the output Q resets to 0.
 When S = 1 and R = 0 , the output Q sets to 1.
 When S = 1 and R = 1, the output of SR latch is
unstable (meta stable).
 D Flip Flop
 D flip-flop operates with only positive clock transitions or negative
clock transitions. Whereas, D latch operates with enable signal. That
means, the output of D flip-flop is insensitive to the changes in the
input, D except for active transition of the clock signal
 Fro SR latch, when both inputs are same the output either does not
change or it is invalid (Inputs 00 no change, inputs 11 Invalid
 In many practical applications, these input conditions are not
required
 These input conditions can be avoided by making them complement
of each other.This modified SR Latch known as D latch(Delay Latch)
D Qn Qn+1
0 0 0
0 1 0
1 0 1
1 1 1
 D Flip Flop Timing Diagram

D Qn Qn+1
0 0 0
0 1 0
1 0 1
1 1 1
 JK FLIP-FLOP
 The indeterminate states of an SR flipflop when S= R=1, can be
eliminated by using JK Flipflop
 The first stage, S input is now labeled as J input and R input
labeled as K input.
 Second input of both NANDs is common and is the clock
input has an additional circuitry to make the J and K inputs
transparent at an instance corresponding to an edge at the
clock input.
 Third input of upper NAND connects the Q output.

 Third input of lower NAND connects the Q output.

JK Flipflop Using NAND Gates JK Flipflop Using NOR Gates

J K Qn Qn+1
0 0 0 0 No Change
0 0 1 1
0 1 0 0 Reset
0 1 1 0
1 0 0 1 Set
1 0 1 1 Logic Symbol
1 1 0 1 Complement
1 1 1 0
TruthTable
Points to be Remembered
 JK-flip flop has the following features:
 When J = 0 and K = 0, the output of JK flip flops does not change
on a clock edge.
 When J = 0 and K = 1, the output Q resets to 0 after the clock
edge.
 When J = 1 and K = 0, the output Q sets to 1 after the clock edge.
 When J = 1 and K = 1, the output of JK flip flops toggles (changes
to opposite state) on a clock edge.
Timing Diagrams
 Race Around Condition
 Generally in flip flops when clock pulse is applied, output changes
when input changes.
 But in JK flip flop, when J=1,K=1 , at each clock pulse output
changes 1 to 0 and 0 to 1 without any change in the input. Because
when J = 1 and K = 1, the output of JK flip flops toggles (changes to
opposite). This is called RACE AROUND CONDITION.
 Master-Slave Flip-Flop
 A master-slave flip-flop is constructed from two seperate
flip-flops. One circuit serves as a master and the other as a
slave.
 The master flip-flop is enabled on the positive edge of the
clock pulse(CP) and the slave flip-flop is disabled by the
inverter.
 The information at the external S and R inputs is
transmitted to the master flip-flop.
 When the pulse returns to negative clock pulse, the master
flip-flop is disabled and the slave flip-flop is enabled. The
slave flip- flop then goes to the same state as the master
flip-flop.
Master Slave Flipflop Timing Diagrams
 T Flip-Flop
 T flip-flop is the simplified version of JK flip-flop. It is obtained by
connecting the same input „T‟ to both inputs of JK flip-flop. It
operates with only positive clock transitions or negative clock
transitions

T Qn Qn+1
0 0 0
0 1 1
1 0 1
1 1 0
Summary
 Excitation Tables
 In electronic deign, an excitation table shows the minimum inputs
that are necessary to generate a particular next state (in other words,
to "excite" it to the next state) when the current state is known
 SR Flipflop ExcitationTable
JK Flipflop
 Conversion of Flipflops
 SR to D Flipflop

LOGIC DIAGRAM
TruthTable

K Map Simplification
 Shift Registers
 In digital electronic systems, a shift register is a type of register
that can shift binary data from one location to another.
 The construction of a shift register consists of a series of flip-flops
connected in a cascade fashion. In this cascaded group of flip-flops,
the output of one flip-flop is connected to input of the next flip-
flop.
This arrangement allows for the shifting or repositioning of data
either to the left or right or both.
Based on their characteristics, the shift registers can be classified
into the following types
 Serial-In Serial-Out (SISO) Shift Register
 Parallel-In Parallel-Out (PIPO) Shift Register
 Serial-In Parallel-Out (SIPO) Shift Register
 Parallel-In Serial-Out (PISO) Shift Register
 Bidirectional Shift Register
 Universal Shift Register
Bidirectional Shift Register
Case 1 – Shift-Right Operation

When the control signal R/L' is HIGH, then the AND gates 1, 3, 5,
and 7 are enabled, and the AND gates 2, 4, 6, and 8 are disabled.
The output of the flip-flop A is connected to the input of the flip-
flop B, the output of the flip-flop B is connected to the input of the
flip-flop C, and the output of the flip-flop C is connected to the
input of the flip-flop D. Hence, when a clock signal occurs, the data
bits are shifted one place to the right.

Case 2 – Shift-Left Operation

When the control signal R/L' is LOW, then the AND gates 2, 4, 6,
and 8 are enabled, and the AND gates 1, 3, 5, and 7 are disabled.
The output Q of each flip-flop connected to the D input of the
following flip-flop. Thus, when a clock signal occurs, the data bits
are shifted one place to the left.
Universal Shift Register
Mode of Control
Register Operation
S0 S1
0 0 No Change
0 1 Shift Right
1 0 Shift Left
1 1 Parallel Load
 Shift Registers
Introduction to shift registers
https://www.youtube.com/watch?v=0vS6O4StDW4&list=PLyKi
mj0ontkd-V-7C3rkE0V1P-A0PBPsF&index=1
Serial In Serial Out Shift Register
https://www.youtube.com/watch?v=1Q3E0gQBtP8&list=PLyKim
j0ontkd-V-7C3rkE0V1P-A0PBPsF&index=2
Serial In Parallel Out Shift Register
https://www.youtube.com/watch?v=GBYn7TGFgf8&list=PLyKim
j0ontkd-V-7C3rkE0V1P-A0PBPsF&index=3
Parallel In Serial Out Shift Register
https://www.youtube.com/watch?v=9ym19Yjhdh0&list=PLyKimj
0ontkd-V-7C3rkE0V1P-A0PBPsF&index=5
Parallel In Parallel Out Shift Register
https://www.youtube.com/watch?v=7bqrrBw9Ais&list=PLyKimj0
ontkd-V-7C3rkE0V1P-A0PBPsF&index=4
 Counters
A Group of flip-flops connected together forms a register.
A counter is a register capable of counting the number of clock pulses
arriving at its clock input. Count represents the number of pulses
arrived.
In case of up counter, the arrival of each clock pulse, the counter is
incremented by one, in case of down counter it is decremented by one
There are two types of counters
1. Asynchronous Counter
2. Synchronous Counter
In Asynchronous counters, (ripple counter) the first flip-flop is clocked
by the external clock pulse and then each successive flip-flop is clocked
by the output of the preceding flip-flop. In Synchronous counters, the
clock input is connected to all of the flip-flop so that they are clocked
simultaneously.
Asynchronous Counter

Synchronous Counter
Ring Counters
 A ring counter is basically a circulating shift register in
which the output of the least significant stage is fed back to
the input of the most significant stage.
 The following is a 4-bit ring counter constructed from D flip-
flops.

 The output of each stage is shifted into the next stage on the
positive edge of a clock pulse.
 If the CLEAR signal is high, all the flip-flops except the first
one FF0 are reset to 0. FF0 is preset to 1 instead.
 An n-stage Ring counter yields a count sequence of
length n
Clock pulse QA QB QC QD
0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1
 Clock pulse QA QB QC QD
0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1

Timing Diagram for Ring Counter for negative Edge Triggering

 Twisted Ring (Johnson) Counter
 In Johnson counters, the inverted output of the last stage
fed back to the input of the first stage.
 They are also known as twisted ring counters. An n-stage
Johnson counter yields a count sequence of length 2n,.
Clock QA QB QC QD
pulse
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
 Clock QA QB QC QD
pulse

0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1

Timing Diagram for Twisted Ring(Johnson) Counter for negative Edge Triggering
 Modulo- N Counter
Steps for the design of modulo-N counter as follows

1. Determine the number of flip flops needed by using the

formula 2n ≥ N where n is number of flip-flops
required, N is number sequences to be counted
2. Choose the type of flip-flops to be used
3. Determine the excitation table for the selected flip-flop
4. Use K-Map or any other simplification method to
derive the flip flop input function
5. Draw the logic diagram
 Modulo-5 Counter
 Design MOD-6 Counter using JK flipflop
Step 1: Find number of flipflops required
Number of flipflops required 2n ≥ N
Here N = 6, therefore n =3

Step 2: Write Excitation Table for JK Fliflop

Step 3: Determine the transition table
Step 4: K Map simplification
Step 5: Design the circuit
 Design Decade Counter Using T Flipflop or Design
MOD-10 Counter Using T Flipflop
The Decade counter is a MOD-10 counter. It has 10 states 0-
9
Step 1: Find number of flipflops required
Number of flipflops required 2n ≥ N
Here N = 10, therefore n =4

Step 2:Type of flipflops used is T

Write Excitation Table for T Fliflop
K Map Simplification
Logic Diagram
 Design MOD-12 Counter usingTflipflop

ExcitationTable
 Design BCD updown counter using SR Flipflop
Step 1 Number of
flipflops needed 4
Step 2 Flipflop to
be used = SR

ExcitationTable
Circuit Diagram
 State Diagram
State diagram representation of a pictorial a
behaviour of sequential circuit.
The state is represented by the circle,
The transition between states is indicated by directed
lines connecting the circles.
A directed line connecting a circle with itself
indicates that next state is same as present state.
The binary number inside each circle identifies the
state represented by the circle.
The directed lines are labelled with two binary
numbers separated by a symbol '/'.
The input value that causes the state transition is
labelled first and the output value during the present
state is labelled after the symbol '/'.
Although the state diagram provides a description of the behaviour of a sequential
circuit that is easy to understand, to proceed with the implementation of the circuit,
it is convenient to translate the information contained in the state diagram into a
tabular form. Table. shows the state table for the state diagram shown in Fig. It
represents relationship between input, output and flip-flop states. It consists of
three sections labelled present state, next state, and output. The present state
designates the state of flip-flops before the occurrence of a clock pulse. The next
state is state of the flip-flop after the application of a clock pulse, and the output
section gives the values of the output variables during the present state. Both the
next state and output sections have two columns representing two possible input
conditions: X = 0 and X = 1.

Let 00 = a, 01 = b, 10 = c, 11 = d
 State Reduction
 The state reduction technique basically avoids the introduction of redundant
states.
 The reduction in redundant states reduce the number of required flip-flops and
logic gates, reducing the cost of the final circuit.
 The two states are said to be redundant or equivalent, if every possible set of
inputs generate exactly same output and same next state.
 When two states are equivalent, one of them can be removed without altering the
input-output relationship.
 State Assignment
There are two rules for making state assignments

Rule 1: States having the same NEXT

STATES for given input condition should
have assignments which can be grouped into
logically adjacent cells in K-map

Rule 2: States that are the NEXT STATES of

single state should have assignments which can
be grouped into logically adjacent cells in K-
map
THANK YOU