Combinatorial Logic Design

D IIgor Ivkovic
Dr. I k i
iivkovic@uwaterloo.ca
@

[with material from “Computer Organization and Design” by Patterson and Hennessy, and “Digital Design and
Computer Architecture” by Harris and Harris, both published by Morgan Kaufmann]
Objectives

 Introduction to Logic Circuits

 Boolean Equations and Boolean Algebra
 From Logic to Gates
 Additional C
Circuit Elements
 Karnaugh Maps
 Timing and Glitches

2
Logic Circuit /1
 Electric Circuit:
 Provides a path through which the electrical current can flow

 Logic Circuit:
 An electric circuit that performs logical operations on input
signals that carry discrete values

 A logic circuit is composed of:

 Input terminals/nodes
 Output terminals/nodes
 Functional specification
 Timing specification

3
Logic Circuit /2
 Input Terminals / Nodes:
 Wires whose voltage represents a value of a discrete variable
 Three types: Input, Output, and Internal
 Inputs receive values from the external world

 E
Example:
l
 Input: A, B, C; Output: Y, Z; Internal: n1

4
Logic Circuit /3
 Circuit Element:
 It is also a circuit with its own inputs, outputs, and specification
 Elements in the example: E1, E2, E3

 Functional Specification:
 Describes the relationship between inputs and outputs

 Timing Specification:
 Specifies
S ifi th
the d
delay
l b between
t iinputs
t change
h and
d output
t t
response

n1
A E1
B E3 Y
C E2 Z

5
Logic Circuit /4
 Logic Gate:
 A circuit element that performs a basic logic function
 Examples include: NOT, AND, OR, NAND, NOR, XOR, NXOR
 Single Input: NOT, BUFFER
 Double Input: AND
AND, OR,
OR NAND,
NAND NOR
NOR, XOR
XOR, NXOR
 Multiple Input: NOR3, AND4

6
Logic Circuit /5
 Logic Gates Continued:

7
Logic Circuit /6
 Logic Gates Continued:

8
Logic Circuit /7
 Example of equivalent circuits:

 Types of Logic Circuits:

 Combinational Logic
 Sequential Logic
 Combinational Logic Circuit:
 Has no memory
 Outputs determined by the current values of inputs
 S
Sequential
i l Logic
i Circuit:
Ci i
 Has memory
 Outputs determined by the previous and the current values of
inputs

9
Combinatorial Logic Circuit /1
 A circuit is combinatorial if it consists of connected
circuit elements, such that:
 The circuit contains no cyclic paths
 Each circuit element is combinational
 Each node is either an input terminal or it connects to exactly
one output terminal

 Examples:
 Valid combinatorial circuit: Invalid combinatorial circuits:

10
Combinatorial Logic Circuit /2
 Bus:
 A bundle of multiple signals, either input or output
 Shown by a slash through the signal line, with the number next
to the slash indicating the number of bits in the bus
 If the number of bits is unimportant
p or obvious,, the number can
be omitted

 Examples:

11
Combinatorial Logic Circuit /3
 Boolean Equations
 Functional specification of outputs in terms of inputs

 Example1:
A
C S
B L
Cout
Cin
S = A ⊕ B ⊕ Cin
Cout = AB + ACin + BCin

 E
Example2:
l 2

12
Combinatorial Logic Circuit /4
 Variable Complement: A variable with a bar over it
 Literal:
te a A variable
a ab e oor its
ts co
complement
pe e t or
o
 Implicant: A product of literals
 Minterm:
 A product that includes all input variables

 Maxterm:
 A sum that includes all input variables

13
Combinatorial Logic Circuit /5
 Sum-of-Products Format:
 Each row can be written as a minterm
 A minterm is a product (AND) of literals
 Each minterm is TRUE for that row and only that row
 Form function by combining minterms for which the output is
TRUE using OR
 Hence, a sum (OR) of products (AND terms)
 Suitable
S it bl ffor representing
ti ffunctions
ti th
thatt have
h ttruth
th tables
t bl with
ith
more FALSE rows than TRUE rows

 Example:
 Y = F(A, B) = AB + AB

14
Combinatorial Logic Circuit /6
 Product-of-Sums Format:
 Each row has a maxterm
 A maxterm is a sum (OR) of literals
 Each maxterm is FALSE for that row and only that row
 Form function by combining maxterms for which the output is
FALSE using AND
 Thus, a product (AND) of sums (OR terms)
 Suitable
S it bl ffor representing
ti ffunctions
ti th
thatt have
h ttruth
th tables
t bl with
ith
more TRUE rows than FALSE rows

 Example:
 Y = F(A, B) = (A + B)(A + B)

15
Combinatorial Logic Circuit /7
 Boolean Equations Example:
 You are going to excel in this course (E as output)
 If you study regularly (S as input), and
 If you do not skip assignments (A as input)

 E
Exercise:
i
 Construct a truth table for the above example
 Express its functional specification in both the sum-of-products
sum of products
and product-of-sums formats
 Which format is better suited for this function (if any)?
 (Bon s) Dra
(Bonus) Draw the combinatorial logic circuits
circ its for both formats

16
Simplifying Boolean Equations /1
 Why simplify Boolean equations?
 To decrease the number of Boolean operators
 And in turn decrease the number of logical gates required to
build the corresponding logical circuit
 Which should make the circuit smaller,, cheaper,
p , and possibly
p y
faster to build

 How to simplify Boolean equations?

 Using the corresponding simplification rules
 Similar to traditional algebra, but simpler since variables have
only
y two values (0( or 1))

 Duality in simplification rules:

 ANDs and ORs, 0s and 1s are interchanged

17
Simplifying Boolean Equations /2

18
Simplifying Boolean Equations /3
 Simplification Rules as Logical Circuits:

B
B B

B
B B

19
Simplifying Boolean Equations /4
 Examples:
 Simplify Y = AB + AB
= B(A + A)
= B(1)
=B
 Simplify Y = A(AB + ABC)
= A(AB(1 + C))
= A(AB(1))
= A(AB)
= (AA)B
= AB

20
Simplifying Boolean Equations /5
 Exercise:
 Simplify Y = ABC + ABC + ABC
 Good Solution: BC + ABC
 Better Solution: BC + AB

 Di
Discussion:
i
 First minimize the number of gates/operators, and then select a
solution with he minimum number of literals

21
From Logic to Gates /1
 Schematic:
 A diagram of a logic circuit that shows the circuit elements and
th wires
the i th
thatt connectt them
th

 Programmable Logic Array (PLA)-Style Schematic:

 An array of AND gates followed by an array of OR gates
 That is, represent the equation in the sum-of-products format

 How to draw the schematic:

1. Draw a column for each input
2. Place inverters (NOT gates) in the adjacent columns
3. Draw rows of AND gates for each minterm, and connect them
to the corresponding inputs
4. Draw an OR gate for each output, and connect them to the
corresponding AND gates
22
From Logic to Gates /2
 Example:
 Y = ABC + ABC + ABC

23
From Logic to Gates /3
 Circuit Schematics Rules:
 Inputs should be placed on the left or on the top
 Outputs should be placed on the right or on the bottom
 Gates should flow from left to right
 Straight wires should be used instead of jagged wires
 Wires always connect at a T junction
 A dot where wires cross indicates a connection between
th wires
the i
 Wires crossing without a dot make no connection

24
From Logic to Gates /4
 Exercise:
 Map the given circuit schematic as the truth table below

25
From Logic to Gates /5
 Example: Priority Circuit
 Output corresponds to the most significant TRUE input

26
From Logic to Gates /6
 Priority Circuit with “Don’t Cares”:
 Output corresponds to the most significant TRUE input

27
From Logic to Gates /7
 Priority Circuit Schematic:
 Output corresponds to the most significant TRUE input

A3 A2 A1 A0 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 X 0 0 1 0
0 1 X X 0 1 0 0
1 X X X 1 0 0 0

28
From Logic to Gates /8
 Contention:
 Circuit tries to drive output of 0 and 1
 The actual value is 0, 1, or somewhere in between (in voltage)
 Might change with voltage, temperature, time, noise
 Often causes excessive power dissipation

 C t ti usually
Contention ll indicates
i di t a bug:
b
 X is used for “don’t care” and contention
 Look at the context to tell them apart

29
From Logic to Gates /9
 Tri-State Buffer:  Floating output:
 When enable (E) is true, it  Floating output (Z) might
acts
t as a BUFFER gate t b 0
be 0, 1
1, or somewhere
h iin
 When enable (E) is false, between (not necessarily
the output Y floats an error)
 It is driven to the
appropriate logical value
when some other circuit
element activates it
 If not active, the floating
output is not relevant to
th overall
the ll operation
ti off
the circuit

30
From Logic to Gates /10
 Tri-State Busses:
en1
 Tri-state buffers are used to
control interaction with the to bus
system memory by different from bus
hardware units
 Only one enable (en-i) signal
is allowed to be active at en2
one time
to bus
 As a result, only one hardware
from bus
unit can communicate with the
system memory at one time
 Hardware units include the
en3
microprocessor, a video
controller, and an Ethernet to bus
controller f
from bus
b
 Shared memory bus is not
very common in the modern
architectures
 Instead, point-to-point links en4
are used instead
to bus
from bus
31
Bubble Pushing /1
 De Morgan’s Theorem Applied:
 Certain circuitry types (e.g., CMOS circuitry) are better suited
f NAND and
for d NOR gates t over AND and d OR gatest
 Y = AB = A + B Y = A + B = AB

A
Y
B

A
Y
B

 Bubble Pushing:
 Redrawing circuits by having the matching bubbles cancel out,
so that the circuit functionality can be more easily determined

32
Bubble Pushing /2
 Bubble Pushing Process:
 Start at the circuit outputs, and work towards the circuit inputs
while
hil using
i D De MMorgan’s’ llaws ffor iindividual
di id l pushing
hi operations
ti
 Push any bubbles on the final output back towards the inputs,
so that the output can be expressed directly (e.g., as Y) and not
as its complement (e.g.,
( as Y))
 Redraw each gate so that the bubbles cancel
 If the current gate has an input bubble, redraw the preceding gate
with an output bubble
 If the current gate does not have an input bubble, redraw the
preceding gate without an output bubble

33
Bubble Pushing /3
 Bubble Pushing Example1:
 Simplify this circuit:  Step 2. No further
simplification
i lifi ti possibleibl
 Both input gates have a
bubble on their output to
match the input bubble
on the last OR gate

 Step1. Y = AB + CD

A
B
Y
C
D

34
Bubble Pushing /4
 Bubble Pushing Example2:
 Simplify this circuit:  Step2.

 Step3.
 Step1.

35
Karnaugh Maps (K-Maps) /1
 Karnaugh Maps (K-Maps):
 A technique for simplifying Boolean equations graphically
 K-maps work well on equations with four variables or less
 Based on simplification equation that eliminates A:
PA + PA = P
 Each square in the K-map corresponds to a row in the
matching truth table, and represents a single minterm

A B C Y Y Y
AB AB
0 0 0 1
00 01 11 10 C 00 01 11 10
0 0 1 1 C
0 1 0 0
0 1 1 0 0 1 0 0 0 0 ABC ABC ABC ABC
1 0 0 0
1 0 1 0
1 1 0 0 1 1 0 0 0 1 ABC ABC ABC ABC
1 1 1 0

36
Karnaugh Maps (K-Maps) /2
 K-maps introduction:
 Start by circling 1s in adjacent squares
 In the resulting Boolean expression, include only literals whose
both true and complement form are not in the circle
 The literals which have both forms included in the circle will be
cancelled out
Adjacent entries differ
 K-maps Example1: only in a single variable
(known as Grey code)

The resulting expression: Y = AB

37
Karnaugh Maps (K-Maps) /3
 K-maps Example2:

 The resulting expression: Y = AB + BC

38
Karnaugh Maps (K-Maps) /4
 K-maps elaboration:
 Every 1 must be circled at least once
 Use the fewest number of circles to cover all 1s
 Each circle must span a rectangular block of power of 2; that is,
1,, 2,, 4,, etc. squares
q in each direction
 Each circle must be as large as possible
 A circle may wrap around the edges of the K-map table
 A “don't
“d 't care”” (X) is
i circled
i l d only
l if it h
helps
l minimize
i i i ththe
equation; it is not mandatory to circle any of the Xs
 Extend an existing circle with Xs to simplify an expression

39
Karnaugh Maps (K-Maps) /5
 K-maps Example3:
Circles wrap around the table

Circles wrap around the table

40
Karnaugh Maps (K-Maps) /6
 K-maps Example4:
A B C D Y
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 X
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 X
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X

41
Multiplexer (Mux) /1
 Multiplexer (Mux):  Example: 2-to-1 Mux
 Selects between one of N
i
inputs
t andd it connects
t it tto
the output
 log2N-bit selects and
controls the input

42
Multiplexer (Mux) /2
 Mux as Logic Gates:  Mux as Tri-State Buffer:
 Sum-of-products format  For an N-input Mux,
Y use N tri-states
tri states
D0 D1
S
00 01 11 10  Turn on exactly one to
0 0 0 1 1 select the appropriate
input
1 0 1 1 0

Y = D0S + D1S

D0

S
D1

Y 43
Decoder /1
 Decoder:
 Takes N inputs and provides 2N outputs
 Only one output selected at once

44
Decoder /2
 Decoder implementation:

45
Decoder /3
 Decoder as a logic circuit:
 Example using OR of minterms

46
Timing and Glitches /1
 Timing in a circuit:
 Delay between inputs change and output response
 Propagation delay: tpd = max delay from input to output
 Contamination delay: tcd = min delay from input to output

 D l is
Delay i caused
d by
b
 Capacitance and resistance in a circuit
 Speed of light limitation

 Reasons why tpd and tcd may be different:

 Different rising
g and falling
g delays
y
 Multiple inputs and outputs, some of which are faster than
others
 Circuits typically slow down when hot
hot, and speed up when cold

47
Timing and Glitches /2
 Critical (Long) and Short Paths:
 Critical (Long) Path: tpd = 2 x tpd_AND + tpd_OR
 Short Path: tcd = tcd_AND

48
Timing and Glitches /3
 Glitch:
Y
 When a single input AB
change
h causes multiple
lti l C
output changes

 Example:
 What happens when
A = 0, C = 1, and B goes
from 1 to 0? Y = AB + BC

A
B
Y

49
Timing and Glitches /4
 Glitch example visualized:

A=
B= n1
Y=
n2
C=

 Fixing the glitch

 How would you fix the glitch and prevent it from occurring?
 W ld adding
Would ddi another
th gate
t fix
fi it? If yes, which
hi h gate?
t ?

50
Food for Thought
 Download and Read Assignment #1 Specifications:
 Assignment #1 is intended as an introduction to the
combinatorial
bi t i l llogic
i ddesign
i

 Read:
 Appendix C of the course textbook
 Review the material discussed in the lecture notes in more detail
 (Optional) Chapter 2 of the Harris and Harris textbook

51
Additional Exercises
 Exercise 1. 1. Write a Boolean equation in
sum-of-products format for the
given truth table
2. Minimize the derived Boolean
equation so that includes as
small as possible number of
minterms and literals
3. Draw a combinatorial circuit
schematic representing the
minimized Boolean equation
using only NOT, AND, and OR
gates
4. Draw a combinatorial circuit
schematic representing the
minimized Boolean equation
using only NOT, NAND, and
NOR gates

52
Additional Exercises
 Exercise 2. 1. Minimize the given Boolean
equation E1 and E2 so that
 Equation E1:
each includes the minimum
number of terms and literals
2. Draw a combinatorial circuit
 Equation E2: schematic for the minimized
equations E1 and E2 so that
each includes as small as
possible number of g
p gates;; yyour
schematic has to correctly
match the minimized equation

53