LONG and FOCOUSED QUESTIONS

8085
1. Explain, how demultiplexing of buses is performed in 8085?

It is very important to reduce number of pins in an IC. As we know address in 8085 contains 16
bits, and data contains 8 pins, we need 24 pins in IC to be used as address and data pins,
rather than this designer has a different approach to reduce the usage of pins for address
& data. Only 16 pins are used totally for address and data, in which 8 pins (AD0-AD7) are
combined, used to generate address & data. Microprocessor generates both data &
addresses one same 8 pins. The thing is to resolve both address & data from these
pins. This process is achieved through demultiplexing the address & data signals.

The Address and Data Busses

The address bus has 8 signal lines A8 –A15which are unidirectional. The other 8 address bits are
multiplexed (time shared) with the 8 data bits. So, the bits AD0 –AD7 are bi-directional and serve
as A0 –A7and D0 –D7at the same time. During the execution of the instruction, these lines carry
the address bits during the early part, then during the late parts of the execution, they carry the 8
data bits. In order to separate the address from the data, we can use a latch to save the value
before the function of the bits changes.

Demultiplexing AD7-AD0

From the above description, it becomes obvious that the AD7–AD0lines are serving a dual
purpose and that they need to be demultiplexed to get all the information. The high order bits of
the address remain on the bus for three clock periods. However, the low order bits remain for
 only one clock period and they would be lost if they are not saved externally. Also, notice that the
low order bits of the address disappear when they are needed most. To make sure we have the
entire address for the full three clock cycles, we will use an external latch to save the value of
AD7–AD0 when it is carrying the address bits. We use the ALE signal to enable this latch.
ALE operates as a pulse during T1, we will be able to latch the address. Then when ALE goes
low, the address is saved and the AD7–AD0 lines can be used for their purpose as the bi-
directional data lines.

The high order address is placed on the address bus and hold for 3 clk periods,
the low order address is lost after the first clk period, this address needs to be holding however we
need to use latch. The address AD7 –AD0 is connected as inputs to the latch 74LS373. The ALE
signal is connected to the enable (G) pin of the latch and the OC –Output control –of the latch is
grounded which you can see in the given diagram.

Procedure

Every Instruction has some machine cycles to complete its executions sometime called T states.
Whenever an instruction is executed by MPU first of all MPU sends ALE signal to address latch
IC to enable all D Latches to receive new address from MPU now (in first T state )
Microprocessor generates the address on Address Bus, half portion of address (lower order
address) is generated on AD0-AD7 . This Address bits are captured by D latches and stored in.
Now during next cycles say T2 T3 and so on, MPU can use AD0-AD7 as Data Bus to send receives
data. During this period the initially generated Address is also available at output pins of D
Latches .The IC 74LS31 is used as Address Latch it contains 8 D Latches to store lower half of
address.(8 bits).

2. Draw and explain the opcode Fetch machine cycle timing diagram of 8085 microprocessor.

Opcode fetch machine cycle of 8085:

 Each instruction of the processor has one byte opcode.

 The opcode are stored in memory. So, the processor executes the opcode fetch machine
cycle to fetch the opcode from memory.
 Hence, every instruction starts with opcode fetch machine cycle.
 The time taken by the processor to execute the opcode fetch cycle is 4T.
 In this time, the first, 3 T-states are used for fetching the opcode from memory and the
remaining T-states are used for internal operations by the processor.
3. Draw and explain the timing diagram of the following instructions: FCO5 RET, 4505H MOV A, B.

FC05 RET
MOV A, B

4. Draw and explain the timing diagram of the STA2300 H instruction.

5. Sketch the timing diagram for memory write cycle of the 8085 microprocessor.

6. Draw and explain the Opcode fetch machine cycle timing diagram of 8085 microprocessor.
7. Write an assembly language program for 8085 microprocessor to find the sum of 10 natural
numbers.

Here, we consider the first 10 natural number (1 to 10)

MVI A, 00H
MOV B, A
MVI C, 0AH
JNZ L1 ADD B
INR B
DCR C
JNZ L1
STA 4500H
HLT
8. Write an assembly language program for getting a delay of 1 sec assuming the clock frequency of 3.3
MHz using 8085 microprocessor instructions.

MVI C, 0AH
LOOP: MVI D, 64H
LOOP1: MVI E, 0DEH
LOOP2: DCR E
JNZ LOOP2
DCR D
JNZ LOOP1
DCR C
JNZ LOOP
RET

9. Eight no’s of 8 bit data are stored in consecutive memory locations. Develop an assembly language
program for 8085
a. Determine the largest element in the block of data.

MVI C, 08H
LXI H, 4500H
DCR C
MOV A, M
LOOP INX H
CMP M
JNC NEXT
MOV A, M
NEXT DCR C
JNZ LOOP
STA 450BH
HLT
10. Design an interface in order to interface two input devices and 1 KB RAM with 8085 microprocessor.
Draw the neat sketch and find the memory map.

11. Show the memory map to obtain 4K×4 memory using the following chips.
a. 1K×4 RAM
b. 2 line to 4 line decoder
12. Make a diagram showing how 2764 EPROMs can be connected to form a 16 K byte program storage
memory subsystem.

13. What are the difference control signals of 8085 microprocessor and explain the functions HOLD and
HLDA?

Control signals
IO/M*(Pin 34,output)
 This pin tells whether I/O or memory operation is being performed.
 If IO/M = 1 then, I/O operation is being performed.
 If IO/M = 0 then, Memory operation is being performed.

Table below showing IO/M, S0, S1 and corresponding operations.

RD* (Pin 34, output)

 RD stands for Read.
 It is an active low signal. It is a control signal used for Read operation either
from memory or from Input device.
 A low signal indicates that data on the data bus must be placed either from
selected memory location or from input device.
WR* (Pin 31, output)
 WR stands for Write.
 It is also active low signal.
 It is a control signal used for Write operation either into memory or into output
 device.
 A low signal indicates that data on the data bus must be written into selected
memory location or into output device.

ALE (Pin 30, output)

 It is used to enable Address Latch.

 It indicates whether bus functions as address bus or data bus.
 If ALE = 1 then, bus functions as address bus.
 If ALE = 0 then, bus functions as data bus.

HOLD (Pin 38, Input)

 HOLD pin is used to request the microprocessor for DMA transfer.
 A high signal on this pin is a request to microprocessor to relinquish the hold on
buses.
 This request is sent by DMA controller.
 Intel 8257 and Intel 8237 are two DMA controllers.

HLDA (Pin 39, Output)

 HLDA stands for Hold Acknowledge.
 The microprocessor uses this pin to acknowledge the receipt of HOLD signal.
 When HLDA signal goes high, address bus, data bus, RD, WR, IO/M pins are tri-
stated.
 This means they are cut-off from external environment.
 The control of these buses goes to DMA Controller.
 Control remains at DMA Controller until HOLD is held high.
When HOLD goes low, HLDA also goes low and the microprocessor takes
control of the buses.

14. What are the interrupt facilities available in 8085?

TRAP (Pin 6, input):

 It is an non-maskable interrupt.
 It has the highest priority.
 It cannot be disabled.
 It is both edge and level triggered.
 It means TRAP signal must go from low to high and must remain high for a certain
period of time.
 TRAP is usually used for power failure and emergency shutoff.

RST 7.5 (Pin 7, input)

 It is a maskable interrupt.
 It has the second highest priority.
 It is positive edge triggered only.
 The internal flip-flop is triggered by the rising edge.
 The flip-flop remains high until it is cleared by RESET IN.
 RST 6.5(Pin 8, Input)
 It is a maskable interrupt.
 It has the third highest priority.
 It is level triggered only.
 The pin has to be held high for a specific period of time.
 RST 6.5 can be enabled by EI instruction.
 It can be disabled by DI instruction.

RST 5.5 (pin 9, Input)

 It is a maskable interrupt.
 It has the fourth highest priority.
 It is also level triggered.
 The pin has to be held high for a specific period of time.
 This interrupt is very similar to RST 6.5.

INTR (pin 10, input)

 It is a maskable interrupt.
 It has the lowest priority.
 It is also level triggered.
 It is a general purpose interrupt.
 By general purpose we mean that it can be used to vector microprocessor to any
specific subroutine having any address.

INTA* (pin 11, Output)

 It stands for interrupt acknowledge.
 It is an outgoing signal.
 It is an active low signal.
Low output on this pin indicates that microprocessor has acknowledged the INTR
request

Software interrupts:
 The software interrupts are program instructions. These instructions are inserted at desired locations in
a program.
 The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for these interrupts
can be calculated as follows. Interrupt number * 8 = vector address
For RST 5.5 * 8 = 40 = 28H
Vector address for interrupt RST 5 is 0028H
The Table shows the vector addresses of all interrupts.
 15. Explain the use of the instructions EI, DI, SIM and RIM.

EI Instruction
 Enable interrupts
 Initially when switched on or resting all the interrupts are in disable position, so EI is used to make them
enable.
 By this interrupt enable flag is set

EI Instruction
 Disable interrupts
 It can be written in the beginning of the program to execute all the program without any interference.
 By this interrupt enable flag is reset

SIM Instruction
 The 8085 provide additional masking facility for RST 7.5, RST 6.5 and RST 5.5 using
SIM instruction.
 The status of these interrupts can be read by executing RIM instruction.The masking or
unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can be performed by moving an
8-bit data to accumulator and then executing SIM instruction.
 The format of the 8-bit data is shown below.

RIM Instruction
 The status of pending interrupts can be read from accumulator after executing RIM
instruction.
 When RIM instruction is executed an 8-bit data is loaded in accumulator, which can be
interpreted as shown in fig.
16. Explain about the 8085 flags with the suitable structure of its flag register.

FLAGS

 This is the 8 bits register and used to reflect the condition of the result of any A/L
operation.
 Among 8 flip flops only 5 flip flops are used.
 Due to this flags MP take the decision to change the sequence of program
execution i.e. it can jump from one location in the memory to another during
program execution.
 This flags depend on the content of the accumulator because after each A/L
operation the result is stored in the accumulator.

 The five flags are 1. Carry flag

2. Parity flag
3. Auxiliary carry flag
4. Zero flag
5. Sign flag

CARRY FLAG
After each A/L operation if there will be a carry result then this flag is set
otherwise it is reset. This acts as a borrow flag in the case of subtraction
operation. For example when the two 8bits numbers like 80H (1000000) and 82H
(10000010) when added the result will be 102H (1, 00000010), so there is a carry
results and in this case the CF will be set.
 PARITY FLAG
If the nos. of 1’s present is even in the result (content of accumulator) after any
A/L operation then this flag is set otherwise it will be reset. For example if the
accumulator contains a data like F2H (11110010) after an A/L operation, then PF
will be set because the result contains six nos. of 1’s i.e. even nos. of 1’s.
ZERO FLAG
 If the accumulator contains 00H (0000000) after any A/L operation then this flag
is set otherwise reset. For example if the two same numbers is subtracted then the
result will be 00H, then in this case the ZF is set.
 It is not only depends the accumulator but also depends the other GPRs (B,C,
used as counter) when INR and DCR instructions is executed.
SIGN FLAG
 If the MSB (D7 bit) in the accumulator is 1 after any A/L operation then this flag
will be set otherwise it will reset.
 This flag is exclusively used in sign operation. As we know the MSB bit is used
to represent the sign of a number i.e if the MSB of a number is 1 then that number
is a negative number so this flag depend on the MSB bit of the accumulator.
 In sign number manipulation among 8 bits only 7 bits are used for the magnitude
and last bit is used for sign.
AUXILLARY FLAG
 This flag is not accessible to the user and no instruction is available using this
flag. This is used exclusively in BCD operation.
 In any arithmetic operation when there will be a carry result from D3-bit to D4-bit
of the operand then this flag is set otherwise it is reset.

17. Explain about the 8085 addressing mode with examples for each.

Addressing modes of 8085

 To perform any operation, we have to give the corresponding instructions to the
microprocessor.
 In each instruction, programmer has to specify 3 things:
 Operation to be performed.
 Address of source of data.
 Address of destination of result.
 The method by which the address of source of data or the address of destination of result
is given in the instruction is called Addressing modes.
 The term addressing mode refers to the way in which the operand of the instruction is
specified.
Types of Addressing Modes
Intel 8085 uses the following addressing modes:
 Direct Addressing Mode
 Register Addressing Mode
 Register Indirect Addressing Mode
 Immediate Addressing Mode
 Implicit Addressing Mode
 Direct Addressing Mode
In this mode, the address of the operand is given in the instruction itself. For
example
 LDA 3456H
 STA 6785H
 LHLD 4532H

 Register Addressing Mode

In this mode, the operand is in general purpose register. For example
 MOV A,B
 ANA B
 SBB C
 Register Indirect Addressing Mode
In this mode, the address of operand is specified by a register pair. For example
 MOV A,M
 LDAX B
 STAX D.
 Immediate Addressing Mode
In this mode, the operand is specified within the instruction itself. For example
 MVI A,65H
 ADI 45H
 SUI 42H
 Implicit Addressing Mode
If address of source of data as well as address of destination of result is fixed, then
there is no need to give any operand along with the instruction. For example
 CMA
 DAA

18. Write a program in 8085 assembly language to compare the two 8-bits numbers stored in two
consecutive memory locations and stores the smaller number in the next location.

LDA4150H
LXI H, 4151H
CMP M
JC NEXT
MOV M, A
NEXT STA 4152H
HLT

19. Write a program in 8085 assembly language to multiply two 8-bits numbers stored in consecutive
memory location and stores the result in the next location.

LDA 4152H
MOV B, A
LXI D, 0000H
LHLD 4150H
 XCHG
LOOP DAD D
DCR B
JNZ LOOP
SHLD 4154H
HLT

20. Write a program in 8085 assembly language to divide two 8-bits numbers stored in consecutive
memory location and stores the result in the next location.

LDA 4150H
MOV B, A
LDA 4151H
MVI C, 00H
LOOP SUB B
INR C
CMP B
JNC LOOP
STA 4152H
MOV A, C
STA 4153H
HLT

21. Interface a 16 KB x 8 EPROM memory chip and a 16KB x 8 RAM chip with the 8085 using logic
gates. Draw the memory map also.
22. Explain the operation of the following instructions in 8085. Also specify the number of T-states and
name of the machine cycles involved in each instructions:
a) ADD R
b) CPI 8-bit
c) JZ 16-bit
d) CALL 16-bit

ADD R: The content of register is added with Accumulator and result is stored in the Accumulator.
M/C: Opcode fetch
T-States: 4

CPI 8-Bit: 8-bit immediate data is compared with the content of accumulator and the corresponding flags
are affected.
M/C: Opcode fetch, Memory Read
T-States: 4+3 = 7

JZ 16 bit: Jump to 16 bit destination address if ZF=1

M/C: Opcode fetch, Memory Read, Memory Read (Satisfied condition)
Opcode fetch, Memory Read (Unsatisfied condition)
T-States: 4+3+3=10 (Satisfied condition)
4+3 = 7 (Unsatisfied condition)

CALL 16-bit: The program control is transferred to the 16-bit destination address and the address of the
next instruction is stored into the stack
M/C: Opcode fetch, Memory Read, Memory Read, Memory Write, Memory Write
T-States: 6+3+3+3+3 = 18
Intel-8086

1. Discuss the various addressing modes of 8086 microprocessor

The different techniques by which the operand specified in an instruction is called addressing
modes.
The following addressing modes used in 8086 are specifying the operand.
 REGISTER ADDRESSING MODE:

In this operands are specified through registers

e.g: MOV AL, BL
ADD CX, BX
SUB CH, DL

 IMMEDIATE ADDRESSING MODE:

In this the operand are specified in the instruction immediately.

e.g: MOV AL, 05
ADD CX, 6000
SUB CH, 50

 MEMORY ADDRESSING MODE:

When the data is in the memory, the address of the data must be specified. Depending upon
address specification, following memory addressing modes are available
 DIRECT ADDRESSING MODE

In this the offset address is specified directly.

e.g: MOV AL, [6000]
SUB CX, [5055]
 BASE REGISTER ADDRESSING MODE

In this the offset address is specified indirectly through base register.

e.g: MOV AL, [BX]
SUB CX, [BP + 0]
 INDEX ADDRESSING MODE

In this the offset address is specified indirectly through index register

r.
e.g: MOV AL, [SI]
SUB CX, [DI]

 BASE INDEX ADDRESSING MODE

In this the offset address is specified indirectly through index and base register.
e.g: MOV AL, [BX + SI]
SUB CX, [BX + DI]

 RELATIVE BASE ADDRESSING MODE

In this the offset address is specified indirectly through base register with some displacement.
 e.g: MOV AL, [BX + 50]
SUB CX, [BX + 6000]
ADD AL, [BD + 05]

 RELATIVE INDEX ADDRESSING MODE

In this the offset address is specified indirectly through index register with some displacement.
e.g: MOV AL, [SI + 50]
MOV BX, [DI + 0350]

 INTRASEGMENT DIRECT ADDRESSING MODE

In this the destination offset address is specified directly either direct address or through any level
name.
e.g: JMP 6000
JMP START
CALL BACK

 INTRASEGMENT INDIRECT ADDRESSING MODE

In this the destination offset address is specified indirectly through register on memory.
e.g: JMP BX
JMP [BX]
CALL [SI]

 INTERSEGMENT DIRECT ADDRESSING MODE

In this the destination segment and offset address is specified directly using FAR pointer.
e.g: START PROC FAR
JMP START
BACK PROC FAR
CALL BACK

 INTERSEGMENT INDIRECT ADDRESSING MODE

In this the destination segment and offset address is specified indirectly using DWORD pointer.
e.g: JMP DWORD PTR [BX]
CALL DWORD PTR [SI]

 STRING ADDRESSING MODE

All string instruction coming under this category.
e.g: MOVSB
MOVSW
CMP SB
 I/O ADDRESSING MODE

All I/O instructions are coming under this category.

e.g: IN AL, 05
OUT DX, AL
IN AL, DX

 IMPLIED ADDRESSING MODE:

In this case no separate operand is used,

 e.g: LLD
AAA
AAM
DAA
PUSHF

2. Explain in detail about memory access mechanism in 8086.

In 8086 memory is interfaced and accessed by segmented concept.

Reason for having segmentation

As the address lines of the 8086 microprocessor is 20, so each location in the memory can be
identified by 20-bit address. Whenever microprocessor accessed the memory the 20-bit address
must be stored in the 20-bit register, but 8086 is designed to support 16-bit architecture, so no
20-bit registers are available in 8086 to hold the address. To avoid this problem the segmented
memory is used, i.e., by using 16-bit register the whole 1MB of memory can be addressed.

Concept
In this concept the total 1MB of memory is logically divided into numbers of segments, where
the maximum length of each segment is up to 64Kbytes. So to accommodate the 1MB of
memory, and assuming the maximum length of 64KB of a segment, 16 segments are possible.
Considering one particular segment, each memory location is identified by two logical address
components.

• Segment address: this 16-bits logical address indicates the starting address of a segment,
and which is fixed for a particular segment.
• Offset address: This 16-bits logical address indicates the individual locations in that
particular segment, and which varies location wise.

The offset address sometimes referred as effective address (EA). The Intel manuals tend to use
the term ‘effective address’ when discussing the machine language and the term “Offset address”
when discussing the assembler language.
Using the two above logical address components the 20-bits physical address can be calculated.
Sometimes “displacement” is also used for calculation of physical address which is discussed in
the later portion.

Physical Address Calculation

The 20-bit physical address can be calculated by using the following formula.
(Physical Address)20-bits= [(Segment Address)16-bits × 1610 (or 10H)] + (Offset
Address)16-bits
When the physical address is calculated to get the multiplication of 16 10 or 10H, segment
address is actually shifted left 4 times to append a 0 (i.e. 0H or 00002) on the right hand side,
then it is simply added with offset address to get the 20-bit physical address (sometimes called
linear address).
For example if the logical addresses are given 2050H: 3000H, then to calculate the physical
address
0010 0000 0101 0000 0000 = 20500H (Shifted version of Segment address)
0011 0000 0000 0000 = 3000H (Offset address)
0010 0011 0101 0000 0000 = 23500H (20- bits physical address/linear address)

Taking another example, if the logical address is 6789H: 5555H, to get the physical address
P.A = 67890H+5555H= 6CDE5H

(Physical address calculation)

3. Draw the structure of 8086 flag register and explain the function of the flags with
examples.

Flag Register contains a group of status bits called flags that indicate the status of the CPU or the result
of arithmetic operations. There are two types of flags:

 The status flags which reflect the result of executing an instruction. The programmer cannot set/reset
these flags directly.
 The control flags enable or disable certain CPU operations. The programmer can set/reset these bits
to control the CPU's operation.

Nine individual bits of the status register are used as control flags (3 of them) and status flags (6 of
them).The remaining 7 are not used. A flag can only take on the values 0 and 1. We say a flag is set if it
has the value 1.The status flags are used to record specific characteristics of arithmetic and of logical
instructions.

Control Flags: There are three control flags

 The Direction Flag (D): Affects the direction of moving data blocks by such instructions as
MOVS, CMPS and SCAS. The flag values are 0 = up and 1 = down and can be set/reset by the
STD (set D) and CLD (clear D) instructions.
 The Interrupt Flag (I): Dictates whether or not system interrupts can occur. Interrupts are
actions initiated by hardware block such as input devices that will interrupt the normal execution
of programs. The flag values are 0 = disable interrupts or 1 = enable interrupts and can be
manipulated by the CLI (clear I) and STI (set I) instructions.
 The Trap Flag (T): Determines whether or not the CPU is halted after the execution of each
instruction. When this flag is set (i.e. = 1), the programmer can single step through his program to
debug any errors. When this flag = 0 this feature is off. This flag can be set by the INT 3
instruction.
Status Flags: There are six status flags

 The Carry Flag (C): This flag is set when the result of an unsigned arithmetic operation is too
large to fit in the destination register. This happens when there is an end carry in an addition
operation or there an end borrows in a subtraction operation. A value of 1 = carry and 0 = no
carry.
 The Overflow Flag (O): This flag is set when the result of a signed arithmetic operation is too
large to fit in the destination register (i.e. when an overflow occurs). Overflow can occur when
adding two numbers with the same sign (i.e. both positive or both negative). A value of 1 =
overflow and 0 = no overflow.
 The Sign Flag (S): This flag is set when the result of an arithmetic or logic operation is negative.
This flag is a copy of the MSB of the result (i.e. the sign bit). A value of 1 means negative and 0
= positive.
 The Zero Flag (Z): This flag is set when the result of an arithmetic or logic operation is equal to
zero. A value of 1 means the result is zero and a value of 0 means the result is not zero.
 The Auxiliary Carry Flag (A): This flag is set when an operation causes a carry from bit 3 to bit
4 (or a borrow from bit 4 to bit 3) of an operand. A value of 1 = carry and 0 = no carry.
 The Parity Flag (P): This flags reflects the number of 1s in the result of an operation. If the
number of 1s is even its value = 1 and if the number of 1s is odd then its value = 0.

Since flag register reflects the happenings inside the 8086 microprocessor, it is called the
Program Status Word (PSW). The contents of PSW, accumulator and other registers are saved in
the stack during the handling of interrupt.

4. Write short notes on following

BIU and EU

Execution Unit (EU)

The functions of execution unit are:

 To tell BIU where to fetch the instructions or data from.
 To decode the instructions.
 To execute the instructions.

During the execution of the instruction, the EU tests the status flags and updates them based on
the results of executing the instruction.

The EU contains the control circuitry to perform various internal operations with the help of
some registers like general purpose registers (AX, BX, CX, DX), pointer registers (SP, BP) and
index registers (SI, DI). A decoder in EU decodes the instruction fetched memory to generate
different internal or external control signals required to perform the operation. EU has 16-bit
ALU, which can perform arithmetic and logical operations on 8-bit as well as 16-bit.
Bus Interface Unit (BIU)

The bus interface unit is responsible for performing all external bus operations.
Specifically it has the following functions:

 Instruction fetching, Instruction queuing, Operand fetching and storage, Address

relocation and Bus control.

 The BIU uses a mechanism known as an instruction stream queue to implement pipeline
architecture.

 This queue permits pre fetch of up to six bytes of instruction code.

BIU contains Instruction queue (IQ), Segment registers (CS,DS,ES,SS), Instruction pointer (IP),
and Address adder. Both units operate asynchronously to give the 8086 an overlapping
instruction fetch and execution mechanism which is called as Pipelining. This results in efficient
use of the system bus and system performance.

5. How is the memory of 8086 microprocessor organized from a hardware point of view?

The BIU has a combined address and data bus, commonly referred to as a time-multiplexed bus.
Time multiplexing address and data information makes the most efficient use of device package
pins. A system with address latching provided within the memory and I/O devices can directly
connect to the address/data bus. The local bus can be demultiplexed with a single set of address
latches to provide non-multiplexed address and data information to the system. The programmer
views the memory or I/O address space as a sequence of bytes. Memory space consists of 1
Mbyte, while I/O space consists of 64 Kbytes. Any byte can contain an 8-bit data element, and
any two consecutive bytes can contain a 16-bit data element (identified as a word). The
discussions in this section apply to both memory and I/O bus cycles. For brevity, memory bus
cycles are used for examples and illustration.
 The memory address space on a 16-bit data bus is physically implemented by dividing
the address space into two banks of up to 512 Kbytes each. One bank connects to the lower half
of the data bus and contains even-addressed bytes (A0=0). The other bank connects to the upper
half of the data bus and contains odd-addressed bytes (A0=1). Address lines A19:1 selects a
specific byte within each bank. A0 and Byte High Enable (BHE) determine whether one bank or
both banks participate in the data transfer.

Physical Data bus Models

Byte transfers to even address transfer information over the lower half of the data bus (see Figure
3-22a). A0 low enables the lower bank, while BHE high disables the upper bank. The data value
from the upper bank is ignored during a bus read cycle. BHE high prevents a write operation
from destroying data in the upper bank. Byte transfers to odd addresses transfer information over
the upper half of the data bus (see Figure 3-22b). BHE low enables the upper bank, while A0
high disables the lower bank. The data value from the lower bank is ignored during a bus read
cycle. A0 high prevents a write operation from destroying data in the lower bank. To access
even-addressed 16-bit words (two consecutive bytes with the least-significant byte at an even
address), information is transferred over both halves of the data bus (see Figure 3-23).
 (16-bit Data Bus Byte Transfers)

(16-bit Data Bus Byte transfers)

(16-Bit Data Bus Even Word Transfers)

A19:1 selects the appropriate byte within each bank. A0 and BHE drive low to enable both banks
simultaneously. Odd-addressed word accesses require the BIU to split the transfer into two byte
operations (see Figure 3-24). The first operation transfers data over the upper half of the bus,
while the second operation transfers data over the lower half of the bus. The BIU automatically
executes the two-byte sequence whenever an odd-addressed word access is performed.
Case 1
Read/Write a byte form/to an even address – A0 will be low and BHE (Active Low) will be high
– Byte is transferred to/from low bank through D0-D7
Example – MOV AH, DS:BYTE PTR[0000]
Case 2
Similar to case 1 except the word access instead of the byte access – Both A0 and BHE (Active
Low) will be asserted low – Low byte of the word through D0-D7 and high byte of the word
through D8-D15
Example – MOV AX, DS:WORD PTR[0000]
Case 3
Read/Write a byte from/to an odd address – A0 will be high and BHE (Active Low) will be
asserted low – Low bank is disabled and high bank is enabled – Byte is transferred through D0-
D7
Example – MOV AL, DS:BYTE PTR[0001]
Case 4
Read/Write a word from/to an odd address – 8086 requires two bus cycles – During the first
machine cycle assert BHE (Active Low) as low and A0 as high – First byte is transferred through
D0-D7 and the second byte is transferred through D8-D15
Example – MOV AX, DS: WORD PTR[0001H]

6. Suppose DS= 8888H, ES = 2345H, CS= 789AH, SS= F123H, BX= 1234H, BP= 3333H,
SI= F000H, DI= 2222H, What physical address are accessed by the following
instruction of 8086 microprocessor?

MOV AH, [BX+SI+10H] PA= 88880H+[1234H+F000H+10H]

MOV BH, [BP] PA= 88880H+3333H
MOV CX, CS:[SI] PA= 789A0H+F0000H
XOR AL, [DI+1111H] PA= 88880+[2222H+1111H]
ADD [2000H], BL PA= 88880H+2000H

7. Write an 8086 assembly language program to find the largest number from the array of
data bytes. Draw the flow chart which support to your program.

Assuming 10 data elements in the array stored at the data segment of address 10000H.
Program: MOV AX, 1000H
MOV DS, AX
MOV CL, 0AH
MOV BX, 0000H
MOV AL, 00H
L2 CMP AL, [BX]
JNC L1
MOV AL, [BX]
 L1 INC BX
LOOP L2
MOV [BX], AL
HLT

8. Write all the string instruction of 8086.

String instruction of 8086

MOVS (MOVe String) instruction

Used for copying a string byte or word at a time. MOVSB for Move String Byte at a time,
MOVSW for Move String Word at a time. MOVSB and MOVSW are more common than
MOVS. Flags are not affected by the execution of MOVS/MOVSB/MOVSW instruction.

CMPS (CoMPare Strings) Instruction

CMPS compares two strings (of equal size), say String1 and String2, a byte or word at a time.
String values remain unaffected. Only flags affected. Basically it performs the subtraction
DS:[SI] - ES:[DI]. CMPSB for comparing Strings Byte at a time. CMPSW for comparing Strings
Word at a time. CMPSB and CMPSW are more common than CMPS.

STOS (STOre String) instruction

STOS is used for creating a string in memory a byte or word at a time. AL/AX contents copied
to memory pointed by ES:[DI]. It does not affect any flag. STOSB is used for storing string
byte at a time. STOSW is used for storing string word at a time. STOSB and STOSW are more
common than STOS. Flags are not affected by the execution of this instruction.
LODS (LOaD String) instruction

LODS is used for processing a string in memory a byte or word at a time. It copies contents of
memory pointed by DS:[SI] into AL or AX. It does not affect any flag. LODSB is used for
loading string byte at a time. LODSW is used for loading string word at a time. LODSB and
LODSW are more common than LODS.

SCAS (SCAn String) instruction

SCAS is used for scanning a string in memory for a particular byte or word. It compares contents
of byte in AL or word in AX with byte or word at memory pointed by ES:[DI]. SCAS
performs AL/AX contents minus byte or word pointed by ES:[DI]. Operand values are not
changed. Flags are affected based on result of subtraction.

9. Explain the register organization of 8086.

Register Organization of 8086

 Accumulator register consists of two 8-bit registers AL and AH, which can be combined
together and used as a 16- bit register AX. AL in this case contains the low-order byte of
the word, and AH contains the high-order byte. Accumulator can be used for I/O
operation and string manipulation.

 Base register consists of two 8-bit registers BL and BH, which can be combined together
and used as a 16-bit register BX. BL in this case contains the low-order byte of the word,
and BH contains the high-order byte. BX register usually contains a data pointer used for
based, based indexed or register indirect addressing.
 Count register consists of two 8-bit registers CL and CH, which can be combined
together and used as a 16-bit register CX. When combined, CL register contains the low
order byte of the word, and CH contains the high order byte. Count register can be used
in Loop, shift/rotate instructions and as a counter in string manipulation.

 Data register consists of two 8-bit registers DL and DH, which can be combined together
and used as a 16-bit register DX. When combined, DL register contains the
low order byte of the word, and DH contains the high order byte. Data register can be
used as a port number in I/O operations. In integer 32-bit multiply and divide instruction
the DX register contains high-order word of the initial or resulting number.
 Stack Pointer (SP) is a 16-bit register pointing to program stack, i.e it is used to store the
offset address for the stack segment. It is also used to save the program status internally
during the interrupt process and in the execution time of PUSH and POP instruction.

 Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is
usually used for based, based indexed or register indirect addressing. Generally it is used
with some displacement. It Can be used to access data in other segments.

 Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register
indirect addressing, as well as a source data addresses in string manipulation instructions.
When string operations are performed, the SI register points to source memory locations
in the data segment which is addressed by the DS register. Thus, SI is associated with the
DS in string operations.

 Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and
register indirect addressing, as well as a destination data addresses in string manipulation
instructions. When string operations are performed, the DI register points to memory
 locations in the data segment which is addressed by the ES register. Thus, DI is
associated with the ES in string operations.
 Flag Register contains a group of status bits called flags that indicate the status of the
CPU or the result of arithmetic operations. There are two types of flags: The status
flags which reflect the result of executing an instruction. The programmer cannot
set/reset these flags directly. The control flags enable or disable certain CPU operations.
The programmer can set/reset these bits to control the CPU's operation.

Control Flags: There are three control flags

 The Direction Flag (D): Affects the direction of moving data blocks by such instructions
as MOVS, CMPS and SCAS. The flag values are 0 = up and 1 = down and can be
set/reset by the STD (set D) and CLD (clear D) instructions.
 The Interrupt Flag (I): Dictates whether or not system interrupts can occur. Interrupts
are actions initiated by hardware block such as input devices that will interrupt the
normal execution of programs. The flag values are 0 = disable interrupts or 1 = enable
interrupts and can be manipulated by the CLI (clear I) and STI (set I) instructions.
 The Trap Flag (T): Determines whether or not the CPU is halted after the execution of
each instruction. When this flag is set (i.e. = 1), the programmer can single step through
his program to debug any errors. When this flag = 0 this feature is off. This flag can be
set by the INT 3 instruction.

Status Flags: There are six status flags

 The Carry Flag (C): This flag is set when the result of an unsigned arithmetic operation
is too large to fit in the destination register. This happens when there is an end carry in an
addition operation or there an end borrows in a subtraction operation. A value of 1 =
carry and 0 = no carry.
 The Overflow Flag (O): This flag is set when the result of a signed arithmetic operation
is too large to fit in the destination register (i.e. when an overflow occurs). Overflow can
occur when adding two numbers with the same sign (i.e. both positive or both negative).
A value of 1 = overflow and 0 = no overflow.
 The Sign Flag (S): This flag is set when the result of an arithmetic or logic operation is
negative. This flag is a copy of the MSB of the result (i.e. the sign bit). A value of 1
means negative and 0 = positive.
 The Zero Flag (Z): This flag is set when the result of an arithmetic or logic operation is
equal to zero. A value of 1 means the result is zero and a value of 0 means the result is
not zero.
 The Auxiliary Carry Flag (A): This flag is set when an operation causes a carry from
bit 3 to bit 4 (or a borrow from bit 4 to bit 3) of an operand. A value of 1 = carry and 0 =
no carry.
  The Parity Flag (P): This flags reflects the number of 1s in the result of an operation. If
the number of 1s is even its value = 1 and if the number of 1s is odd then its value = 0.

Instruction Pointer (IP) is a 16-bit register. This is a crucially important register which is used
to control which instruction the CPU executes. The ip, or program counter, is used to store the
memory location of the next instruction to be executed. The CPU checks the program counter to
ascertain which instruction to carry out next. It then updates the program counter to point to the
next instruction. Thus the program counter will always point to the next instruction to be
executed.

Segment RegisterMost of the registers contain data/instruction offsets within 64 KB memory

segment. There are four different 64 KB segments for instructions, stack, data and extra data. To
specify where in 1 MB of processor memory these 4 segments are located the processor uses four
segment registers.

Instruction Pointer (IP) is a 16-bit register. This is a crucially important register which is used
to control which instruction the CPU executes. The ip, or program counter, is used to store the
memory location of the next instruction to be executed. The CPU checks the program counter to
ascertain which instruction to carry out next. It then updates the program counter to point to the
next instruction. Thus the program counter will always point to the next instruction to be
executed.

Segment Register
Most of the registers contain data/instruction offsets within 64 KB memory segment. There are
four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1
MB of processor memory these 4 segments are located the processor uses four segment registers.

Instruction Queue (IQ.

 The BIU uses a mechanism known as an instruction stream queue to implement pipeline
architecture.
 This queue permits pre-fetch of up to six bytes of instruction code. Whenever the queue
of the BIU is not full, it has room for at least two more bytes and at the same time the EU
is not requesting it to read or write operands from memory, the BIU is free to look ahead
in the program by prefetching the next sequential instruction.
 These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the
BIU fetches two instruction bytes in a single memory cycle.
 After a byte is loaded at the input end of the queue, it automatically shifts up through the
FIFO to the empty location nearest the output.
 The EU accesses the queue from the output end. It reads one instruction byte after the
other from the output of the queue. If the queue is full and the EU is not requesting access
to operand in memory.
10. Interface four 16×8 memory chips using 8086 and also find the memory map.

A15 A0 BHE Function

0 0 0 16 bit word transfer at RAM1
0 0 1 8 bit transfer at even RAM1
0 1 0 8 bit transfer at odd RAM1
1 0 0 16 bit word transfer at RAM2
1 0 1 8 bit transfer at even RAM2
1 1 0 8 bit transfer at odd RAM2

Memory Mapping

RAM1
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

F0000H to F7FFFH

RAM2
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

F8000H to FFFFFH
11. Explain pipelining used in 8086 microprocessor for efficient operation.

 The BIU uses a mechanism known as an instruction stream queue to implement pipeline
architecture.
 This queue permits pre-fetch of up to six bytes of instruction code. Whenever the queue
of the BIU is not full, it has room for at least two more bytes and at the same time the EU
is not requesting it to read or write operands from memory, the BIU is free to look ahead
in the program by prefetching the next sequential instruction.
 These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the
BIU fetches two instruction bytes in a single memory cycle.
 After a byte is loaded at the input end of the queue, it automatically shifts up through the
FIFO to the empty location nearest the output.
 The EU accesses the queue from the output end. It reads one instruction byte after the
other from the output of the queue. If the queue is full and the EU is not requesting access
to operand in memory.
 These intervals of no bus activity, which may occur between bus cycles are known as Idle
state.
 If the BIU is already in the process of fetching an instruction when the EU request it to
read or write operands from memory or I/O, the BIU first completes the instruction fetch
bus cycle before initiating the operand read / write cycle.
 The BIU also contains a dedicated adder which is used to generate the 20bit physical
address that is output on the address bus. This address is formed by adding an appended
16 bit segment address and a 16 bit offset address.
 For example: The physical address of the next instruction to be fetched is formed by
combining the current contents of the code segment CS register and the current contents
of the instruction pointer IP register.
 The BIU is also responsible for generating bus control signals such as those for memory
read or write and I/O read or write.
12. Write the program to find the smallest number in the data array of ten numbers.

MOV CL, 09H

MOV BX, 2000H
MOV AL, [BX]
L2 INC BX
CMP AL, [BX]
JC L1
MOV AL, [BX]
L1 LOOP L2
MOV [2050H], AL
HLT
13. Interface two 4K X 8 EPROMS and two 4K X 8 RAMs chips with 8086
microprocessor. Select the suitable memory maps.

14. Write an assembly language program to add a series of decimal bytes using 8086
microprocessor.

MOV AX, 2000H

MOV DS, AX (Assuming the segment address 2000H)
MOV CL, 0AH
MOV SI, 1000H
L2 ADD AL, [SI]
JNC L1
INC AH
L1 INC SI
LOOP L2
MOV [SI], AX
HLT

15. With suitable diagram explain about the 8086 microprocessor architecture.
 16. Write the addressing mode and find the physical address of the following instructions
of 8086 microprocessor. Assume the content of registers are:
CS=1000H, DS=1200H, ES=1501H, SS=3408H, SI=2300H, DI=0900H, BX=0FFFH
and BP=1A00H.
i. MOV [SI],AL
ii. ADD CX,[BP+DI]
iii. MOV [2456H],BP
iv. SCASB
v. MOV[DI+08H],SI

i) Physical Address: 12000 + 2300 = 14300H

ii) Physical Address: 34080 + 1A00 + 0900 = 36380H
iii) Physical Address: 12000 + 2456 = 14456H
iv) Physical Address: 15010 + 0900 = 15910H
v) Physical Address: 15010 + 0900 + 8 = 15918H

17. What the function and addressing modes of the following instructions of
microprocessor/microcontroller?
ADD [DI+05H], CX
MOV A, M
MOV [SI], AL

ADD [DI+05H], CX:

The content of CX is copied into the memory of address [DS: DI+05H] and Addressing mode is
relative index addressing mode
MOV A, M
The content of memory whose address is stored in HL register pair is copied into the
Accumulator and Addressing mode is memory indirect addressing mode
MOV [SI], AL
The content of AL is copied into the memory of address [DS: SI] and Addressing mode is index
addressing mode.

18. Write an ALP in 8086 to transfer 10 data words from offset address 2000H to offset
address 3000H.
MOV AX, 5000H
MOV DS, AX
MOV ES, AX
MOV CL, 0AH
MOV SI, 2000H
MOV DI, 3000H
CLD
REP MOBSB
HLT
19. Describe the operation performed by the following instructions. Also mention the type
of instructions group and the addressing mode in which each instruction falls.
 XCHG [DATA], AX
 IMUL BYTE PTR [BX+SI]
 NOT WORD PTR [BX+DI]
 JNP 1000H

XCHG [DATA], AX
AX value is copied into memory addressed by [DS:DATA]
Data Transfer group
Direct addressing mode

IMUL BYTE PTR [BX+SI]

AL value is multiplied with 8 bit memory content addressed by [DS:BX+SI]
Arithmetic group
Based indexed addressing mode

NOT WORD PTR [BX+DI]

16 bit content of memory addressed by [DS: BX+DI] is complemented.
Logical group
Based indexed addressing mode

JNP 1000H
Jump when no parity (Jump into the offset address when PF=0)
Branching group
Intra segment direct addressing mode

20. Write the MOV instructions of 8086 in following five different addressing mode types.
 Direct addressing mode
 Register indirect addressing mode
 Base indexed addressing mode
 String addressing mode

Direct addressing mode: MOV AL, [2345H]

Register indirect addressing mode: MOV AL, [BX]
Base indexed addressing mode: MOV AL, [BX+SI]
String addressing mode: MOVSB or MOVSW
23. Write an assembly language program for 8086 microprocessor to multiply two 8-bit
numbers stored in two different locations and store the result in another location
using both direct and indirect addressing.
Direct
MOV AX, 2000H
MOV DS, AX
MOV AL, [1100H]
MOV BX, 3000H
MOV DS, BX
MOV CL, [1200H]
MUL CL
MOV BX, 4000H
MOV DS, BX
MOV AL, [1500H]
MOV [1500H], AX
HLT

Indirect
MOV AX, 2000H
MOV DS, AX
MOV SI, 1100H
MOV AL, [SI]
MOV BX, 3000H
MOV DS, BX
MOV SI, 1200H
MOV CL, [SI]
MUL CL
MOV BX, 4000H
MOV DS, BX
MOV SI, 1500H
MOV [SI], AX
HLT

24. Develop an 8086 microprocessor based program to transfer 50 bytes of data from
memory location starting from 2000Hto 3000H, using the string instruction MOVSB.
MOV AX, 5000H
MOV DS, AX
MOV ES, AX
MOV CL, 32H
MOV SI, 2000H
 MOV DI, 3000H
CLD
REP MOBSB
HLT

25. See if there is any syntax errors in the following instructions

(a) MOV BH, AX (b) MOV DX, CI (c) ADD AL 2073H
(d) MOV 7632H, CX (e) IN BL, 04H

26. Assume that DS=1120H, SI=2498H and AX=17FEH. Determine the memory address
being accessed by ‘MOV [SI], AX’ and specify the content of these locations after
executing this instruction.
27. Write an assembly code to move a string of 16 bytes long from the offset address
0200H to 0300H in the segment 7000H. Discuss an alternate way of writing this code.
28. (a) Give examples for each of the addressing modes of 8086 processor.
(b) Which of the following are invalid assembly language instructions?
i. MOV BP, AL
ii. MOV WORD_OP [BX+4*3][DI],SP
iii. MOV WORD_OP1, WORD_OP2
iv. MOV AX, WORD_OP1 [DX]
v. MOV CS, AX
vi. MOV DS, BP
vii. MOV SAVE_WORD, DS
29. Suppose DS=8888H, ES=2345H, CS=789AH, SS=F123H, BX=1234H, BP=3333H,
SI=F000H. What physical address in memory is accessed by the following
instructions?
i. MOV AH, [BX+SI+10H]
ii. MOV BH, [BP]
iii. MOV CL, [CS: SI]

30. Explain with suitable example the unconditional jump instructions of 8086
microprocessor.
31. Write a program to swap between memory contents within a segment and in different
segment in both direct and indirect addressing.
 Intel-8255

1. Write down the features of 8255 PPI.

Features
 40 pins IC designed by CMOS technology.
 Among 40 pins , 24 pins are used for I/O operation. They can be grouped into two 8-bit
parallel ports (port A, port B) and remaining 8 pins for port C. Port C can also be used as
port C upper (PCu) and port C lower (PCl) each of 4-bits.
 All ports can be programmed to act as input port or output port or both by writing the
control word in the control register.
 Three programming modes ( mode 0, mode 1, mode 2) for all ports and bit set reset
(BSR) mode for port C.
 8-bit bidirectional system data bus with standard microprocessor interface.
 Compatible with almost all Intel family.
 Used to interface the keyboard and parallel printer in many micro controller system.

2. Explain the I/O modes of operation of 8255 PPI.

Operating modes of 8255A

When the reset pin goes ‘high’, all the ports are set to the input mode (i.e, all 24 pins will
be in the high impedance state). After the reset is removed the 8255A remains in the input mode.
The 8255A is having a control register (8-bit). The content of the register is called control word,
which specifies the I/O operation for each port. The MSB(D7) of the control register decides the
two possible modes of operation, BSR mode and I/O mode.
Again I/O mode is divided into three different modes, Mode 0, Mode 1, and Mode 2.

CONTROL REGISTER

I/O Mode
Mode 0 Operation
This functional configuration provides simple input and output operation for each of three
ports. No handshaking signals are exchanged, data are simply written to or read from a specified
port.
Mode 0 basic functional definition
 Two 8-bit ports and two 4-bit ports
 Any port can be input or output
 Output are latched
 Input are not latched
 16 different I/O configurations are possible in this mode.

Mode 1 Operation

This functional configuration provides a means for transferring I/O data to or from a specified
port in conjunction with strobes or handshaking signals. In Mode 1, Port A and Port B uses the
lines on port C to generate or accept the handshaking signals.
Mode 1 Basic Functional Definitions
 Two groups (Group A and Group B)
 Each group contains one 8-bit data port and one 4-bit control port.
 When port B used as a I/O port , then PC0,PC1,PC2 are used for handshaking or control.
 When Port A used as I/P port , then PC3,PC4,PC5 are used for controlling and when port
A used as O/P port ,then PC3,PC6,PC7 are used for controlling.
 The combination of Mode 0 and Mode 1 is also possible.

Mode 2 operation

This functional configuration provides a mean for communicating with a peripheral device on a
single 8-bit bus for both transmitting and receiving the data. Handshaking signal are
provide to maintain proper data flow in a similar manner as in mode 1.

Mode 2 basic functional definition

 Applicable for Port A only.
 When port A is used for mode 2 operation then PC3 to PC7 are used for controlling and
at that time port is used either in mode 0 or in mode 1operation.
 It is otherwise called as strobe bidirectional mode.
3. Explain the control word format for 8255 PPI for I/O mode

CONTROL WORD FORMAT FOR I/O MODE

4. Write the control word for 8255 operated in mode 1 and specifications are PA-
Bidirectional mode 2, PB- mode 0 & I/P, PC0, PC1 & PC2-O/P.
5. Suppose switch have been interfaced at port A and LEDs are at port B in peripheral
mapped I/O. Write down the program in 8086 assembly language to read data from
switches and display at LEDs in mode 0.

Program: MOV AL, 90H

OUT 83H, AL
IN AL, 80H
OUT 81H, AL

6. Write the sequence of instructions needed to initialize the control register of 8255A,
so that the port A is an output port and port B and C are input port in mode )
operation. Also write the program that will input the contents of port B and C, AND
them together, and output the results to port A in memory mapped I/O scheme.

Program: Assuming the segment address is already defined.

MOV AL, 8BH
MOV [8003H], AL
MOV AL, [8001H]
MOV BL. [8002H]
AND AL, BL
MOV [8000H], AL

7. Explain the BSR mode of 8255 PPI with control word format.

BSR mode
It is only applicable for port C and other ports are unaffected.
This becomes operational by resetting the D7 bit of control register.
Any of the eight bits of Port C can be Set or Reset using a single OUT put instruction. This
feature reduces software requirements in Control-based applications . When Port C is
 being used as status/control for Port A or B these Bits can be set or reset by just as if they
were data output port.

8. Suppose a switch is connected to d7 bit of port C. Write down a program to toggle

the switch at some time delay.

Ans: Control word to set PC7: 0FH and to reset the PC7: 0EH

BACK: MOV AL, 0FH

OUT 83H, AL
CALL NEAR PTR XXX
MOV AL, 0EH
OUT 82H, ALH XXX: MOV CL, Count
CALL NEAR PTR XXX L1: NOP
JMP BACK DEC CL
JN Z L1
RET
Intel-8051
1. Explain in detail about internal RAM organization of 8051 microcontroller.
Sol:

2. Write the program in order to subtract two 16 bit numbers using 8051
microcontroller.
Sol:
N1-16 bit no, N2-16 bit no
Mov A, N1_low
Mov B, N2_low
Subb A, B
Mov R0,A
Mov A, N1_high
Mov B, N2_high
Subb A, B
Mov R1, A
Sjmp $
3. Write the addressing modes of 8051 microcontroller.

The CPU can access data in various ways, which are called addressing modes
 Immediate
 Register
 Direct
 Register indirect
 Indexed

Immediate Addressing Modes

The source operand is a constant

 The immediate data must be preceded by the pound sign, “#”
 Can load information into any registers, including 16-bit DPTR register
e.g MOV A,#25H ;load 25H into A
MOV R4,#62 ;load 62 into R4
MOV B,#40H ;load 40H into B
MOV DPTR,#4521H ;DPTR=4512H
MOV DPL,#21H ;This is the same
MOV DPH,#45H ;as above

Register Addressing Modes

 Use registers to hold the data to be manipulated

e.g MOV A,R0 ;copy contents of R0 into A

MOV R2,A ;copy contents of A into R2
ADD A,R5 ;add contents of R5 to A
ADD A,R7 ;add contents of R7 to A
MOV R6,A ;save accumulator in R6

Direct Addressing Modes

 It is most often used the direct addressing mode to access RAM locations 30 – 7FH
 The entire 128 bytes of RAM can be accessed
 The register bank locations are accessed by the register names

e.g MOV A, 4 ;is same as

MOV A, R4; which means copy R4 into A

Register Indirect Addressing Modes

 A register is used as a pointer to the data

  Only register R0 and R1 are used for this purpose
 R2 – R7 cannot be used to hold the address of an operand located in RAM
 When R0 and R1 hold the addresses of RAM locations, they must be preceded by the
“@” sign

e.g MOV A,@R0 ;move contents of RAM whose ;address is held by R0 into A
MOV @R1,B ;move contents of B into RAM ;whose address is held by R1

Index Addressing Modes

 Indexed addressing mode is widely used in accessing data elements of look-up table
entries located in the program ROM
 The instruction used for this purpose is MOVC A,@A+DPTR
 Use instruction MOVC, “C” means code
 The contents of A are added to the 16-bit register DPTR to form the 16-bit address of the
needed data

4. Write down the key features of 8051 microcontroller.

 8-bit CPU

 On-chip oscillator

 Harvard architecture

 4 KB of on-chip ROM

 128 bytes of on-chip RAM

 21 special function registers

 32 I/O lines

 64 KB address space for external Program memory

 64 KB address space for external Data memory

 Two 16-bit timer/counters

 One full-duplex serial port

 Five-source interrupt structure with two priority levels

 Bit addressability for Boolean processing

 2. Draw the block diagram of 8051 MCU.

5. Explain the register organization of 8051 MCU.

Register Organization of 8051

 General purpose registers

- 4 banks of 8-registers
The 8051 uses 8 "R" registers which are used in many of its instructions. These
"R" registers are numbered from 0 through 7 (R0, R1, R2, R3, R4, R5, R6, and
R7). These registers are generally used to assist in manipulating values and
moving data from one memory location to another.
 Twenty one Special function registers

- A , B , DPL, DPH, IE , IP , P0 , P1 , P2 , P3 , PCON, PSW,

SCON, SBUF, SP, TMOD, TCON, TL0, TH0, TL1, TH1
Accumulator (A)
 The A register is the accumulator register. ACC is the location of the accumulator
in the Internal Data Memory.
 Accumulator is one of the most-used SFRs on the 8051 since it is involved in so
many instructions. The Accumulator resides as an SFR at E0h, which means the
instruction MOV A,#20h is really the same as MOV E0h,#20h.
Register (B)
 B register or accumulator B at address F0H is used along with the accumulator for
multiply and divide operations.
 MUL AB: multiplies 8 bit unsigned values in A and B and leaves the 16 bit result
in A (low byte) and B (high byte).
 DIV AB: divided A by B, leaving the integer result in A and remainder in B
 B register is bit-addressable.
PSW (program status register)

 The carry (CY), auxiliary carry (AC), user flag 0 (FO), register bank select I (RS I),
register bank select 0 (RSO), overflow (OV) and parity (P) flags reside in the Program
Status Word (PSW) Register.
 These flags are bit memory- mapped within the byte-memory-mapped PSW.
 The PSW flags record processor status information and control the operation of the
processor.
 The CY, AC, and OV flags generally reflect the status of the latest arithmetic operation.
The P flag always reflects the parity of the A register.
 The carry flag is also a Boolean accumulator for bit operations.
 FO is a general purpose flag which is pushed onto the stack as part of a PSW save.
 The two Register Bank select bits (RS I 'and RSO) determine which of the four 8-
Register Banks is selected.

Stack Pointer

 Stack pointer (SP) is an 8-bit register at address 81H

 It contains the address of the data item currently on top of the stack.
 Stack operations include pushing data on the stack and popping data off the stack
 Pushing increments SP before writing the data
 Popping from the stack reads the data and decrements the SP
 8051 stack is kept in the internal RAM
 Depending on the initial value of the SP, stack can have different sizes
 Example: MOV SP,#5FH
 On 8051 this would limit the stack to 32 bytes since the uppermost address of on chip
RAM is 7FH.
 The default value of SP (after system reset) is 07H.
 This result in the first stack write operation to store data in location 08H which means
that register bank 1 (and possible 2 and 3) are not available.

Data Pointer

 The 16-bit Data Pointer (DPTR) register is the concatenation of registers DPH (data
pointer's high-order byte) and DPL (data pointer's low-order byte).
  The DPTR is used in Register-Indire91 Addressing to move Program Memory constants,
to move External Data Memory variables, and to branch over the 64K Program Memory
address space.

Program Counter

 The I6-bit Program Counter (PC) controls the sequence in which the instructions stored
in program memory are executed.

PCON

 The Power Control SFR is used to control the 8051's power control modes. Certain
operation modes of the 8051 allow the 8051 to go into a type of "sleep" mode which
requires much less power. These modes of operation are controlled through PCON.
Additionally, one of the bits in PCON is used to double the effective baud rate of the
8051's serial port.

TCON
 The Timer Control SFR is used to configure and modify the way in which the 8051's two
timers operate. This SFR controls whether each of the two timers is running or stopped
and contains a flag to indicate that each timer has overflowed. Additionally, some non-
timer related bits are located in the TCON SFR. These bits are used to configure the way
in which the external interrupts are activated and also contain the external interrupt flags
which are set when an external interrupt has occurred.

TMOD
 The Timer Mode SFR is used to configure the mode of operation of each of the two
timers. Using this SFR your program may configure each timer to be a 16-bit timer, an 8-
bit auto reload timer, a 13-bit timer, or two separate timers. Additionally, you may
configure the timers to only count when an external pin is activated or to count "events"
that are indicated on an external pin.

SCON
 The Serial Control SFR is used to configure the behaviour of the 8051's on-board serial
port. This SFR controls the baud rate of the serial port, whether the serial port is activated
to receive data, and also contains flags that are set when a byte is successfully sent or
received.

SBUF
 The Serial Buffer SFR is used to send and receive data via the on-board serial port. Any
value written to SBUF will be sent out the serial port's TXD pin. Likewise, any value
which the 8051 receives via the serial port's RXD pin will be delivered to the user
 program via SBUF. In other words, SBUF serves as the output port when written to and
as an input port when read from.

IP (Interrupt Priority)
 The Interrupt Priority SFR is used to specify the relative priority of each interrupt. On the
8051, an interrupt may either be of low (0) priority or high (1) priority. An interrupt may
only interrupt interrupts of lower priority. For example, if we configure the 8051 so that
all interrupts are of low priority except the serial interrupt, the serial interrupt will always
be able to interrupt the system, even if another interrupt is currently executing. However,
if a serial interrupt is executing no other interrupt will be able to interrupt the serial
interrupt routine since the serial interrupt routine has the highest priority.

P0
 This is input/output port 0. Each bit of this SFR corresponds to one of the pins on the
microcontroller. For example, bit 0 of port 0 is pin P0.0, bit 7 is pin P0.7. Writing a value
of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a
value of 0 will bring it to a low level.

P1
 This is input/output port 1. Each bit of this SFR corresponds to one of the pins on the
microcontroller. For example, bit 0 of port 1 is pin P1.0, bit 7 is pin P1.7. Writing a value
of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a
value of 0 will bring it to a low level.

P2
 This is input/output port 2. Each bit of this SFR corresponds to one of the pins on the
microcontroller. For example, bit 0 of port 2 is pin P2.0, bit 7 is pin P2.7. Writing a value
of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a
value of 0 will bring it to a low level.

P3
 This is input/output port 3. Each bit of this SFR corresponds to one of the pins on the
microcontroller. For example, bit 0 of port 3 is pin P3.0, bit 7 is pin P3.7. Writing a value
of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a
value of 0 will bring it to a low level.

(Also see the program whichever discussed in the class)