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    DC_A4

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    DC_A4

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    DC_A4

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    You are on page 1of 6

    NAME: T.

    ANKUSH REDDY DATE:


    ROLL NO: 20EG104251 PAGE NO:

    EXPERIMENT-4
    VERILOG HDL CODE TO REALIZE 3 TO 8 DECODER AND 8
    TO 3 ENCODER.
    Aim: To realize 3 to 8 decoder and 8 to 3 encoder Xilinx with Verilog HDL programming
    language.
    Apparatus: ISE Xilinx 9.2i.

    Theory:
    Binary code of N digits can be used to store 2 distinct elements of coded information. This is
    N

    what encoders and decoders are used for. Encoders convert 2 lines of input into a code of N bits
    N

    and Decoders decode the N bits into 2 lines.


    N

    An encoder is a combinational circuit that converts binary information in the form of a 2 input
    N

    lines into N output lines, which represent N bit code for the input. For simple encoders, it is
    assumed that only one input line is active at a time.
    A decoder does the opposite job of an encoder. It is a combinational circuit that converts n lines
    of input into 2n lines of output.
    Source Code: (3 to 8 Decoder)
    Data flow Model:
    module decoder38(

    input [2:0] a,

    output [7:0] d

    );

    assign d[0]=(~a[2])&(~a[1])&(~a[0]);

    assign d[1]=(~a[2])&(~a[1])&(a[0]);

    assign d[2]=(~a[2])&(a[1])&(~a[0]);

    assign d[3]=(~a[2])&(a[1])&(a[0]);

    assign d[4]=(a[2])&(~a[1])&(~a[0]);

    assign d[5]=(a[2])&(~a[1])&(a[0]);

    assign d[6]=(a[2])&(a[1])&(~a[0]);

    assign d[7]=(a[2])&(a[1])&(a[0]);

    ANURAG UNIVERSITY DIGITAL CIRCUITS AND SIMULATION LAB ECE DEPARTMENT


    NAME: T.ANKUSH REDDY DATE:
    ROLL NO: 20EG104251 PAGE NO:

    endmodule

    Test bench Model:


    module decoder38_tb(
    );
    reg a;
    reg b;
    reg c;
    wire [7:0]d;
    decoder38 uut(a,b,c,d);
    initialbegin
    a=0;b=0;c=0;#100;
    a=0;b=0;c=1;#100;
    a=0;b=1;c=0;#100;
    a=0;b=1;c=1;#100;
    a=1;b=0;c=0;#100;
    a=1;b=0;c=1;#100;
    a=1;b=1;c=0;#100;
    a=1;b=1;c=1;#100;
    end
    endmodule
    8 to 3 Encoder:
    Data flow Model:
    module encoder83(
    input [7:0] d,
    output a,
    output b,
    output c
    );
    assign a=d[4]|d[5]|d[6]|d[7];
    assign b=d[2]|d[3]|d[6]|d[7];
    assign c=d[2]|d[4]|d[6]|d[7];
    endmodule

    ANURAG UNIVERSITY DIGITAL CIRCUITS AND SIMULATION LAB ECE DEPARTMENT


    NAME: T.ANKUSH REDDY DATE:
    ROLL NO: 20EG104251 PAGE NO:

    Test bench Model:


    module encoder83_tb();
    reg[0:07]a;
    wire a,b,c;
    encoder38 uut(a,b,c,d);
    initialbegin
    d0=1;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;#100;
    d0=0;d1=1;d2=0;d3=0;d4=0;d5=0;d6=0;d7=0;#100;
    d0=0;d1=0;d2=1;d3=0;d4=0;d5=0;d6=0;d7=0;#100;
    d0=0;d1=0;d2=0;d3=1;d4=0;d5=0;d6=0;d7=0;#100;
    d0=0;d1=0;d2=0;d3=0;d4=1;d5=0;d6=0;d7=0;#100;
    d0=0;d1=0;d2=0;d3=0;d4=0;d5=1;d6=0;d7=0;#100;
    d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=1;d7=0;#100;
    d0=0;d1=0;d2=0;d3=0;d4=0;d5=0;d6=0;d7=1;#100;
    end
    endmodule

    Procedure:
    1. Open Xilinx Vivado software tool and click on new project.
    2. Select Verilog HDL language and proceed to next.
    3. Select the Constraints inputs and outputs used for design.
    4. Select Zedboard. A file will be selected write the code and save the file.
    5. Check for errors, if any correct them.
    6. Now add a source file for writing test bench code.
    7. Write Test bench code and run synthesis.
    8. Now run behavioral simulation for output waveform.

    Applications:
    1. Speed synchronization of multiple motors in industries.
    2.War field flying robot with a night vision flying camera.

    ANURAG UNIVERSITY DIGITAL CIRCUITS AND SIMULATION LAB ECE DEPARTMENT


    NAME: T.ANKUSH REDDY DATE:
    ROLL NO: 20EG104251 PAGE NO:

    3.A robotic vehicle with the metal detector.


    4.RF-based home automation system.
    5.Automatic health monitoring systems.

    Result: 3 to 8 decoder and 8 to 3 encoder using Verilog HDL is realized in Xilinx ISE 9.2i
    Software tool.

    ANURAG UNIVERSITY DIGITAL CIRCUITS AND SIMULATION LAB ECE DEPARTMENT


    NAME: T.ANKUSH REDDY DATE:
    ROLL NO: 20EG104251 PAGE NO:

    Output:(3 to 8 Decoder)

    ANURAG UNIVERSITY DIGITAL CIRCUITS AND SIMULATION LAB ECE DEPARTMENT


    NAME: T.ANKUSH REDDY DATE:
    ROLL NO: 20EG104251 PAGE NO:

    8 to 3 Encoder:

    ANURAG UNIVERSITY DIGITAL CIRCUITS AND SIMULATION LAB ECE DEPARTMENT

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