Department of Electrical & Electronic Engineering

University of Rajshahi
Course Title: - VLSI Circuits & Design Course Title: - EEE 4121
Section: - A Session: - 2016-17

Question
Chap.1 IC trends, technology and design approaches. MOS device: structure, operation,
threshold voltage and characteristics.
Q. 01 Describe the three domains of IC design.
02 How to evaluate the performance of a digital circuit?/ Discuss the design matrics of
VLSI design
03 Describe the VLSI design flow.
04 What are the issues in integrated circuit?
05 Explain the operation of enhancement type nMOS transistor.
06 What is CMOS Technology? Give the advantages of CMOS IC.
07 Define threshold voltage.
Deduce the expression of threshold voltage of MOSFET
08 Deduce the current expression of MOSFET for the linear region/saturation region.
09 What is body effect?
10 Calculate the drain current……………..
Chap.2 Ratioed circuits: NMOS inverter with resistive and transistor load, Pseudo NMOS
inverter.
Ratioless circuits: CMOS inverters: operation, transfer characteristics, design for
equal rise and fall time, propagation delay, rise time, fall time and power
consumption estimation. NMOS pass transistor and CMOS pass gate circuits.
Buffer chain design to drive large capacitive load.
Q. 01 Draw the voltage transfer characteristics of a practical inverter and illustrate the critical
voltage points.
02 Define noise margins. Explain how a greater noise margin helps in reducing the effect
of external noise in digital circuits.
03 Calculate the noise margin of a digital logic circuit………
04 Derive the expression of critical voltage of resistive load inverter.
05 MOS inverter with enhancement-type nMOS load
06 What is propagation delay in CMOS inverter?
07 Define rise time and fall time of CMOS inverter. Draw the output waveform of a
CMOS inverter showing rise time and fall time.
08 What are interconnect delay models? Discuss each of them in brief.
/Discuss RC delay model/Elmores delay.
09 Explain why a pMOS transistor is used in the pull-up network and the nMOS transistor
is used in the pull-down network in CMOS circuits.
Chap.3 Integrated circuit fabrication technology: Microelectronic technology, planner
process, photolithography, BJT fabrication, FET fabrication, CMOS technology-
CMOS process flow, design rules. Monolithic diodes, metal-semiconductor
 contact, IC resistor and capacitor, IC packaging, characteristics of IC components,
microelectronic circuit layout, printed circuit board. Estimation of resistance and
capacitance from layout. Layout matching. Stick diagram and area estimation
from stick diagram. Reliability issues : Latch-up, electromigration
Q. 01 What are the Si single crystal growth technique? Describe one of them
02 Explain Photolithographic process. What are the components of photolithography?
03 Distinguish between positive and negative photoresist.
04 Describe the Si oxidation mechanisms.
05 How diffusion can be done in IC fabrication?
06 State the steps used for nMOS fabrication
07 State the steps used for the fabrication of an n-well CMOS process/p-well/twin tub and
SOI.
08 What is twin tub process? Why it is so called? / Explain the twin-tub process of CMOS
fabrication. What are the advantages of this technique?
09 Explain the latch-up problem of CMOS devices and its prevention techniques
10 What is stick diagram? What are the uses? Draw the stick diagram….
11 How to determine the parasitic resistances and capacitances for the poly wire.
12 Discuss the reliability issues of IC. Discuss about electromigration.
Chap.4 Basic logic gates in CMOS. Synthesis of arbitrary combinational logic in
CMOS, pseudo-NMOS, dynamic CMOS, clocked CMOS and CMOS domino
logic. Structured design: Parity generator, bus arbitration logic, multiplexers
based design, programmable logic array (PLA) design, Field Programmable gate
arrays (FPGA), I/O systems. Clocked sequential circuit design: two phase
clocking, dynamic shift register. CMOS latches and flip flops. Introduction to
VHDL hardware description language
Q. 01 Design a CMOS Inverter, two input NAND gate, two input NOR gate and explain its
operation.
02 What is static CMOS? What is its disadvantages? What are the alternate logic families
in order to reduce the number of transistor?
03 What is pseudo-nMOS? Explain its operation.
04 Explain dynamic CMOS and write down its advantage-disadvantages.
05 Discuss the phase of operation of dynamic CMOS.
06 Explain the operation of Domino logic.
07 Classify programmable logic devices(PLD) based on the architecture and
programmability.
08 Explain the PLA architecture with necessary circuit diagrams and operating principle
09 Explain the PAL architecture with necessary circuit diagrams and operating principle
10 What are the components of an FPGA? Discuss each of them in detail
11 What are the characteristics of FPGA?
12 What are FPGA applications?
13 Explain programming technology of FPGA
14 How FPGA is different from CPU?
15 Write a short note on Hardware Description Language.
 IC Trends, Technology & Design Approaches.
Q. Describe the three domains of IC design.
VLSI design is a sequential process of generating the physical layout of an IC, starting from the
specification of that circuit. The designers first get an idea of a new system or device for a particular
application. This new idea is translated in the form of an integrated circuit chip using the VLSI design
flow. An electronic system has two parts—hardware and software. The IC design can be described in the
following three domains:
 Behavioral
 Structural
 Physical

❑Behavioral: In the behavioral domain, a circuit is described fully by its behavior without describing its
physical implementation or structure.
Map of design specification to formal behavioral description design: -
- Specification on user desires
- Often not formally described
- Design and behavioral spec often developed together
Approach: -
- Use behavioral hardware description language
 Verilog
 VHDL
- HDL is programming language superset
 Support for timing, modules
- Verify HDL implements design specification
 Usually through simulation
- Check that HDL is self-consistent
 Compile and simulate Behavioral Design
❑Structural: In the structural domain, a circuit is described by its components and their interconnections.
Map of behavioral spec to structural spec: -
- Partition into functional blocks - the netlist
- Targets for eventual physical design
Approach: -
- Use behavioral modules as starting point.
- Decompose each block to finer detail
 Function to gates to transistors, etc.
 Stop at manufacturing interface
- Logic design
  Boolean equations.
 Gates
- Simulation to verify structure has correct behavior
- Interconnect verification
- Design rule checking
- Feedback from physical design - back annotation
 For performance verification.
❑Physical: The physical domain deals with actual geometry of the circuit and describes the shape, size,
and locations of its components.
Map from structure to physical implementation: -
- Target technology
- Technology mapping
- Netlist to 2D layout
Approach: -
- Partition into boards, modules, chips, cells, layout
- Place and route
 Fix cell locations
 Route wiring
- Cell layout
- Design rule checking
- Circuit extraction
 Interconnect verification
 Back annotation

Q. How to evaluate the performance of a digital circuit?/ Discuss the design matrics of VLSI
design
To evaluate the performance of a digital circuit must be follow the following design metrics-
❑Functionality: A design size and complexity can be measured by its functionality. For example, what
are the different operations it can perform; or how many number of inputs and outputs the system has.
❑Cost (non-recurring and recurring): The cost of designing and manufacturing of a design directly
gives a measure about the design quality. For example, more metal layers in a design means more
processing steps, and hence more cost.
❑Reliability (noise margin/immunity): A good design must have large noise margins.
❑Performance (speed, power, energy): A good design must have high speed, low power dissipation,
and energy consumption.
❑Speed (delay, operating frequency): The processing speed of the design must be high so that high
frequency inputs can be applied to its input.
❑Time-to-market: The design must be designed, verified, and finally implemented in the form of the
integrated circuit as quick as possible to become available first in the market to beat the competitors.

Q. Describe the VLSI design flow.

The VLSI design flow is a sequence of steps followed to translate the idea of a system into a chip. The
flow is based on the standard design automation tools.
System specifications such as area, speed, and power.
Functional design is done followed by functional verification to check if the design is correct. In this
phase, the design is described at the behavioral level.
The design is implemented at the logic level and verified for its correctness. This is followed by the
transistor level or circuit design verification. the flow is known as logical design.
The physical design which actually deals with the geometry of the chip.
The last and final step is the fabrication and testing of the chip.

Q. What are the issues in integrated circuit?

The performance of the ICs is measured in terms of how many million operations can be performed per
unit time. This indicates that the performance is dependent upon how fast circuits can respond to an input.
In other words, the propagation delay through the circuits or devices must be reduced from microseconds
to nanoseconds.
❑The propagation delay through the circuits depends on process (P), voltage (V), and temperature (T)
conditions, which are very often called PVT or PTV conditions.

❑Increase in power dissipation of the integrated circuits. With a large number of devices packed into a
small area, the power dissipation in a chip is almost 1 kW which is equivalent of 10 filament bulbs of 100
W! The active and standby power dissipation of the chip has already been almost equal.
❑Gate Delay
❑Interconnect Delay

Q. What is CMOS Technology? Give the advantages of CMOS IC

CMOS, which is short for Complimentary Metal-Oxide Semiconductor, is a predominant technology for
manufacturing integrated circuits. Generally, the CMOS Technology is associated with VLSI or Very
Large-Scale Integrated Circuit, where a few millions or even billions of transistors specifically MOSFET
are integrated into a single chip or die. The CMOS Technology uses both NMOS and PMOS to realize
various logic functions. Both the N-channel MOSFET and the P-channel MOSFET are design in such a
way that they have matching characteristics
The advantages of CMOS IC given below-.
❑ Easy scaling down of MOS device ❑ Low area due to less device requirement
dimensions ❑ Low fabrication cost
❑ Low power dissipation

Q. Explain the operation of enhancement type nMOS transistor.

The MOSFET, which is commonly known as MOS transistor has four terminals The source terminal
serves as the source of carriers of either electron or hole. The drain terminal collects the carriers flown
from the source terminal. The carriers flow from the source to the drain terminal through a conducting
path called channel. The flow of carriers in the channel is controlled by applying voltage at a third
terminal called gate of the MOSFET. The channel can be created either physically or electrically.

If the MOSFET is normally OFF, and is turned ON by applying voltage at the gate terminal, then the
MOSFET is known as enhancement-type MOSFET. The enhancement-type MOSFET, the channel is
created electrically by applying voltage at the gate terminal.
A semiconductor, p-type, is taken as a substrate. On the substrate, two diffusion regions are created. If the
substrate is p-type, the diffusion regions are n+-type. The diffusion regions are known as source and
drain. Between the source and drain, an oxide layer is formed on top of the substrate. The oxide layer is
known as gate oxide. On top of the oxide layer a metal or polysilicon is deposited. Four metal contacts are
taken from the source, gate, drain, and the bulk to form the electrodes.
If a voltage is applied at the gate terminal, a conducting channel is formed underneath the oxide layer
between the source and drain. nMOS is called due to the channel is formed with electron.
Depending on the voltage applied at the gate terminal, the operation of MOSFET is divided into three
conditions:
❑Accumulation
❑Depletion
❑Inversion
Accumulation: - If a negative voltage is applied at the gate terminal, the majority carriers (holes) from the
p-type substrate are attracted towards the gate terminal and are accumulated underneath the gate oxide
layer. This condition is known as accumulation.
Depletion: - If a small positive voltage is applied, the holes will be repelled into the substrate. The
repelled holes will move into the substrate and create negatively charged fixed acceptor ions underneath
the gate oxide layer. These fixed negatively charged ions form the depletion layer.

Inversion: - If the positive gate voltage is large enough, the majority carrier holes are repelled into the
substrate and the small numbers of minority carrier electrons are attracted towards the gate oxide surface.
The attracted electrons accumulate underneath the gate oxide layer and form a conducting path between
the source and drain. This conducting path is called channel and the condition is known as strong
inversion.

Q. Define threshold voltage. Deduce the expression of threshold voltage of MOSFET

Threshold voltage of a MOSFET is defined as the gate voltage with respect to the source terminal at
which the inversion layer is formed underneath the gate oxide layer which is denoted by Vt .
There are four physical parameters which affects the threshold voltage of MOS structure-
❑ The difference between the work function of the gate and channel
❑ The voltage required to create strong inversion
❑ The voltage required to offset the depletion layer charge
❑ The voltage required to offset the fixed oxide charge
The depletion layer charge density can be derived by solving the Poisson equation as follows:
ρ (i)
∇×E ⃗ =
ϵsi
We know that,
ρ = −q NA
Equation (i) can be written as-
dE ρ
=
dx ϵsi
NA (ii)
dE = −q dx
ϵsi
Integrating on both side of the equation of (ii) we get-
NA (iii)
E = −q x
ϵsi
If the potential be φ equation (iii) can be written as-
dφ
− = E(x)
dx
NA (iv)
Or, dφ = q x dx
ϵsi
Now integrating both sides of Equation (iv) we obtain-
φS xd
NA
∫ dφ = ∫ q x dx
ϵsi
φF 0
NA x2d (v)
Or, φS − φF = q
2ϵsi
Hence, the thickness of the depletion region is given by
2ϵsi |φS − φF |
xd = √
q NA
The depletion layer charge per unit area can be written as
Q = −√2ϵsi q NA |φS − φF |
Under strong inversion condition, the surface potential φS must be equal to −φF. Hence, the depletion
layer charge density per unit area under strong inversion condition can be written as-
Q b0 = −√2ϵsi q NA |−2φF |
If the substrate (bulk) potential is not same as that of the source, the depletion layer charge density
becomes a function of the source-to-bulk voltage, as given by
Q b = −√2ϵsi q NA |−2φF + VSB |
So, the threshold voltage under substrate bias can be written as
Q b Q ox
Vt = ϕms − 2φF − −
Cox Cox
Q b0 Q ox Q b − Q b0
Vt = 𝜙ms − 2φF − − −
Cox Cox Cox
 Q. Deduce the current expression of MOSFET for the linear region/saturation region.
An nMOS transistor with terminal voltages. The source and bulk terminals are connected to the ground.
The voltage VDS is applied at the drain terminal and VGS is applied at the gate terminal.
Let us assume that VGS > Vt so that the channel is formed underneath the gate oxide layer. Because of
voltage difference between the drain and source, the current ID flows from drain to source.
*Equation 2.9 to 2.26 of D. Das
For saturation current Case III from D. Das

Q. What is body effect?

Body effect refers to the change in the MOS transistor threshold voltage resulting from a voltage
difference between the source and substrate. Body effect occurs when the body or substrate of the
transistor is not biased at the same level as that of the source. And this voltage difference between source
and bulk leads to an increase or decrease of the threshold voltage. The variation of the threshold voltage
due to the body effect.

Q. Calculate the drain current

Math- Example 2.1, Example 2.2, Example 2.3 from D. Das
 Ratioed Circuits & Ratioless Circuits
Q. Draw the voltage transfer characteristics of a practical inverter and illustrate the critical
voltage points.
An inverter can be realized with the source of an n-type Metal Oxide Semiconductor (nMOS)
enhancement transistor connected to the ground, and the drain connected to the positive supply rail VDD
through a pull-up device.

The input voltage is applied to the gate of the nMOS transistor with respect to ground and output is taken
from the drain. When the MOS transistor is ON, it pulls down the output voltage to the low level, and that
is why it is called a pull-down device, and the other device, which is connected to VDD , is called the pull-
up device.
The Voltage Transfer Characteristics (VTC) of an inverter represent its output voltage as a function of the
input voltage. The VTC of an ideal inverter is-

In an ideal inverter, the output voltage Vout is maintained at the maximum value VDD when the input
voltage Vin varies from 0 to, VDD /2 and becomes 0 for input voltages from VDD /2 to VDD. The input
voltage, VDD /2, at which the output changes from high ‘1’ to low ‘0’, is known as inverter threshold
voltage.
In practical inverter, the VTC is not like ideal VTC due to some voltage drop across the pull-up device,
the output high voltage level is less than VDD for the low input voltage level. This voltage is represented
by VOH , which is the maximum output voltage level for output level ‘1’.
As the input voltage increases and crosses the threshold voltage of the pull-down transistor, it starts
conducting, which leads to a decrease in the output voltage level. However, instead of an abrupt change
in the voltage level from logic level ‘1’ to logic level ‘0’, the voltage decreases rather slowly.
 dVout
The unity gain point at which dVin
= −1 is defined as the input high voltage VIL , which is the maximum
input voltage which can be treated as logic level ‘0’. As the input voltage is increased further, the output
crosses a point where Vin = Vout .

The voltage at which this occurs is referred to as the inverter threshold voltage VT. The inverter threshold
voltage may not be equal to VDD /2 for practical inverters.
The output attains the output low voltage VOL, which is the minimum output voltage for output logic level
‘0’, the transfer-characteristic curve crosses another important point VIH , the minimum input voltage that
dVout
can be accepted as logic ‘1’. This point is also obtained at another unity gain point at which = −1
dVin

Q. Define noise margins. Explain how a greater noise margin helps in reducing the effect of
external noise in digital circuits.
Generally, a practical inverter experiences the unwanted signal from the input signal such unwanted
signal is known as noise. The noise in a digital circuit exceeds certain margins, known as noise margins,
hence, the desired logic levels are changed.
***In practical inverter circuits, the maximum input low level is VIL and the maximum output low level
is VOL. Therefore, if VIL > VOL, then there is a margin in the input voltage for logic ‘0’, which can be
allowed without causing any change in the output voltage. Hence, the noise margin for logic ‘0’ NML is
defined as follows:
NML = VIL − VOL [Noise margin low]
Similarly, the noise margin for logic ‘1’ NMH is defined as follows:
NMH = VOH − VIH [Noise margin high]
Real digital inverters do not instantaneously switch from a logic high (1) to a logic low (0), there is some
capacitance. While an inverter is transitioning from a logic high to low, there is an undefined region
where the voltage cannot be considered high or low. ***

Q. Derive the expression of critical voltage of resistive load inverter.

The basic structure of a MOS inverter which consists of an nMOS transistor connected between the
output node and the ground, and is controlled by the input voltage applied at its gate terminal. A load is
connected between the power supply VDD and the output terminal. The nMOS transistor acts as a switch
between the output and ground terminals.
When the input voltage is low, the nMOS transistor is OFF, and the output is connected to the power
supply through the load. When the input is high, the nMOS transistor becomes ON, and the output is
connected to ground terminal.
Let us consider the load as a resistor of value R L ; and let the resistance of the driver nMOS transistor be
R D. The output voltage is,
RD
Vout = V
R D + R L DD
The output is logic high for a logic low input, therefore, ideally, either R L is zero or R D is infinite, so that
Vout = VDD
For logic high input, the output is logic low. Therefore, either R L is infinite or R D is zero, so that Vout = 0
Calculation of critical voltage from D. Das article 3.3.1 & 3.3.2

Q. MOS inverter with enhancement-type nMOS load

The disadvantage of a resistive inverter is that it requires a large area on silicon in order to implement the
resistive load.
It is possible to design a MOS inverter with an enhancement-type nMOS transistor acting as a load, the
load nMOS transistor ML can operate both in the saturation region and in the linear region, which
showing fig (a) ML operates in the saturation region as its gate and drain are shorted together and tied to
the power supply, VDD. On the other hand, in Fig (b), ML operates in the linear region depending on the
bias voltage VDD1 .

When the input is at logic low, the driver nMOS transistor MD is OFF, and the output is at logic high
through the load transistor. On the other hand, when the input is at logic high, the driver nMOS transistor
becomes ON, and the output is connected to ground through MD.
The circuit configuration as shown in Fig. (b) is not generally preferred as it requires dual power supply
voltages. The circuit configuration as shown in Fig.(b) is not generally preferred as it requires dual power
supply voltages. Nevertheless, both the circuit configurations have a drawback as they lead to significant
static power dissipation.

Q. What is propagation delay in CMOS inverter?

There are two time delays between the input and output waveforms in a CMOS one is due to the delay
between the input and output waveforms during the high-to-low transition of the output waveform,
termed as TPHL, and the other is due to the delay between input and output waveforms during the low-to-
high transition of output waveform, termed as TPLH.

The average of TPHL and TPLH is known as the propagation delay t p of the gate-
TPLH + TPHL
tp =
2
The propagation delay of the gate is determined by the load capacitance and the dimensions of the nMOS
and pMOS transistors.

Q. Define rise time and fall time of CMOS inverter. Draw the output waveform of a CMOS inverter
showing rise time and fall time
Rise time t r is the time, during transition, when output switches from 10% to 90% of the maximum value.
Fall time t r is the time, during transition, when output switches from 90% to 10% of the maximum value.
 Q. What are interconnect delay models? Discuss each of them in brief./Discuss RC delay
model/Elmores delay
Interconnect delay is the difference between the time a signal is first applied to the net and the time it
reaches other devices connected to that net. It is due to the finite resistance, capacitance and inductance of
the net. It is also known as wire delay. In recent technology trends, the parasitic resistance and
capacitance have become dominant in comparison to the inductance effects.
Interconnect introduces capacitive, resistive and inductive parasites. All three have multiple effects on the
circuit behavior.
1.Interconnect parasites cause an increase in propagation delay (i.e. it slows down working speed)
2. Interconnect parasites increase energy dissipation and affect the power distribution.
3.Interconnect parasites introduce extra noise sources, which affect reliability of the circuit.
RC Delay Model & Elmore Delay Model from Das article 4.18.1 & 4.18.2

Q Explain why a pMOS transistor is used in the pull-up network and the nMOS transistor is
used in the pull-down network in CMOS circuits
Not Found

Q. Calculate the noise margin of a digital logic circuit

Math- Example 3.1 from D. Das
 Integrated Circuit Fabrication Technology
Q. What are the Si single crystal growth technique? Describe one of them.
To start the IC fabrication, we need the substrate or the wafer. In reality, the semiconductor material is not
available in the elemental form. The elemental semiconductor needs to be extracted from its compounds.
The crystalline form of the semiconductor needs to be grown. The techniques that grow the
semiconductor crystals are known as crystal growth techniques. The grown crystal is often called the
single crystal.
The Si single crystal growth technique given below-
i. Czochralski Technique iii. Bridgman Technique
ii. Float-zone Technique iv. Verneuil Method
v. EGS Technique

Czochralski Technique: - Czochralski technique is the method of single Si crystal growth. The process of
this technique describe below-
- The crystal growth takes place from the melt.
- The molten silicon is taken in a crucible.
- A seed crystal is placed just on top of the melt.
- The seed is pulled upwards slowly and rotated.
- The molten silicon is cooled slowly and solidifies underneath the seed in the desired crystal
direction.
- The grown crystal takes a cylindrical shape, which is known as an ingot.

EGS Technique: - EGS technique stand for Electronic Grade Silicon. It’s the technique of single Si
crystal growth. Si is available in nature abundantly in the form of sand SiO2. So, first the elemental Si is
extracted from sand using a series of chemical reactions as follows: -
- Sand is taken with coal, coke, and woodchips in a furnace and is reacted at 1400°C to form
metallurgical grade silicon (MGS). MGS is 98% pure, where impurities are in the order of parts
per million (ppm).
 coal,coke,woodchips
1400℃
SiC + SiO2 → Si + SiO + CO
- MGS is reacted with hydrogen chloride at 300°C to form trichlorosilane SiHCl3. Trichlorosilane
is used to remove the impurities.
300℃
Si + 3HCl → SiHCl3 ↑ + H2 ↑
- Then reacted with hydrogen gas at 1150°C to reduce the hydrogen atom and produce electronic
grade silicon (EGS). EGS has the highest purity and its impurity level is in the order of parts per
billion (ppb).
1150℃
SiHCl3 + H2 → Si + 3HCl

Q. Explain Photolithographic process. What are the components of photolithography?

Photolithography is the technology to create a pattern on Si wafer using an UV ray of light. The
components of the photolithography process are as follows: -
❑ Si Wafer ❑ UV light source
❑ Photoresist-a light sensitive material ❑ Developer solution—a method of developing
❑ Lens the photoresist,
❑ Mask with the desired pattern

Steps of photolithographic processes is given below-

- Cleaning the wafer surface of Si
- Depositing the SiO2 layer on the wafer
- Coating the wafer with the photoresist on the top of the layer
- Projecting the UV light on the wafer through the mask and a lens. The mask has certain regions
transparent and other regions opaque. Transparent regions of the mask allow the UV light to pass
through and fall on the photoresist. Photoresist can be positive or negative.
- Dripping the wafer on the developer solution, the photoresist and SiO2 layer are etched out.
 - Stripping the photoresist and the replica of mask is formed on the SiO2 layer.

Q. Distinguish between positive and negative photoresist

The difference between positive and negative photoresist is given below-
Positive photoresist Negative photoresist
1. A positive photoresist is a type of photoresist in 1. A negative photoresist is a type of photoresist
which the portion of the photoresist that is in which the portion of the photoresist that is
exposed to light becomes soluble to the exposed to light becomes insoluble to the
photoresist developer. photoresist developer.
2. The unexposed portion of the photoresist 2. The unexposed portion of the photoresist is
remains insoluble to the photoresist developer. dissolved by the photoresist developer.
3. It consists of a resin and a photoactive 3. It consists of a chemically inert polyisoprene
compound dissolved in an organic solvent. rubber and a photosensitive compound.
4. Higher resolution 4. Lower resolution
5. Developer solution is temperature sensitive 5. Developer solution is temperature non-sensitive
6. Adhesion to Silicon is fair 6. Adhesion to Silicon is excellent
7. Relatively more expensive 7. Relatively cheap

Q. Describe the Si oxidation mechanisms.

Oxidation refers to the conversion of the silicon wafer to silicon oxide. Silicon dioxide layers are used as
an insulating separator between different conducting layers also acts as mask or protective layer against
diffusion and high-energy ion implantation.
In the case of grown oxide layers, there are two main growth mechanisms-
1. Thermal growth
 Dry oxidation
 Wet oxidation
2. Chemical vapor deposition
In dry oxidation, Si reacts with O2 to form SiO2
Si (s) + O2 (g) → SiO2 (s)
Dry oxidation performed in O2 with a few percent of HCl added to produce thin, but robust oxide layers is
used to form the gate structure. These layers are known as gate oxide layers. The reaction takes place in
the temperature range 900°C–1200°C
In wet oxidation, Si reacts with water (steam) to form SiO2
Si (s) + 2H2 O(g) → SiO2 (s) + 2H2 (g)
The wet oxidation produces a thicker and slightly porous layer. This layer is known as field oxide layer.

To form a SiO2 layer of thickness, t ox 1 µm, it consumes Si layer of thickness 0.44 µm. Initially, as oxide
starts to grow, the grown oxide thickness t ox linearly increases with time t. After a certain thickness is
grown, the growth becomes parabolic.
Chemical vapor deposition (CVD) is another technique by which the SiO2 layer can be grown. But it does
not produce high quality oxide as in the thermal oxidation technique.
Process:
❑ Precursor gases dissociate at the wafer surface to form SiO2
❑ No Si on the wafer surface is consumed
❑ Film thickness is controlled by the deposition time
The chemical reactions are given below-
700℃
Si(C2 H5 O)4 + 2H2 O → SiO2 + 4C2 H6 O
450℃
SiH4 + O2 → SiO2 + 2H2 O
In the CVD technique, oxide thickness grows linearly with time.

Q. How diffusion can be done in IC fabrication?

Using the diffusion process, dopants are introduced into the wafer. Diffusion is a process of displacement
of particles or atoms from a high concentration region to a low concentration region. For n-type material,
arsenic (As) and phosphorus (P) are used as dopants, and for p-type material, boron (B) is used as a
dopant. The introduction of doping atoms into the semiconductor can be done by two techniques: -
(a) Diffusion (b) Ion implantation.
An ambient is created of the dopant atoms at the surface of the wafer and the temperature is raised to
800°C–1200°C.
❑ Ion implantation process:
- Ionization of the dopant source to form positive ions
- Acceleration of ions through a high voltage field to reach the required energy
- Projection of high-energy ions towards the target of wafer surface
- Collision of ions with silicon atoms resulting in energy loss finally come to rest which is known
as ion stopping.
- End of penetration of ions in the substrate
❑ Advantages of ion implantation: -
- Very precise control of impurity - Low penetration depth of the implanted
numbers is possible. ions.
- Low processing temperature. - Implantation through thin layers is
- Short processing time. possible.

Q. State the steps used for nMOS fabrication

An nMOS device requires p-type substrate. Typical processing steps of the poly-silicon gate self-aligning
nMOS technology are given below-
Step 1 By using wet oxidation technique, to grow a thick silicon dioxide SiO2 layer which thickness is
about 1 µm all over the wafer surface. This layer act as barrier to dopants and insulating layer.

Step 2 After forming SiO2 layer, some regions are defined where transistors are to be formed which is
done by the photolithographic process with the help of mask.
Step 3 SiO2 has already, formed which discussed earlier in step 1. The SiO2 layer thickness is about 1 µm
all over the wafer surface. At this step poly-silicon layer is deposited on the top of the SiO2 layer which
thickness is about 1.5 µm. This layer consists of heavily doped poly-silicon which deposited using CVD
technique.
Step 4 At this step, poly-gate structures and interconnections by poly layers are formed by using mask and
photographic process.
Step 5 At this step, the diffusion process is performed. For, obtaining the source and drain, the thin oxide
layer is removed and expose areas where n-diffusions are take place.

Step 6 At this step, a thick oxide layer is grown all over again and holes are made at selected areas of the
poly-silicon gate, drain, and source regions by using a mask and the photolithographic process.
Step 7 At this step, a metal (aluminum) layer of 1μm thickness is deposited on the entire surface by the
CVD process. The metal layer is then patterned with the help of a mask (MASK 4) and the
photolithographic process.

Step 8 At this step, the entire wafer is again covered with a thick oxide layer—this is known as over-
glassing. This oxide layer acts as a protective layer to protect different parts from the environment.

Q. State the steps used for the fabrication of an n-well CMOS process/p-well/twin tub and
SOI.
There are several approaches for CMOS fabrication, namely, p-well, n-well, twintub, triple-well, and SOI.
The n-well approach is compatible with the nMOS process. However, the most popular approach is the p-
well approach, which is similar to the n-well approach. The twin-tub and silicon on sapphire are more
complex and costly approaches.

p-well: - The p-well process is given below-

Step 1 The basic idea behind the p-well process is the formation of an p-well or tub in the n-type
substrate. The formation of an p-well by ion implantation. This step requires a mask which defines the
deep p-well diffusions.
 Start with a blank wafer, commonly known as a substrate, which is lightly doped.
 Cover the wafer with a protective layer of SiO2 using the oxidation process
 Expose photoresist through the p-well mask and strip off the exposed photoresist using
organic solvents.
 Etch oxide with HF, which only attacks oxide where the resist has been exposed.
 Remove the photoresist
  Implant or diffuse p dopants into the exposed wafer using diffusion or ion implantation.
The ion implantation process allows shallower wells suitable for the fabrication

 Strip off SiO2 leaving behind the n-substrate along with the p-well.
Step 2 The formation of thin oxide regions for the formation of p- and n–transistors requires MASK 2,
which is also known as active mask.
Step 3 The formation of patterned poly-silicon regions is done using MASK 3.
Step 4 The formation of p-diffusion is done with the help of the p+ mask, which is essentially MASK 4.
Step 5 Ion implantation to dope the source and drain regions of the pMOS (p+) and nMOS (n+)
transistors, this will also form n+ polysilicon gate and p+ polysilicon gate for nMOS and pMOS
transistors respectively.
Step 6 Thick SiO2 is grown all over and then contact cut definition using another mask.
Step 7 The whole chip then has metal deposited over its surface to a thickness of 1μm. The metal layer is
then patterned by the photolithographic process to form interconnection patterns using MASK 7.
Step 8 Lastly, over-glassing on the layer which is require to define the openings for access to bonding
pads.

Twin- Tub Process: - The twin-tub process allows two separate tubs to be implanted into very lightly
doped silicon. This allows the doping profiles in each tub region to be tailored independently so that
neither type of device will suffer from excessive doping effects. The lightly doped silicon is an epitaxially
grown layer on a heavily doped silicon substrate. The substrate can be either n-type or p-type. The
process is similar to the n-well process, involving the following steps: -
❑ Tub formation
❑Thin oxide construction
❑ Source and drain implantations
❑ Contact cut definition
❑ Metallization

Q. Explain the twin-tub process of CMOS fabrication. What are the advantages of this
technique?
SOI: - A prominent emerging CMOS process is Silicon-On-Insulator (SOI). As the name suggest it is a
process where the transistors are fabricated on an insulator. The steps used in a typical SOI CMOS
process are as follows: -
 A thin film of very lightly doped n-type Si is epitaxially grown over an insulator.
 An anisotropic etch is used to etch away the Si
 Implantation of the p-island where an n-transistor is formed.
 Implantation of the n-island where a p-transistor is formed.
 Growing of a thin gate oxide
 Depositing of phosphorus-doped poly-silicon film over the oxide. Patterning of the poly-silicon
gate.
 Forming of the n-doped source and drain of the n-channel devices in the p-islands.
 Forming of the p-doped source and drain of the p-channel devices in the n-islands.
 Depositing of a layer of insulator material such as phosphorus glass or SiO2 over the entire
structure.
 Etching of the insulator at contact cut locations. The metallization layer is formed next.
 •Depositing of the passivation layer and etching of the bonding pad location.
The advantages of SOI given below-
- Due to the absence of wells, transistor structures denser than bulk silicon are feasible.
- Lower substrate capacitance.
- No field-inversion problems
- No latch-up is possible because of the isolation of transistors by insulating substrate.

Q. What is twin tub process? Why it is so called? /

Twin tub process is one of CMOS technology. There are two wells available in this process. The other
name of well is tub. so because of these two tubs, this process is known as twin tub process. The main
advantage of this process is that the
 Threshold voltage,
 Body effect parameter
 The trans-conductance
can be optimized separately. The starting material for this process is p+ substrate with epitaxially grown
p-layer which is also called as epilayer.

Q. Explain the latch-up problem of CMOS devices and its prevention techniques
In CMOS circuits, the parasitic NPN and PNP bipolar junction transistors (BJT)form a thyristor or PNPN
structure. Latch-up can be defined as the formation of a low-impedance path between the power supply
and ground rails through the parasitic n–p–n and p–n–p bipolar transistors.
Once the device is triggered, the current through the device continues to increase due to regenerative
feedback action, then it cannot be stopped. The only way to stop it is to switch the power supply.
Due to the regenerative feedback action, there can be a very large current flowing through the device,
damaging the device components. Hence, in order to keep the current limited, the parasitic transistors gain
must be low, and the parasitic resistances must be small
The possibility of internal latch-up can be reduced to a great extent by using the following rules:
❑ Use of p+ and n+ guard rings around nMOS and pMOS connected to the ground and VDD, respectively.
❑ Every well must have an appropriate substrate contact.
❑ Every substrate contact should be directly connected to a supply pad by metal
❑ Keeping sufficient spacing between the nMOS and pMOS transistors.

Q. Discuss the reliability issues of IC. Discuss about electromigration.

The IC product lifetime is determined by several reliability mechanisms. Some of the most important
mechanisms are as follows:
1) Electromigration (EM) 4) Channel-hot-electron (CHE)
2) CMOS Latch-up 5) Negative-bias temperature instability (NBTI)
3) Time-dependent dielectric breakdown 6) Electrostatic discharge (ESD)
(TDDB)
Electromigration: - It is a phenomenon which causes migration of atoms of metal interconnects in the
VLSI chips due to electron wind. When the current density through a metal wire exceeds a threshold
level, the electrons travel at a greater velocity. This is called electron wind. The high-speed electrons
knock the metal atoms and displace them. The displacement of the metal atoms can cause void or hillock
in the metal wire, and can cause either open circuit or short-circuit failure.
❑ Electromigration occurs when the device is in operation for some time.
❑ It also depends on the operating temperature. EM can occur both for signal and power lines

Q. What is stick diagram? What are the uses? Draw the stick diagram….

Q. How to determine the parasitic resistances and capacitances for the poly wire.
 Basic Logic Gates in CMOS
Q. Design a CMOS Inverter, two input NAND gate, two input NOR gate and explain its
operation.
CMOS Inverter: - A CMOS inverter is the simplest logic circuit that uses one nMOS and one pMOS
transistor. The nMOS is used in Pull-Down-Network and the pMOS is used in the Pull-Up-Network, as
shown in Fig-

When input is low, the nMOS is OFF and the pMOS is ON. Hence, the output is connected to VDD
through pMOS. When the input is high, the nMOS is ON and the pMOS is OFF. Hence, the output is
connected to the ground through nMOS. The load capacitor is charged to VDD through pMOS when the
input is low and is discharged to the ground through nMOS when the input is high.

CMOS NAND: - Let us, consider a simple example of a two input NAND gate design. The two-input
NAND function is expressed by
Y = A.B
Step 1: Take complement of Y
Y = ̿̿̿̿̿̿
A .B = A .B
Step 2: Design the PDN, in this case, there is only one AND term. So there will be two nMOSFETs in
series,
Step 3: Design the PUN, in PUN, there will be two pMOSFETs in parallel. AND Operation
Join the PUN and PDN as shown in Fig- pMOS-Parallel
nMOS-Series

OR Operation
pMOS-Series
nMOS-Parallel

For pMOS;
G = 0; D-S; Short Ckt-ON
G = 1; D-S; Open Ckt-OFF
For nMOS;
G = 0; D-S Open Ckt-OFF
G = 1; D-S Short Ckt-ON

When A = 0 and B = 0, both the nMOS transistors are OFF and both pMOS transistors are ON. Hence,
the output is connected to VDD and we get logic high at the output.
When A = 1 and B = 0, the upper nMOS is ON and lower nMOS is OFF. So, output cannot be connected
to the ground. Under this condition, left pMOS is OFF but right pMOS is ON. Hence, the output is
connected to VDD, and we get logic high at the output.
When A = 0 and B = 1, the upper nMOS is OFF and lower nMOS is ON. So, output cannot be connected
to ground. Under this condition, left pMOS is ON but right pMOS is OFF. Hence, the output is connected
to VDD, and we get logic high at the output.
When A = 1 and B = 1, both nMOS transistors are ON and both pMOS transistors are OFF. Hence, the
output is connected to the ground, and we get logic low at the output. This is illustrated in Fig. This
proves by the truth table of NAND gate shown in table.

CMOS NOR: - Let us, consider a simple example of a two input NOR gate design. The two-input NOR
function is expressed by
Y=A+B
Step 1: Take complement of Y
Y = ̿̿̿̿̿̿̿
A+B =A+B
Step 2: Design the PDN, Here, there is only one OR term. Hence, there will be two nMOSFETs
connected in parallel, as shown in Fig.
Step 3: Design the PUN, in the PUN, two pMOSFETs will be connected in series, as shown in Fig

When A = 0 and B = 0, both nMOS transistors are OFF and both pMOS transistors are ON. Hence, the
output is connected to VDD and we get logic high at the output.
When A = 1 and B = 0, the upper pMOS is OFF and lower pMOS is ON. So, output cannot be connected
to the VDD. Under this condition, left nMOS is ON and right nMOS is OFF. Hence, the output is
connected to the ground and we get logic low at the output.
When A = 0 and B = 1, the upper pMOS is ON and lower pMOS is OFF. So, output cannot be connected
to VDD. Under this condition, left nMOS is OFF and right nMOS is ON. Hence, the output is connected
to the ground and we get logic low at the output.
When A = 1 and B = 1, both nMOS transistors are ON and both pMOS transistors are OFF. Hence, the
output is connected to VDD and we get logic low at the output. This proves the truth table of NOR gate as
shown in Fig.

Q. What is static CMOS? What is its disadvantages? What are the alternate logic families in
order to reduce the number of transistor?
Static CMOS is a logic circuit design technique whereby the output is always strongly driven due to it
always being connected to either VCC or GND. This design is in contrast to
A static CMOS gate is a combination of two networks, called the pull-up network (PUN) and the pull-
down network (PDN). A pull-up network consists of pMOS and pull-down network consist of nMOS.
Advantages of Static CMOS Logic-
 - Ease of fabrication - Lesser switching activity
- Availability of matured logic synthesis - No need for swing restoration
tools and techniques - Good I/O decoupling
- Good noise margin
Disadvantages of Static CMOS Logic-
- Larger number of transistors - Spurious transitions due to finite
- Short-circuit power dissipation propagation delays from one logic block
- Weak output driving capability to the next
To reduce the number of transistors needed to implement a logic function
❑ Pseudo NMOS ❑ Differential Cascade Voltage Switch Logic
❑ Dynamic Logic ❑ Clocked Logic
❑ Domino Logic ❑ Pass Transistor Logic

Q. What is pseudo-nMOS? Explain its operation.

In the pseudo-nMOS logic, the PDN is realized by a single pMOS transistor. The gate terminal of the
pMOS transistor is connected to the ground. It remains permanently in the ON state. Depending on the
input combinations, output goes low through the PDN. Pseudo-nMOS logic suffers from large static
power dissipation problem.
Operation of an inverter realized using pseudo-nMOS logic is shown in Fig-

When, input A = 0, drain and source become open circuit of nMOS and PDN is in OFF state. The VDD is
connected with the drain of pMOS transistor, the gate is always connected with ground hence, pMOS is
permanently in ON state Therefore, the output Y is connected to VDD and we get logic high at the output.
When, input A = 1, drain and source of nMOS become short circuit and PDN is in ON state. The VDD is
connected with the drain of pMOS transistor, the gate is always connected with ground hence, pMOS is
permanently in ON state. Hence, we get logic low at the output.
Ex: Design an XNOR gate using pseudo-nMOS logic
 Q. Explain dynamic CMOS and write down its advantage-disadvantages.
Dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high-
impedance circuit nodes. Reducing transistor count is to use dynamic CMOS logic. In order to reduce the
number of transistors, pseudo-nMOS logic is used where pull-up network is replaced by a pMOS
transistor with gate terminal connected to the ground. An alternate method of reducing transistor count is
to use dynamic CMOS logic. It is very similar to the pseudo-nMOS logic except one additional nMOS
transistor MN connected between the pull-down network and the ground. The pMOS transistor in the
PUN and the extra nMOS transistors in the PDN are operated by a clock signal φ shown in fig-

The dynamic CMOS logic circuit has a serious problem when they are cascaded. In the pre-charge phase
(φ = 0), output of all the stages are pre-charged to logic high. In the evaluation phase (φ = 1), the outputs
of all the stages are evaluated simultaneously.
Advantages of the Dynamic Logic Circuits
❑ Low power dissipation ❑ No spurious transitions and glitching power
❑ Small area due to less number of transistors dissipation, since any node can undergo at the
❑ Large noise margin most one power-consuming transition per clock
cycle.
Disadvantages of dynamic CMOS
Higher switching activity Suffers from charge leakage problem requiring
Not as robust as static CMOS pre-charging at regular interval
Clock skew problem in cascaded realization Difficult to implement power-down circuits
Suffers from charge sharing problem Matured synthesis tools not available

Q. Discuss the phase of operation of dynamic CMOS

It is very similar to the pseudo-nMOS logic except one additional nMOS transistor MN connected
between the pull-down network and the ground. The pMOS transistor in the PUN and the extra nMOS
transistors in the PDN are operated by a clock signal φ.
There are two phase in a dynamic CMOS-
- Pre-charge phase
- Evaluation phase
When the clock is low the pMOS (MP) is ON and the nMOS (MN) is OFF. So the capacitor at the outputs
gets charged to VDD thus changing to logic 1. This operation is known as pre-charge phase.
When the clock is high, MP is OFF The output capacitor get discharged conditionally based on the logic
function implemented by PDN thus changing to logic 0. This operation is known as evaluation phase.
 Q. Explain the operation of Domino logic.
Domino CMOS logic is a slightly modified version of the dynamic CMOS logic circuit. In this case, a
static inverter is connected at the output of each dynamic CMOS logic blocks. The addition of the inverter
solves the problem of cascading of dynamic CMOS logic circuits.

In the pre-charge phase (φ = 0), the outputs of the dynamic CMOS logic circuits are pre-charged to logic
high and the output of the static inverter is logic low.
In the evaluation phase (φ = 1), outputs of the dynamic CMOS logic circuits can either go to logic low or
remain at logic high. The output of the static inverter can make only a 0→1 transition in the evaluation
phase. So, irrespective of the input logic, the output of the static inverter cannot make a 1→0 transition in
the evaluation phase.

Q. Classify programmable logic devices(PLD) based on the architecture and programmability.

Programmable Logic Devices (PLD) s are the integrated circuits. They contain an array of AND gates &
another array of OR gates. There are three kinds of PLDs based on the type of arrays, which has
programmable feature. Programmable logic devices (PLD) are standard products, but can be programmed
to function in a specific application. The programming can be done either by the end user or by the
manufacturer.
The PLDs are classified into three categories based on the architecture and programmability as given
below:
❑ Programmable Read only memory (ROM)
❑ Programmable logic array (PLA)
❑ Programmable array logic (PAL)

Q. Explain the PLA architecture with necessary circuit diagrams and operating principle
The AND array, also called the AND plane, implements the product terms, and the OR array, also called
the OR plane, implements the sum of product (SOP) terms. In PLA, both the arrays are programmable.
PLA has a limited number of product terms, not the minterms.

Hence, to implement a logic using PLA, a minimal SOP form should be derived, so that the logic can be
implemented using the available product terms.

Q. Explain the PAL architecture with necessary circuit diagrams and operating principle
The programmable array logic (PAL) is another class of programmable logic device with the AND array
followed by the OR array, where the AND array is programmable but the OR array is fixed.

The OR plane cannot be programmed. In this PAL architecture, each OR gate has two inputs; hence, the
SOP must have two product terms. Each function must be simplified individually to reduce the product
terms to maximum two. If the SOP expression contains more than two product terms, each OR gate can
be used to implement the function partially, and then summed using the additional OR gate to implement
the complete function.

Q. What are the components of an FPGA? Discuss each of them in detail

Field programmable gate array (FPGA) is an IC which can be hardware-programmed to implement
various logic functions. The end users of FPGA can program it to configure for any functionality—so it is
called field programmable. FPGA is completely fabricated and standard parts are tested and available
readily for use. There are a number of different FPGA architecture. Basically, it contains three major
components-
1) Configurable logic block (CLB)
2) Switch matrix
3) The IOB.
The configurable logic blocks (CLBs) contain several modules such as lookup tables (LUT), multiplexers,
gates, and flip-flops. LUT is a hardware that stores the truth table of a function in an SRAM to function as
a combinational circuit.

Q. How FPGA is different from CPU?

The difference between FPGA and CPU given below-

Q. Explain programming technology of FPGA

There are three types:
a) Anti-fuse-based: The anti-fuse FPGAs are programmed by applying high voltage between the two
terminals of the fuse to break down the dielectric material of the fuse.
b) EPROM-based: The FPGAs use EPROM and EEPROM technology which are programmed using high
voltages.
c) SRAM-based: In the SRAM-based FPGA, the logic functions are based on the stored bits in the SRAM

The answers of the remaining questions will read from the slide
of this chapter.