UNIVERSITI KUALA LUMPUR

ASSESSMENT BRIEF

COURSE DETAILS
INSTITUTE UniKL BRITISH MALAYSIAN INSTITUTE
COURSE NAME INTRODUCTION TO DIGITAL ELECTRONICS
COURSE CODE BEB17203
COURSE LEADER NAS
LECTURER NAS, NHR
SEMESTER & YEAR OCTOBER 2024

ASSESSMENT DETAILS
TITLE/NAME LABORATORY 1
WEIGHTING 20%
DATE/DEADLINE 12/12/2024, 5.00 PM
COURSE LEARNING CLO 3: Construct combinational and sequential logic circuit using modern
OUTCOME(S) engineering techniques and tools. (P7, PLO5)

INSTRUCTIONS Perform the following tasks:

1. Complete this assessment individually or in a group of two (2) as
instructed by the lecturer.
2. Answer all questions in English language only within the allocated
duration.

Student Name: ID: Group:

LUQMAN HAKIM BIN ANUAR 51220123060 L01-B01

Assessor’s Comment: Marks:

Verified by: Course Leader [NAS] QSC format PC/HOS content

Prepared by: [NAS] verification validation

I hereby declare that all my team members have agreed

with this assessment. All team members are certain that
this assessment complies with the Course Syllabus.

25/11/2024

Signature: ____________________________
Date : ____________________________28 / 10 /
2024

TASK NO CLO MARKING SCHEME MARKS

1 3 Produce and simulate Combinational Logic 100
circuits

2 3 Produce and simulate an asynchronous counter 40

3 3 Produce and simulate a synchronous counter 70

TOTAL 210
 INFORMATION ON SK_SP-TA FOR COURSE

Course Code & Name : BEB17203 & INTRODUCTION TO DIGITAL ELECTRONICS

PLOs : 5

Please tick (  ) in the box provided.

Knowledge Profiles (SK) A programme that builds this type of knowledge and develops the attributes listed below is typically
achieved in 4 years of study
SK1 A systematic, theory-based understanding of the natural sciences applicable to the sub-discipline
Conceptually-based mathematics, numerical analysis, statistics and aspects of computer and information
SK2
science to support analysis and use of models applicable to the sub-discipline
A systematic , theory-based formulation of engineering fundamentals required in an accepted subdiscipline
SK3

Engineering specialist knowledge that provides theoretical frameworks and bodies of

SK4
knowledge for an accepted sub-discipline
SK5 Knowledge that supports engineering design using the technologies of a practice area
SK6 Knowledge of engineering technologies applicable in the sub-discipline 
Comprehension of the role of technology in society and identified issues in applying
SK7 engineering technology: ethics and impacts: economic, social, environmental and
sustainability
SK8 Engagement with the technological literature of the discipline

Definition of Broadly-Defined Problem Solving (SP)

Broadly-defined Engineering Problems have characteristic SP1 and some or all of
No. Attribute
SP2 to SP7:
Cannot be resolved without engineering knowledge at the level of one or
SP1 Depth of Knowledge Required more of SK 4, SK5, and SK6 supported by SK3 with a strong emphasis on 
the application of developed technology
Range of conflicting
SP2 Involve a variety of factors which may impose conflicting constraints.
requirements
SP3 Depth of analysis required Can be solved by application of well-proven analysis techniques
Belong to families of familiar problems which are solved in well-accepted
SP4 Familiarity of issues
ways
May be partially outside those encompassed by standards or codes of
SP5 Extent of applicable codes 
practice
Extent of stakeholder
Involve several groups of stakeholders with differing and occasionally
SP6 involvement and level of
conflicting needs
conflicting requirements
SP7 Interdependence Are parts of, or systems within complex engineering problems 

Range of Engineering Activities (TA)

No. Attribute Broadly-defined activities
Involve a variety of resources (and for this purposes resources includes people,
TA1 Range of resources
money, equipment, materials, information and technologies)
Require resolution of occasional interactions between technical, engineering and
TA2 Level of interactions
other issues, of which few are conflicting
TA3 Innovation Involve the use of new materials, techniques or processes in non-standard ways

Consequences to
Have reasonably predictable consequences that are most important locally, but
TA4 society and the
may extend more widely
environment
TA5 Familiarity Require a knowledge of normal operating procedures and processes
A. Introduction
Binary input signal based on binary or decimal number representation is applied to any
standard logic gates to produce binary outputs. These combinations of binary inputs
can produce Boolean expression and thus, truth table can be obtained. A Boolean
expression can be simplified using Karnaugh Map or Boolean Algebra. The simplified
Boolean expression could reduce the number gates utilization and could also enable
the implementation of universal logic gates where the knowledge of De Morgan’s
Theorem is applied.

To explore this knowledge, students will be exposed with the standard logic gates such
as AND, OR and NOT gates as well as the universal logic gates like NAND and NOR
gates. All gates will be explored in terms of individual component in theory and as an
integrated circuit (IC) in practical. Besides that, the comparative observation (i.e.
similarities and/or dissimilarities) between the standard logic gates and universal logic
gates are required in this assessment. In this assessment, datasheet for individual IC
is needed as main references and it is required for the students to perform all the
simulated circuit investigations using modern tools.

For task 2 and task 3, circuits for counting events are frequently used in computers and
other digital systems. Since counter circuit must remember its past states, it has to
possess memory. Such kind of circuits are known as sequential logic circuits. In this
lab, several types of sequential logic circuits are simulated using modern tools and
implemented. These include basic flip flop to store one bit, synchronous and
asynchronous counters.

Moreover, Counters can be classified into two broad categories according to the way
they are clocked. The first category is asynchronous (ripple) counters in which the first
flip-flop is clocked by the external clock pulse, and then each successive flip-flop is
clocked by the Q or Q' output of the previous flip-flop. The second category is
synchronous counters where all the memory elements are simultaneously triggered by
the same clock.

This lab will focus on Multisim simulation as modern tools to constructe synchronous
and asynchronous counters. Students will be exposed on how to connect the flip-flops
as counters. The number of flip-flops used and how they are connected will determine
the number of states and sequence of states the counter will pass through in each
complete cycle.

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B. Objectives
• To select any specific implementation of Karnaugh Map, Boolean Algebra
and/or DeMorgan’s Theorems to obtain a simplified Boolean expression.
• To simulate using modern tools and investigate a complete combinational logic
circuit using standard logic gates.
• To simulate using modern tools and investigate a complete combinational logic
circuit using universal logic gates
• To understand the basic concept of sequential logic circuits such as flip flops,
counters etc.
• To differentiate between asynchronous and synchronous counters.
• To design and simulate an asynchronous counter.
• To design and simulate a synchronous counter.

C. Equipment / Software
• Multisim Software

INSTRUCTIONS

1. Ensure to attach your simulation as evidence

2. Ensure to have your name on top of the software simulator as evidence. NO MARKS
for evidence without name.
3. Your experimental result must be verified by the assessor.

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Task 1
In a family business of four members, the decision-making power is distributed as in Table 1.

Table 1: Decision power

Member % Vote

Mr Alif 25%
Miss Batrisya 25%
Mrs Cempaka 25%
Mr Daniel 25%

Each member has a percentage vote equal to his or her power. A total vote of equal and more
than 50% is required to carry out the task. An electronics voting system (logic circuit) in which
an LED is to light (1) is needed to be implemented.
Based on the scenario given,

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(a) Obtained the truthtable, boolean expression and draw the circuit for the system.
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

Y=(A⋅B)+(A⋅C)+(A⋅D)+(B⋅C)+(B⋅D)+(C⋅D)

Figure 1:Circuit Diagram

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(b) Simulate the system in Task 1 (a) using Multisim. Attach the simulation results to show
the overall circuit operation.

Figure 2 Above: 0001

Figure 3 Above: 0010

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Figure 4 Above: 0011

Figure 5 Above: 1011

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(c) Simplified the expression obtained in Task 1 (a)

Y=(A⋅B)+(A⋅C)+(A⋅D)+(B⋅C)+(B⋅D)+(C⋅D)
Y=A⋅(B+C+D)+(B⋅C)+(B⋅D)+(C⋅D)
Y=A⋅(B+C+D)+(B⋅C)+(B⋅D)+(C⋅D)

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(d) Simulate the circuit design obtained in Task 1 (c ) using basic logic gates. Attach the
simulation results to show the overall circuit operation.

Figure 6 Above: 0010

Figure 7 Above:0100

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Figure 8 Above:0101

Figure 9 Above:1111

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(e) Redesign and simulate the simplified circuit in Task 1 (c) using universal gates only.

Figure 10 Above: 1000

Figure 11Above:1001

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Figure 12 Above: 1011

Figure 13 Above:1111

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 ASSESSMENT COVERSHEET

Attach this coversheet as the cover of your submission. All sections must be completed.

Section A: Submission Details

Student Name :

Student ID :

Programme :
Course Code & Name : BEB17203 & INTRODUCTION TO DIGITAL ELECTRONICS

Course Lecturer(s) Submission Title :

Deadline : LAB 1

Day Month Year Time

Penalties • 5% will be deducted per day to a maximum of four (4) working days, after which
the submission will not be accepted.

• Plagiarised work is an Academic Offence as stated in University Rules &

Regulations and will be penalised accordingly.

Section B: Declaration of Academic Integrity

Tick (✓) each box below if you agree:

I have read and understood the UniKL’s policy on Plagiarism in University Rules & Regulations.
This submission is my own, unless indicated with proper referencing.
This submission has not been previously submitted or published.
This submission follows the requirements stated in the course.

Section C: Details of the Submitter

Check that all the details above are filled in, then sign below with the date of submission:

Signature:

Date:

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