MODULE-5

Verilog Behavioral description: Structure, Variable Assignment

Statement,Sequential Statements, Loop Statements, Verilog
Behavioral Description of Multiplexers (2:1, 4:1, 8:1). (Section 3.1 to
3.4 (only Verilog) of Text 3)
• Verilog Structural description: Highlights of Structural description,
Organization of structural description, Structural description of ripple
carry adder. (Section 4.1 to 4.2 of Text 3)
 Behavioral Description

Behavioral Description highlights :

• Describes the system by showing how outputs
behave in response to changes in inputs.
• In this style of description (modeling), it is not
necessary to know the logic diagram of the system,
but we must know the behavior of the outputs in
response to the changes in the inputs
• Major behavioral description statements are always
and initial

12/11/2024 Dr. Prakash K M. Dept. of E&CE, BIET 2

1. Initial statement:
• An initial statement executes only once. It begins its execution at
the start of the simulation which is at time 0. The syntax for the
initial statement is,
initial
[timing control]
Procedural_statements
• Timing_control can be a delay or an event control.
• Where procedural_statement can be one of the following:
1. Continuous_assignment
2. Conditional_statement
3. Case_statement
4. Loop_statement
5. Wait_statement
6. Sequential_block

• execution of an initial statement will result in execution of the

procedural_statement once.
12/11/2024 Dr. Prakash K M. Dept. of E&CE, BIET 3
Example of an initial statement

reg yurt;
……….
initial
yurt=2;

• In the above example the initial statement contains a procedural

assignment with no timing control(delay). The initial statement executes
at time 0 and yurt is assigned value 2 at time 0 only.
Consider
reg curt;
………..
Initial
#5 curt=2;
• Register curt is assigned value 2 at time 5. The initial statement starts
execution at time 0 but completes execution at time 5.
12/11/2024 Dr. Prakash K M. Dept. of E&CE, BIET 4
2. always statement:
• Just like the initial statement, an always statement also begins execution at time 0.
But In contrast to the initial statement, an always statement executes repeatedly.
• The syntax of an always statement is:
always
[timing_control]
Procedural_statement.
Example:
always
clk=~clk; //will loop indefinitely.
• In the above example the always statement has one procedural_statement. Since
always statement executes repeatedly and there is no timing control the statement
clk=~clk will loop indefinitely. Therefore an always statement must have a timing
control (delay or an event).
Consider
always
#5 clk=~clk;
• This always statement upon execution, produces a waveform with a period of 10
time units.
12/11/2024 Dr. Prakash K M. Dept. of E&CE, BIET 5
Structure of Verilog Behavioral Description :
module halfadd(a, b, sum, carry);
input a, b;
output sum, carry;
reg sum, carry; /*since sum and carry are outputs and they are written inside
“always”, they should be declared as “reg” or else it will result in
syntax error/*
always @(a, b)
begin
#10 sum = a^b; //statement1-procedural as it is inside always.
#10 carry = a&b; //statement2- procedural as it is inside always.
end
endmodule
In the above example
• The name of the module is halfadd. It has two inputs a and b, two outputs sum
and carry.
• Any signal declared as output should be declared as a register (reg).Therefore sum
and carry are declared as registers.

12/11/2024 Dr. Prakash K M. Dept. of E&CE, BIET 6

Sequential statements :
There are several statements associated with the behavioral descriptions which
appear inside initial or always in Verilog.
IF statement:
• “IF” is a sequential statement that appears inside always or initial in Verilog.
• An “IF” statement selects a sequence of statements for execution, depending upon
the value of a condition.
• The condition can be an expression that evaluates to a Boolean value.
• General form of an IF statement is:
If (boolen expression)
begin
statement1;
statement2;
The execution of “if” is controlled by the Boolean
…. expression. If the expression is true, then
end statements 1, 2,..are executed. If the expression
else is false, statements a,b,. are executed.
begin
statement a;
statement b; ….
end

12/11/2024 Dr. Prakash K M. Dept. of E&CE, BIET 7

Execution of IF as ELSE-IF :
if (Boolean expression1)
begin
statement 1;
statement 2;
end
Example program:
else if (Boolean expression2)
begin if(signal 1==1)
statement i; temp=s1;
statement ii; else if(signal 2==1)
temp=s2;
end else
else temp=s3;
begin
statement a;
statement b;
end

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Examples1: Behavioral description of the 2X1 Multiplexers with tristate output.

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 Verilog Program using IF-ELSE and ELSE-IF

Verilog 2x1 Multiplexer Using IF-ELSE Verilog 2x1 Multiplexer Using ELSE-IF
module mux2x1 (A, B, SEL, Gbar, Y); module MUXBH (A, B, SEL, Gbar, Y);
input A, B, SEL, Gbar; inputA, B, SEL, Gbar;
output Y; output Y;
reg Y; regY;
always @ (SEL, A, B, Gbar) always @ (SEL, A, B, Gbar)
begin begin
if (Gbar == 1) if (Gbar == 0 & SEL == 1)
Y =1'bz; begin
else Y = B;
begin end
if (SEL) else if (Gbar == 0 & SEL == 0))
Y = B; Y =A;
else else
Y = A; Y = 1'bz;
end end
end endmodule
endmodule

12/11/2024 Dr. Prakash K M. Dept. of E&CE, BIET 10

Examples 2: Behavioral description of the D-Latch.

module D_latch (d, E, Q, Qb);

input d, E;
output Q, Qb;
reg Q, Qb;
always @ (d, E)
begin
if (E == 1)
begin
Q = d;
Qb = ~Q;
end
end
endmodule

12/11/2024 Dr. Prakash K M. Dept. of E&CE, BIET 11

Case Statement:
Syntax:
case (control-expression)
test value1: begin statements1; end
test value2: begin statements2; end
default : begin default statements end
endcase
The case statement also has a total of three
variations: case, casex and casez:
1. case: considers x and z as it is. If an exact match is not found,
the default statement will be executed.
2. casex: considers all x and z values as don’t care 0,1,x.
3. casez: considers all z values as don’t cares i.e. 0,1,x.

12/11/2024 Dr. Prakash K M. Dept. of E&CE, BIET 12

Example
case(sel) casez(sel) casex(sel)
00: y=a; 00: y=a; 00: y=a;
01: y=b; 01: y=b; 01: y=b;
X0: y=c; X0: y=c; X0: y=c;
1x: y=d; 1x: y=d; 1x: y=d;
Z0: y=e; Z0: y=e; Z0: y=e;
1?: y=f; 1?: y=f; 1?: y=f;
default: y=g; default: y=g; default: y=g;
endcase endcase endcase
Case item Ouput
sel executed sel Case item Ouput sel Case item Ouput
y executed executed
y y
00 00 a 00 00 a 00 00 a
11 default g 11 1? f 11 1x d
xx default g xx default g xx 00 a
x0 x0 c x0 x0 c x0 00 a
1z 1? f 1z 1x d 1z 1x d
z1 default g z1 01 b z1 01 b
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Examples 3: Behavioral description of a Positive edge triggered JK Flip-Flop
using the CASE statements.
module JK_FF (JK, clk, q, qb);
input [1:0] JK;
input clk;
output g, gb;
reg q, qb
always @(posedge clk, JK)
begin
case (JK)
2’d0 :q =q;
2’d1 :q = 0;
2’d2 :q =1;
2‘d3: q= ~q;
endcase

12/11/2024 Dr. Prakash K M. Dept. of E&CE, BIET 14

Examples 4: Behavioral description of a 3-bit Binary counter with Active High
Synchronous Clear
module CT_CASE (clk, clr, q);
input clk, clr
output [2:0] q;
reg [2:0] q;
initial
q= 3'b101;
3’b000;
always @ (posedge clk) clk, clr)
begin
if (clr == 0)
begin
case (q)
3’d0 : q = 3' d1;
3’d1 : q = 3'd2;
3’d2 : q = 3'd3;
3’d3 : q = 3'd4;
3’d4 : q = 3'd5;
3’d5 : q = 3'd6;
3’d6 : q =3'd7;
3’d7 : q = 3’d0;
endcase
end
else
q= 3'b000;
end
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endmodule
Loop statement:
• Loop is used to repeat the execution of the statements inside its body; this
repetition is controlled by the range of an index parameter.
• The loop reduces the size of the code.
• Loop is a sequential statement that has to appear inside always or initial in verilog.
• There are several formats of loop statement namely for, while, verilog repeat and
forever.
i) For -loop
for(initial_assignment; condition; step_assignment)
begin
Statements…………;
end • i increments at the end of each iteration.
Example: for (i=0; i<=2; i= i+1) • As long as condition is true, all statements
begin inside loop are executed.
if (temp [i] == 1)
begin
result=result+2;
end
end
12/11/2024 Dr. Prakash K M. Dept. of E&CE, BIET 16
ii) while loop
while(condition)
begin
Statement 1;
Statement 2;
end
• As long as the condition is true, all the statements within the body of the loop are
executed.
iii) Verilog repeat:
• The repeat construct executes the set of statements between it’s begin and end a
fixed number of times.
• A repeat construct must contain a number which can be a constant, variable or a
signal. It cannot contain an expression or condition.
Example:
repeat (32)
begin
#100 i=i+1; time units.
end
• the statement is executed 32 times. Each time “i” is incremented and assigned to itself after
a delay of 100
12/11/2024 Dr. Prakash K M. Dept. of E&CE, BIET 17
iv) Verilog forever:
• The statement “forever” in Verilog repeats the loop endlessly. The loop
does not contain any expression and executes until it encounters “$finish”
task. A forever can be exited or stopped by using “disable” statement.
• forever loop is equivalent to “while” loop with an expression that always
evaluates to true.
• One common use of “forever” is to generate clocks in code-oriented test
benches.
Example:
Initial
begin
clk=1’b0;
forever #20 clk=~clk;
end

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 Structural description

Highlights of Structural description:

• Simulates the system by describing its logical components (AND gate, OR
gate, NOT gate).
• Best style of description if digital logic of system’s hardware components is
known.
• All statements in structural description are concurrent. At any simulation
time, all statements that have an event executed concurrently.
• Recognizes all the primitive gates, such as AND, OR, XOR, NOT, and XNOR
gates. Need not include packages.

12/11/2024 Dr. Prakash K M. Dept. of E&CE, BIET 19

Example of Verilog half adder Structural Description

module half_adder (a, b, sum, carry);

a
sum input a,b;
b
output sum, carry;
carry xor (sum, a, b);
and (carry, a, b);
endmodule
• xor (sum, a, b); Describes a two-input XOR gate with a and b
as inputs and sum as output.

12/11/2024 Dr. Prakash K M. Dept. of E&CE, BIET 20

Example : Structural description of a 3 bit ripple-carry adder
module fulladder (x, y, cin, sum, carry);
input x, y, cin;
output sum, carry;
wire w1, w2, w3;
xor x1 (w1, x, y);
xor x2 (sum, w1, cin);
Full Adder circuit and A1 (w2, x, y);
and A2 (w3, w1, cin);
or O1(carry, w3, w2);
endmodule

module ripple_adder(x, y, s, cout);

input [2:0] x, y;
output [2:0] s;
output cout;
wire w1, w2;
fulladder FA0 (x[0], y[0], 1’b0, s[0], w1);
3 bit ripple carry adder fulladder FA1 (x[1], y[1], w1, s[1], w2);
fulladder FA2 (x[2], y[2], w2, s[2], cout);
endmodule
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 Example : Structural description of a 4 bit ripple-carry adder

12/11/2024 Dr. Prakash K M. Dept. of E&CE, BIET 22