CS3351 DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION

UNIT I COMBINATIONAL LOGIC

Combinational Circuits – Karnaugh Map - Analysis and Design Procedures – Binary

Adder – Subtractor – Decimal Adder - Magnitude Comparator – Decoder – Encoder –
Multiplexers - Demultiplexers

UNIT II SYNCHRONOUS SEQUENTIAL LOGIC

Introduction to Sequential Circuits – Flip-Flops – operation and excitation tables,

Triggering of FF, Analysis and design of clocked sequential circuits – Design –
Moore/Mealy models, state minimization, state assignment, circuit implementation -
Registers – Counters.

UNIT III COMPUTER FUNDAMENTALS

Functional Units of a Digital Computer: Von Neumann Architecture – Operation and

Operands of Computer Hardware Instruction – Instruction Set Architecture (ISA):
Memory Location, Address and Operation – Instruction and Instruction Sequencing –
Addressing Modes, Encoding of Machine Instruction – Interaction between Assembly and
High Level Language.

UNIT IV PROCESSOR

Instruction Execution – Building a Data Path – Designing a Control Unit – Hardwired

Control, Micro programmed Control – Pipelining – Data Hazard – Control Hazards.

UNIT V MEMORY AND I/O

Memory Concepts and Hierarchy – Memory Management – Cache Memories: Mapping

and Replacement Techniques – Virtual Memory – DMA – I/O – Accessing I/O: Parallel
and Serial Interface – Interrupt I/O – Interconnection Standards: USB, SATA
TEXT BOOKS: 1. M. Morris Mano, Michael D. Ciletti, “Digital Design: With an
Introduction to the Verilog HDL, VHDL, and System Verilog”, Sixth Edition,
Pearson Education, 2018.

2. David A. Patterson, John L. Hennessy, “Computer Organization and Design, The

Hardware/Software Interface”, Sixth Edition, Morgan Kaufmann/Elsevier, 2020.
CS3351 DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION

UNIT I COMBINATIONAL LOGIC

Combinational Circuits – Karnaugh Map - Analysis and Design Procedures – Binary Adder
– Subtractor – Decimal Adder - Magnitude Comparator – Decoder – Encoder –
Multiplexers - Demultiplexers

COMBINATIONAL CIRCUITS:
A combinational circuit consists of input variables, logic gates, and output variables. A
Combinational circuit accepts n-input binary variables and generates m-output variables
depending the logic combination of the gates.

Block diagram of a combinational circuit

• The n input binary variables come from an external source; the m output variables
go to an external destination
• For n input variables, there are 2" possible combinations of binary input values. For
each possible input combination, there is one and only one possible output
combination.
• A combinational circuit can be described by m Boolean functions, one for each
output variable. Each output function is expressed in terms of the n input variables.
• Each input variable to a combinational circuit may have one or two wires. When only
one wire is available, it may represent the variable either in the normal form
(unprimed) or in the complement form (primed).

Charateristics of combinational circuits

A combinational circuit performs a specific information-processing operation fully
specified logically by a set of Boolean functions.
• The output at any instance of time depends only on the signal levels present at input
terminals.
• Do not use any memory, previous states don’t have any effect or present state of the
circuit.
ANALYSIS AND DESIGN PROCEDURES OF COMBINATIONAL CIRCUITS
Analysis
The analysis of a combinational circuit requires determination of the function that the
circuit implements.
Steps:
• Starts with a logic diagram
• Verify the logic diagram is combinational with no any feedback path, no memory
elements and not sequential
• Obtain the set of Boolean functions Steps:
1. Label all gate outputs that are functions of input variables
2. Find the Boolean functions for each gate output
3. Repeat the step 2 until the outputs of the circuits are obtained
4. Obtain the output Boolean function in terms of the input variables by
simplification
• A Truth table: If the Boolean function is known, the truth table is derived directly
• Explanation of the circuit operation

Design Procedures
The design of combinational circuits starts from the verbal outline of the problem and
ends in a logic circuit diagram or a set of Boolean functions from which the logic diagram
can be easily obtained.
steps:
1. Start the problem
2. Determine the number of available input variables and required output
variables
3. Assign letter symbols to the input and output variables
4. Derive the Truth table that defines the required relationships between inputs
and outputs
5. Obtain the simplified Boolean function for each output as a function of input
variables
6.Draw the logic diagram from the simplified expression
KARNAUGH MAP(K MAP)
A K-map method is the diagrammatic representation, made of square it is used to reduce
the complexiety of Boolean expression and manipulations. These can be considered as a
special or extended version of the ‘Truth table’
• It can be explained as “An array containing 2K cells in grid like format, where k is the
number of variables in the Boolean expression that is to be reduced or optimized”.
Each cell represent a single row of the truth table a cell is represented by a square.
• By using the K map, the Boolean expression containing 2,3,4,5 and any number of
variables can be simplified

Rules for grouping of variables in K Map

• The square containing ‘1’ should be taken in simplifying at least once and it can be
considered as many times as the grouping is possible with it
• The square containing 0 should not be taken for grouping
• The group should be as large as possible
• Groups should be done in horizontal or vertical but not in diagonal manner
Steps to solve expression using K map
1. Select K map according to the number of variables
2. Identify minterms as given in the problem
3. Put ‘1’ in the square respective to the minterm
4. Make rectangular groups of total squares in power of 2 like 2,4,8… except 1 and try
to cover as many square as possible
5. From the groups made find the product terms and sum them up to the simplified
Function F.

2-variable K map

3-variable K map
4-variable K map

Problems:
1. Simplify the Boolean function

2 Simplify the Boolean function

3 Simplfy the Boolean function

BINARY ADDER
• The basic functions that digital computers perform are the arithmetic operations.
The most basic arithmetic operation is the addition of two binary digits.
• This simple addition consists of four possible elementary operations, namely,
• 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, and 1 + I = 10.
• The first three operations produce a sum whose length is one digit, but when both
augend and addend bits are equal to 1, the binary sum consists of two digits.
 • The higher significant bit of this result is called a carry. When the augend and
addend numbers contain more significant digits, the carry obtained from the
addition of two bits is added to the next higher-order pair of significant bits.
• A binary adder is a digital circuit that produces the sum of two binary numbers
Half Adder
A combinational circuit that performs the addition of two bits is called a half-adder. One
that performs the addition of three bits (two significant bits and a previous carry) is a full-
adder.
• This circuit needs two binary inputs and two binary outputs.
The input variables designate the augend(x) and addend(y) bits;
the output variables produce the sum and carry.
• It is necessary to specify two output variables because the result
may consist of two binary digits.
• Designing Half Adder
1. Assign symbols x and y to the two inputs
2. Assign S (for sum) and C (for carry) to the outputs.
3. Formulate a truth table to identify exactly the function of the half-adder.
Truth table

• The carry output is 0 unless both inputs are 1. The S output

represents the least significant bit of the sum. The simplified
Boolean functions for the two outputs can be obtained directly
from the truth table.
• The simplified SOP expressions are S=x'y+xy'
C = xy
• Logic Diagram
Full Adder
A full-adder is a combinational circuit that forms the arithmetic sum of three input bits.
• It consists of three inputs and two outputs. Two of the input variables, denoted by x
and y, represent the two significant bits to be added. The third input, Z, represents
the carry from the previous lower significant position.
• Designing the Full adder
• Two outputs are necessary because the arithmetic sum of three binary digits ranges
in value from 0 to 3, and binary 2 or 3 needs two digits.
• The two outputs are designated by the symbols S for sum and C for carry. The binary
variable S gives the value of the least significant bit of the sum. The binary variable C
gives the output carry. The truth table of the full-adder is
• Truth Table

• K Map

• The simplified SOP expressions are

S = x’y'z + x'yz' + xy'z’ + xyz
C = xy + xz + yz
• Logic Diagram in SOP form
 • Implementation of Full adder with two half adders and OR Gate Two half -adders
can be employed to implement a full-adder.
• A full-adder can be implemented with two half-adders and one OR gate, as shown in
Fig. 4- The S output from the second half-adder is the exclusive-OR of z and the
output of the first half-adder, giving sum and carry output as below

• Logic diagram:

Ripple Carry Adder

Ripple Carry Adder is a combinational logic circuit that is used for the purpose of adding
two n-bit binary numbers.
• It requires n full adders in its circuit for adding two n-bit binary numbers.
• It is also known as n-bit parallel adder.
Binary Parallel Adder
• 4-bit ripple carry adder is used for the purpose of adding two 4-bit binary numbers
• The sum of two n-bit binary numbers, A and B, can be generated in two ways: either
in a serial fashion or in parallel
• The serial addition method uses only one full-adder circuit and a storage device to
hold the generated output carry. The pair of bits in A and B are transferred serially,
one at a time, through the single full-adder to produce a string of output bits for the
sum. The stored output carry from one pair of bits is used as an input carry for the
next pair of bits.
• The parallel method uses n full-adder circuits, and all bits of A and B are applied
simultaneously. The output carry from one full-adder is connected to the input carry
of the full-adder one position to its left. As soon as the carries are generated, the
correct sum bits emerge from the sum outputs of all fulladders.
• In parallel adder all the bits of the augend and addend are available for computation
at the same time.
• It can be constructed with full adders connected in cascade with the output carry
from each adder connected to the input carry of the next full adder in the chain An
n bit adder requires n full adder.
• The carries are connected in a chain through the full adders. The input carry to the
adder is C0, and I tripples through the full adders to the output carry C4.
• All the carries must be generated for the correct sum bits to appear at the outputs.
Therefore, the sum and carry outputs of any stage cannot be produced until the
input carry occurs. This delay is known as carry propagation delay.
Carry Propagation
• The signal must propagate through the gates before the correct output sum is
available in the output terminals. The total propagation time is equal to the
propagation delay of a typical gate, times the number of gate levels in the circuit.
• The longest propagation delay time in an adder is the time it takes the carry to
propagate through the full adders. Since each bit of the sum output depends on the
value of the input carry.
•
• Disadvantages
 • Ripple Carry Adder does not allow to use all the full adders simultaneously.
• Each full adder has to necessarily wait until the carry bit becomes available from its
adjacent full adder this increases the propagation time.
• Due to this reason, ripple carry adder becomes extremely slow.and it is considered
to be the biggest disadvantage of using ripple carry adder
• There are several techniques for the reduction of carry propagation delay time.
However, the most widely used method employs the principle of look ahead carry
generation

Carry Look Ahead Adder

• Logic Diagram

• The output sum and carry can respectively be expressed as

• Gi is called a carry generate, and it produces a carry of 1 when both Ai and Bi are 1,
regardless of the input carryCi.
• Pi is called a carry propagate-it determines whether a carry in stage i will propagate
into stage i+1
 • This circuit can add in less time because C3 does not have to wait for C2 and C1 to
propagate.C3 is propagated at the same time as C1 & C2.
• The three Boolean functions for C1,C2 & C3 are implemented in the carry lookahead
generator as shown in figure below Four bit adder with carry look ahead
• The 4-bit binary adder using full adder circuits is capable of adding two 4-bit
numbers resulting in a 4-bit sum and a carry output as shown in figure below.

SUBTRACTOR

Elementary subtraction 0-0 = 0, 0-1=1, 1-0=1, 1-1=0

Design of Half subtractor
Design of Full Subtractor
Implementing Full subtractor using 2 half subtractors and OR gate
DECIMAL ADDER
• Computers that perform arithmetic operations directly in the decimal number
system represent decimal numbers in binary coded form.
• An adder circuit that accepts coded decimal numbers as input and present results in
the same coded decimal form is the decimal adder.
• A decimal adder requires a minimum of nine inputs and five outputs.There is wide
variety of possible decimal adder circuits, depending upon the code used to
represent the decimal digits

BCD adder
A BCD adder is a circuit that adds two BCD digits with an input carry from the previous
stage and produces a sum digit also a BCD
• Since each input digit does not exceed 9, the output sum cannot be greater than
9+9+1 =19.
• If two BCD digits are applied to a four-bit binary adder,the adder will form the sum in
binary and produce a result that ranges from 0 through 19.

• These binary numbers are listed in Table and are labeled by symbols K , Z8, Z4, Z2,
and Z1. K is the carry.
• The output sum of two decimal digits must be represented in BCD and should
appear in the form listed in the columns under―BCD Sum.
• when the Binary-sum is equal to or less than 1001, the corresponding BCD number is
identical. No conversion is needed.
• When the binary sum is greater than 1001, needs conversion for BCD
representation.
• The addition of binary 6 (0110) to the binary sum converts it to the correct BCD
representation and also produces an output carry as required.
• The logic circuit that detects the necessary Correction can be derived from the
entries in the table.
• A correction is needed when the binary sum has an output carry K= 1.
• The other six combinations from 1010 through 1111 that need a correction have a 1
in position Z8.
• To distinguish them from binary 1000 and1001, which also have a 1 in position Z8,we
specify further that either Z4 or Z2 must have a‘1‘.
• The condition for a correction and an output carry can be expressed by the Boolean
function C = K + Z8Z4 + Z8Z2 When C = 1, it is necessary to add 0110 to the binarysum
and provide an output carry for the next stage.
• To implement BCD adder we require 4 bit binary adder for initial addition - The two
decimal digits, together with the input carry, are first addedin the top four-bit adder
to produce the binary sum
• Logic circuit to detect sum greater than 9 One more four bit adder to add (0010)2 to
the sum. if the output carry is equal is 1
 Block diagram of BCD adder

• A BCD adder must include the correction logic in its internal construction.
• To add 0110 to the binary sum, a second 4-bit binary adder is needed as shown in
Figure
• The two decimal digits, together with the input carry, are first added in the top 4bit
binary adder to produce the binary sum.
• When the output carry is equal to zero, nothing is added to the binary sum.
• When it is equal to one, binary 0110 is added to the binary sum through the bottom
4-bit binary adder.
 • The output carry generated from the bottom binary adder can be ignored, since it
supplies information already available at the output-carry terminal.
• To achieve shorter propagation delays, a BCD adder includes the necessary circuits
for look-ahead carries.
• A decimal parallel adder that adds n decimal digits needs n BCD adder stages.
• The output carry from one stage must be connected to the input carry of the next
higherorder stage

MAGNITUDE COMPARATOR
A magnitude comparator is a combinational circuit that compares two numbers, A and B,
and determines their relative magnitudes. This comparison of two numbers determines if
one number is greater than, less than, or equal to the other number.
The outcome of the comparison is specified by three binary variables that indicate
whether A > B, A = B, or A < B, if A and B are the two numbers being compared.

1 bit magnitude comparator

A comparator used to compare two bits is called a single-bit comparator.
• It consists of two inputs each for two single-bit numbers and
three outputs to generate less than, equal to, and greater than
between two binary numbers. Inputs A,B of single bit
• Truth table

• The simplfied boolean function, when

A>B: F= AB'
A<B: F= A'B
A=B: F= A'B' + AB
• Logic diagram
2 bit magnitude comparator
A comparator used to compare two binary numbers each of two bits is called a 2-bit
Magnitude comparator. It consists of four inputs and three outputs to generate less than,
equal to, and greater than between two binary numbers.
• Inputs A,B of two bits A= A1A0, B=B1B0

• Truth table

• Logic Diagram:
n bit magnitude comparator
• The circuit for comparing two n-bit numbers has 2'" entries in the truth table and
becomes too cumbersome even with n = 3.
• It is inherent that a comparator circuit possesses a certain amount of regularity.
Digital functions that possess an inherent well-defined regularity can usually be
designed by means of an algorithmic procedure.
• This method is illustrated by deriving an algorithm for the design of a 4-bit
magnitude comparator. The algorithm is a direct application of the procedure a
person uses to compare the relative magnitudes of two numbers.
4 bit magnitude comparator
• Consider two numbers, A and B, with four digits each.
• Write the coefficients of the numbers with descending significance as follows:
A = A3A2A1A0
B = B3 B2 B1 B0,
• Each subscripted letter represents one of the digits in the number. It is observed
from the bit contents of two numbers that A = B when A3 = B3, A2 = B2, A1 = B1 and
A0 = B0.
When A=B
1. the numbers are binary they possess the value of either 1 or 0, the equality
relation of each pair can be expressed logically by the equivalence function as,
 2.
3. The equality of the two numbers, A and B, is displayed in a combinational
circuit by an output binary variable that we designate by the symbol (A = B).
4. This binary variable is equal to I if the input numbers, A and B, are equal, and it
is equal to 0 otherwise.
5. For the equality condition to exist, all Xi variables must be equal to I. This
dictates an AND operation of all variables: (A = B) = X3X2X,XO
6. The binary variable (A = B) is equal to I only if all pairs of digits of the two
numbers are equal.
If A>B or A<B
1. To determine if A is greater than or less than B, inspect the relative magnitudes of
pairs of significant digits starting from the most significant position.
2. If the two digits are equal, compare the next lower significant pair of digits. This
comparison continues until a pair of unequal digits is reached.
3. If the corresponding digit of A is I and that of B is 0, conclude that A > B.
4. if If the corresponding digit of A is 0 and that of B is 1, then conclue A < B.
5. The sequential comparison can be expressed logically by the following two
Boolean functions:

The symbols (A > B) and (A < B) are binary output variables that are equal to I when
A > B or A < B, respectively.
• Logic diagram
• The gate implementation of the three output variables just derived is simpler
than it seems because it involves a certain amount of repetition.
• The "unequal" outputs can use the same gates that are needed to generate the
"equal" output
• The four x outputs are generated with equivalence (exclusive·NOR) circuits and
applied to an AND gate to give the output binary variable (A = B). The other two
outputs use the x variables to generate the Boolean functions listed before. The
same circuit can be used to compare the relative magnitudes of two BCD digits.
DECODER
• A decoder is a combinational circuit that converts binary information from n input
lines to a maximum of 2n unique output lines. If the n-bit decoded information has
unused or don't-care combinations, the decoder output will have fewer than 2 n
outputs.
• A binary code of n bits is capable of representing up to 2 n distinct elements of the
coded information.
Block diagram

• The encoded information is presented as ‘n’ inputs producing ‘2n’ possible outputs.
The 2n output values are from 0 through 2n-1.
• A decoder is provided with enable inputs to activate decoded output based on data
inputs. When any one enable input is unasserted, all outputs of decoder are
disabled.

Binary decoder(2:4 decoder)

• A binary decoder has ‘n’ bit binary input and a one activated output out of 2 n
outputs. A binary decoder is used when it is necessary to activate exactly one of 2 n
outputs based on an n-bit input value
• Here the 2 inputs are decoded into 4 outputs, each output representing one of the
minterms of the two input variables, 1 Enable input has path to all four outputs
Block diagram

• Truth table
 • if enable input is 1 (EN= 1) only one of the outputs (Y 0 – Y3), is active for a given
input. The output Y0 is active, ie., Y0= 1 when inputs A= B= 0, Y1 is active when
inputs, A= 0 and B= 1, Y2 is active, when input A= 1 and B= 0, Y3 is active, when
inputs A= B= 1.
• Boolean function:

• Logic diagram

n-to-m line decoders

• The decoders are called n-to-m-line decoders, where m <;2 n. Their purpose is to
generate the 2n (or fewer) minterms of n input variables.
• The name decoder is also used in conjunction with some code converters such as a
BCD-to-sevensegment decoder.
• 3-to-8-line decoder can be used for decoding any 3-bit code to provide eight
outputs, one for each element of the code
• A decoder with enable inputs can be connected to for larger decoder circuit

3:8 decoder
• A 3-to-8 line decoder has three inputs (A, B, C) and eight outputs (Y0- Y7).
• Based on the 3 inputs one of the eight outputs is selected.
• The three inputs are decoded into eight outputs, each output representing one of
the minterms of the 3-input variables.
• This decoder is used for binary-to-octal conversion The input variables may
represent a binary number and the outputs will represent the eight digits in the octal
number system
• The output variables are mutually exclusive because only one output can be equal to
1 at any one time.
• For each possible input combination, there are seven outputs that are equal to 0 and
only one that is equal 1
• The output line whose value is equal to 1 represents the minterm equivalent of the
binary number presently available in the input lines.
• The three inputs are decoded into eight outputs, each output representing one of
the minterms of the 3input variables.
• Block diagram

• Truth table

• Logic Diagram
The three inverters provide the complement of the inputs, and each one of the eight
AND gates generates one of the minterms.
• Constructing 4-to-16 line decoder using two 3-to-8 line decoder
1. When w=0, the top decoder is enabled, and the eight outputs generate minterms
from 0000 to 0111 while the outputs of bottom decoder are all 0s
2. When w=1, the bottom decoder is selected the outputs generate minterms from
1000 to 1111 while the outputs of top decoder are all 0s
ENCODER
An encoder is a digital circuit that performs the inverse operation of a decoder. Hence, the
opposite of the decoding process is called encoding.
An encoder is a combinational circuit that converts binary information from 2 n input lines to
a maximum of ‘n’ unique output lines.
Block diagram

• An encoder has 2" (or fewer) input lines and n output lines. The output lines
generate the binary code corresponding to the input value.
• Types: 4 to 2 encoder, 8 to 3 encoder(octal to-binary encoder), 16 to 4(hexadecimal
to binary), decimal to BCD encoder, Proiority encoder
Octal to binary encoder
• It has eight inputs, one for each of the octal digits, and three outputs that generate
the corresponding binary number.
• It is assumed that only one input has a value of 1 at any given time;
• The encoder can be implemented with OR gates whose inputs are determined
directly from the truth table. Truth table

• Output z is equal to 1 when the input octal digit is I or 3 or 5 or 7.

• Output y is 1 for octal digits 2, 3, 6, or 7,
• output x is 1 for digits 4, 5, 6, or 7.
 • Boolean Function
These conditions can be expressed by the following output Boolean functions:

• Logic Diagram

• Liimitation:
1. that only one input can be active at any given time. If two inputs are active
simultaneously, the output produces an undefined combination.
Example if D3 and D6 are I simultaneously, the output of the encoder will be
III because all three outputs are equal to I. This does not represent binary 3
nor binary 6. To resolve this ambiguity, encoder circuits must establish a
priority to ensure that only one input is encoded. If high priority for higher
subscript numbr is given and D3 and D6 are I at the same time, the output will
be 110 because D6 has higher priority than D3
2. Another ambiguity in the octal-to-binary encoder is that an output with all D's
is generated when all the inputs are O. The problem is that an output with all
D's is also generated when Do is equal to I. This ambiguity can be resolved by
providing an additional output that specifies the condition that none of the
inputs are active
Priority encoder
A priority encoder is an encoder circuit that includes the priority function. The operation of
the priority encoder is such that if two or more inputs are equal to 1 at the same time, the
input having the highest priority will take precedence.
• 4 input priority encoder
• In addition to the two outputs x and y, a third output V (valid bit
indicator) is reqrequired. It is set to 1 when one or more inputs are
equal to 1. If all inputs are 0, there is no valid input and V is equal to
0.
• The higher the subscript number, higher the priority of the input.
Input D3, has the highest priority. So, regardless of the values of the
other inputs, when D3 is 1, the output for xy is 11. D2 has the next
priority level. The output is 10, if D2= 1 provided D3= 0. The output
for D1 is generated only if higher priority inputs are 0, and so on
down the priority levels.
• Truth table

1. The X's are don't-care conditions that may be 0 or 1. Input D3, has the highest
priority when
2. D3 =1, xy is 11
3. D2=1, xy is 10 provided thatD3=0
4. D1=1 only if D3=D2=0.
5. A valid-output indicator, designated by V, is set to 1 only when one or more of
the inputs are equal to 1. If all inputs are 0, V is equal to 0, and the other two
outputs of the circuit are not used
6. Although the above table has only five rows, when each don’t care condition is
replaced first by 0 and then by 1, 16 possible input combinations.The don’t
care condition is replaced by 0 and 1 as shown in the table below.
7.Modified truth table
• K Map and boolean function

• Logic diagram
MULTIPLEXER(data selector)
A Multiplexer or MUX, is a combinational circuit with more than one input line, one output
line and more than one selection line. A multiplexer selects binary information present from
one of many input lines, depending upon the logic status of the selection inputs, and directs
it to the output line. There are 2 n input lines and n selection lines whose bit combinations
determine which input is selected. A multiplexer is also called a data selector, since it
selects one of many inputs and steers the binary information to the output line.
Block diagram

2 to 1 line MUX
• The circuit has two data input lines, one output line and one selection line, S.
1. When S= 0, the upper AND gate is enabled and I0 has a path to the output.
2. When S=1, the lower AND gate is enabled and I1 has a path to the output.
• The multiplexer acts like an electronic switch that selects one of the two
sources. Block diagram

• Truth table and logic diagram

4 to 1 line MUX
A 4-to-1-line multiplexer has four (2n) input lines, two (n) select lines and one output line.
• 4 input channels and information of one of the channels can be selected and
transmitted to an output line according to the select inputs combinations.
• Two selection inputs S0 and S1

• Block diagram, Logic diagram and Function table


Each of the four inputs I0 through I3, is applied to one input of AND gate. Selection
lines S1 and S0 are decoded to select a particular AND gate. The outputs of the AND
gate are applied to a single OR gate that provides the 1-line output.
• To demonstrate the circuit operation. when S1S0= 10. The AND gate associated with
input I2 has two of its inputs equal to 1 and the third input connected to I2. The
other three AND gates have atleast one input equal to 0, which makes their outputs
equal to 0. The OR output is now equal to the value of I2, providing a path from the
selected input to the output.

• As in decoder, multiplexers may have an enable input to control the operation of

the unit. When the enable input is in the inactive state, the outputs are disabled,
and when it is in the active state, the circuit functions as a normal multiplexer
• The enable input (sometimes called strobe) can be used to expand two or more
multiplexers to a digital multiplexer with a larger number of inputs
 
Quadruple 2-to-1 Line Multiplexer

This circuit has four multiplexers, each capable of selecting one of two input lines.
• Output Y0 can be selected to come from either A0 or B0.
• Similarly, output Y1 may have the value of A1 or B1, and so on.
• Input selection line, S selects one of the lines in each of the four multiplexers.
• The enable input E must be active for normal operation.
• Although the circuit contains four 2-to-1-Line multiplexers, it is viewed as a circuit
that selects one of two 4-bit sets of data lines.
• The unit is enabled when E= 0.
• Then if S= 0, the four A inputs have a path to the four outputs. On the other hand, if
S=1, the four B inputs are applied to the outputs.
• The outputs have all 0’s when E= 1, regardless of the value of S.
• Application:
1. They are used as a data selector to select out of many data inputs.
2. They can be used to implement combinational logic circuit.
3. They are used in time multiplexing systems.
4. They are used in frequency multiplexing systems.
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5. They are used in A/D and D/A converter.
6. They are used in data acquisition systems.

DEMULTIPLEXER
Demultiplex means one into many. Demultiplexing is the process of taking information
from one input and transmitting the same over one of several outputs.
• A demultiplexer is a combinational logic circuit that receives information on a
single input and transmits the same information over one of several (2n) output
lines.
Block Diagram

• The block diagram of a demultiplexer which is opposite to a multiplexer in its

operation
• The circuit has one input signal, ‘n’ select signals and 2n output signals.
The select inputs determine to which output the data input will be connected.
• As the serial data is changed to parallel data, i.e., the input caused to appear on
one of the n output lines,
• the demultiplexer is also called a “data distributer” or a “serial-to-parallel
converter”.
1-to-4 line Demultiplexer
• A 1-to-4 demultiplexer has a single input, Din, four outputs (Y0 to Y3) and two select
inputs (S1 and S0).
• The input variable Din has a path to all four outputs, but the input information is
directed to only one of the output lines. The truth table of the 1-to-4 demultiplexer
is shown below.


• Block diagram


• Truth table

• the data input, Din is connected to the output Y0, when S1= 0 and S0= 0 and the
data input is connected to output Y1 when S1= 0 and S0= 1.
• the data input is connected to output Y2 and Y3 when S1= 1 and S0= 0 and when
S1= 1 and S0= 1, respectively.
• the expression for outputs from truth table can be written as follows,
 • Logic diagram

• a 1-to-4 demultiplexer can be implemented using four 3-input AND gates and two
NOT gates. the input data line Din, is connected to all the AND gates.
• The two select lines S1, S0 enable only one gate at a time
• the data that appears on the input line passes through the selected gate to the
associated output line
1-to-8 Demultiplexer
A 1-to-8 demultiplexer has a single input, Din, eight outputs (Y0 to Y7) and three select
inputs (S2, S1 and S0). It distributes one input line to eight output lines based on the select
inputs. truth table

• the data input is connected with one of the eight outputs based on the select
inputs.
• Now from this truth table, the expression for eight outputs can be written as
follows:

• logic diagram
• the single data line, Din is connected to all the eight AND gates, but only one
of the eight AND gates will be enabled by the select input lines.
• For example, if S2S1S0= 000, then only AND gate-0 will be enabled and
thereby the data input, Din will appear at Y0. Similarly, the different
combinations of the select inputs, the input Din will appear at the respective
output.
Design 1:8 demultiplexer using two 1:4 DEMUX.