What is Metastability in VLSI and How to

Avoid it?
Metastability in VLSI is an unstable equilibrium occurrence in digital electronics in which the sequential
element is unable to resolve the state of the input signal. This causes the output to remain unresolved for
an infinite period. This often occurs when data transitions extremely close to the active edge of the clock,
breaking setup and holding constraints. Because the data transitions near the active edge of the clock,
the flop is unable to catch the data entirely. The flop begins to capture data, and the output begins to
transition. However, before the output changes its state, the input is disconnected from the output when
the clock edge arrives.

How Does Metastability in VLSI Occur?

When there is setup and hold time violations in a flip-flop, it enters a state in which its output is
unpredictable: this is known as a metastable state (quasi-stable state). At the end of the metastable state,
the flip-flop settles down to either ‘1’ or ‘0’. This is referred to as metastability. When the flip-flop is in a
metastable state, the output oscillates between ‘0’ and ‘1’. The time it takes to settle down is determined
by the technology of the flip-flop.

How To Avoid Metastability In VLSI?

In reality, it is impossible to prevent metastability without the employment of complex self-timed circuits
and increasing clock-to-Q delays when synchronizing asynchronous inputs. Designers can tolerate
metastability in the simplest instance by ensuring that the clock period is long enough to allow for the
resolution of quasi-stable states and the delay of whatever logic is in the route to the next flip-flop. This
strategy is rarely viable given the performance needs of most current systems.

Tolerating metastability in VLSI is most commonly accomplished by adding one or more subsequent
synchronizing flip-flops to the synchronizer. This method permits metastable events in the first
synchronizing flip-flop to resolve themselves across a complete clock period. However, this increases the
delay in the perception of input changes of the synchronous logic. Neither of these systems can ensure
that metastability will not pass through the synchronizer. They only lower the likelihood to manageable
levels.

Conclusion

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Chipedge is the right place for you. It is the best VLSI training institute in Bangalore that offers a wide
range of VLSI courses online that includes VLSI design courses, DFT courses, RTL courses, Design
verification courses, and many more. Enroll yourself now.
The noise margin in VLSI

The noise margin in VLSI is the amount of noise that a CMOS circuit can endure without interfering with
its function. The noise margin ensures that any logic ‘1’ signal with finite noise added to it is still identified
as logic ‘1’ and not logic ‘0’. It is essentially the difference between the signal and noise values.

What exactly is the noise margin in VLSI?

Noise margin is a measure of design margins used to guarantee that circuits operate properly under
defined conditions. The operation environment, power supply, electric and magnetic fields, and radiation
waves are all sources of noise. Unwanted noise can also be generated by on-chip transistor switching
activity. Circuits must be constructed with defined noise margins to guarantee that transistors switch

properly under specified noisy situations.

What is the mechanism of noise margin in a VLSI digital circuit?

The noise margin in a VLSI digital circuit is the amount by which the signal exceeds the threshold for a
correct ‘0’ or ‘1’. As an example, a digital circuit may be constructed to swing between 0.0 and 1.2 volts,
with anything less than 0.2 volts regarded as a ‘0’ and anything greater than 1.0 volts considered as a ‘1’.
The noise margin for a ‘0’ is the amount by which a signal is less than 0.2 volts, while the noise margin for
a ‘1’ is the amount by which a signal exceeds 1.0 volts. Noise margins are assessed as an absolute
voltage rather than a ratio in this situation. Because VOH min is closer to the power supply voltage and
VOL max is closer to zero, noise margins for CMOS chips are often substantially higher than those for
TTL.

There are two noise margins to consider: high noise margin (NMH) and low noise margin (NML). NMH is
the voltage difference between an inverter moving from a logic high (1) to a logic low (0) and vice versa
for NML. Equations are:

NMH ≡ VOH – VIH and NML ≡ VIL – VOL

With a CMOS inverter, VOH equals VDD and VOL equals the ground potential.

In practice, the noise margin in VLSI is the amount of noise that a logic circuit can endure. Positive noise
margins ensure correct operation, whereas negative noise margins result in impaired functioning or
outright failure.

Conclusion

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make a career in the VLSI field, then Chipedge is here to help you. Being the best VLSI training institute
in Bangalore, it offers a wide range of online VLSI courses that covers courses
including DFT, RTL, Design Verification, and many more. Enroll yourself now.
Fanout
In VLSI (Very Large Scale Integration), the term "max fanout" refers to the maximum
number of standard loads that a gate output can drive while still maintaining correct
logic levels. It is an important parameter in digital circuit design, as exceeding the
max fanout can lead to signal degradation and timing issues.

Fanout" in system design

The Fan-out Pattern is a software design pattern commonly used in distributed systems to efficiently
manage and distribute messages from a single source to multiple destinations. In this pattern, there is a
central component or service that acts as the source of messages.

What is fan-out in cmos?

CMOS has the maximum fan-out capacity. Additional Information. Fan-Out is the maximum number of
inputs that can be connected to the output of a gate without affecting the normal operation..

Synchronous circuit

In digital electronics, a synchronous circuit is a digital circuit in which the changes in

the state of memory elements are synchronized by a clock signal. In a sequential digital
logic circuit, data are stored in memory devices called flip-flops or latches. The output of
a flip-flop is constant until a pulse is applied to its "clock" input, upon which the input of
the flip-flop is latched into its output. In a synchronous logic circuit, an electronic
oscillator called the clock generates a string (sequence) of pulses, the "clock signal".
This clock signal is applied to every storage element, so in an ideal synchronous circuit,
every change in the logical levels of its storage components is simultaneous. Ideally, the
input to each storage element has reached its final value before the next clock occurs,
so the behaviour of the whole circuit can be predicted exactly. Practically, some delay is
required for each logical operation, resulting in a maximum speed limitations at which
each synchronous system can run.

To make these circuits work correctly, a great deal of care is needed in the design of
the clock distribution networks. Static timing analysis is often used to determine the
maximum safe operating speed.
Nearly all digital circuits, and in particular nearly all CPUs, are fully synchronous circuits
with a global clock. Exceptions are often compared to fully synchronous circuits.
Exceptions include self-synchronous circuits, globally asynchronous locally
[1][2][3][4]

synchronous circuits, and fully asynchronous circuits.

synchronous sequential circuits are digital circuits that use clock signals to
determine the timing of their operations. They are commonly used in digital systems
to implement timers, counters, and memory elements and are essential components
in digital systems design.

What Is a Finite State Machine?

A finite state machine (FSM) is a mathematical model used to represent
and control the behavior of systems that can exist in a finite number of
states at any given time. It is a concept widely used in computer science,
engineering, and other fields to design, analyze, and implement systems
with discrete and sequential behavior.
At its core, an FSM consists of a set of states, a set of input events or
stimuli, a set of output actions or responses, and a set of transitions
between states based on input events. It can be visualized as a directed
graph where nodes represent the states and the edges connecting the
nodes represent transitions.
Let’s look at what an FSM is in simple terms.
Imagine you have a robot that can perform different tasks. At any given
moment, the robot can be in one of a limited number of states, such as
‘Idle,’ ‘Moving,’ or ‘Cleaning.’ These states represent the robot’s current
condition or what it is doing.
Now, let’s say the robot receives different commands or events, such as
pressing a button or detecting an obstacle. These commands or events
can cause the robot to change its state and perform different actions.
An FSM is like a blueprint or a set of rules that helps the robot decide
what to do in each state and how to transition from one state to another
based on the commands or events it receives. It’s like a decision-making
mechanism for the robot.
For example, if the robot is in the ‘Idle’ state and receives a command to
start cleaning, the FSM will tell the robot to transition to the ‘Cleaning’
state and start performing the cleaning action. Similarly, if the robot is in
the ‘Moving’ state and it detects an obstacle, the FSM will instruct the
robot to transition to the ‘Avoiding’ state and change its path to avoid the
obstacle.
In short, an FSM helps control the behavior of a system or a robot by
defining its different states, the actions it can take in each state, and how
it transitions between states based on the commands or events it
receives. It is similar to a rulebook that guides the system’s decision-
making process and helps it respond appropriately to different situations.
FSMs are widely used to model and control systems with discrete and
sequential behavior, such as software protocols, digital circuits, robotic
systems, and user interfaces, among others. They provide a structured
and systematic approach to designing and analyzing complex systems,
making them easier to understand, implement, and maintain.
Types of FSM
FSMs are widely used in various fields such as electronics, robotics,
networking and telecommunications, and everyday applications. A few
common types of FSMs are:
1. Deterministic finite state machine (DFSM)
In a deterministic FSM, each state transition is uniquely determined by
the current state and input. This means that given a specific input and
current state, only one possible transition to the next state exists.
Example: Vending Machine
Let’s consider a vending machine with three states: Idle, Selection, and
Dispense. The transitions between these states depend on user input and
the current state. For instance, if the current state is ‘Idle’ and the user
selects a product, the machine transitions to the ‘Selection’ state. If the
user confirms the selection, the machine moves to the ‘Dispense’ state
and dispenses the chosen item. This example showcases a deterministic
FSM because, for each input and state, there is a unique next state.
2. Non-deterministic finite state machine (NDFSM)
Non-deterministic FSMs allow multiple transitions for a given input and
current state. This means that the next state is not uniquely determined
and the machine can be in multiple states simultaneously.
Example: Elevator System
Let’s consider an elevator system with four floors: Ground, First, Second,
and Third. When a user presses a button inside the elevator, the desired
floor can be reached in different ways. For instance, if the current state is
‘Ground’ and the user presses the button for the third floor, the elevator
can take different paths, such as stopping at the first floor and then on
the second floor before finally reaching the third floor. This example
illustrates a non-deterministic FSM since multiple transitions are possible
for the same input and state.
3. Mealy machine
Mealy machines are FSMs that not only define the states and transitions
but also associate outputs with each transition. The outputs in these
types of machines rely on both the current state and the input.
Example: Coin-operated Turnstile System
Consider a coin-operated turnstile system. The turnstile has two states:
‘Locked’ and ‘Unlocked.’ When a coin is inserted (input) while in the
‘Locked’ state, the system transitions to the ‘Unlocked’ state and outputs
a signal to allow the person to pass through (output). On the other hand,
if someone tries to pass through without inserting a coin (input) while in
the ‘Locked’ state, the system remains in this state and outputs a signal
indicating that access is denied (output). In this example, the outputs
(pass or access denied signals) depend on both the current state and the
input, showcasing the behavior of a Mealy machine.
4. Moore machine

A Moore machine is a type of FSM where the outputs depend only on the
current state. This implies that regardless of the inputs, the outputs are
determined by the state the machine is in. The transitions between states
are triggered by the inputs, but the outputs are associated with the states
themselves.

Example: Doorbell System

A doorbell system has two states: ‘Idle’ and ‘Ring.’ When someone
presses the doorbell button (input), the system transitions from the ‘Idle’
state to the ‘Ring’ state. In the ‘Ring’ state, the system continuously
outputs a ringing sound (output) until the button is released. Once the
button is released, the system transitions back to the ‘Idle’ state. In this
example, the outputs (ringing sound) depend only on the current state,
regardless of the input, illustrating the behavior of a Moore machine.
See More: What Is UMTS (Universal Mobile Telecommunication System)?
Meaning, Working, Importance, and Applications
How Does a Finite State Machine Work?
Finite state machines provide a systematic way of controlling and
managing systems with discrete and sequential behavior. By defining
states, transitions, and output actions, FSMs allow for clear and structured
design and analysis of complex systems, making them easier to
understand and implement.

Let’s break down how an FSM works in a step-by-step process.

Latch
A latch is an electronic device that changes its output immediately on the basis of the applied input. One
can use it to store either 0 or 1 at a specified time. A latch contains two inputs- SET and RESET, and it
also has two outputs. They complement each other.

A door latch is a general type of latch used for keeping doors or gates closed. A typical door latch is a
door knob composed of a latching mechanism, a locking mechanism, and two knobs on the interior and
exterior sides. Other types of latches are bolt, spring, cam, compression, slam, and rotary latches.
 The simplest bistable device, therefore, is known as a set-reset, or S-R, latch. To create an S-R latch, we
can wire two NOR gates in such a way that the output of one feeds back to the input of another, and vice
versa, like this: The Q and not-Q outputs are supposed to be in opposite states.

A latch or catch (called sneck in Northern England and Scotland) is a type of mechanical fastener
that joins two (or more) objects or surfaces while allowing for their regular separation. A latch typically
engages another piece of hardware on the other mounting surface.

A D latch is like an S-R latch with only one input: the “D” input. Activating the D input sets the circuit, and
de-activating the D input resets the circuit. Of course, this is only if the enable input (E) is activated as
well. Otherwise, the output(s) will be latched, unresponsive to the state of the D input. A D latch is like an
S-R latch with only one input: the “D” input. Activating the D input sets the circuit, and de-activating the D
input resets the circuit. Of course, this is only if the enable input (E) is activated as well. Otherwise, the
output(s) will be latched, unresponsive to the state of the D input.

In summary, latches are digital circuits that store a single bit of information and hold
its value until it is updated by new input signals. There are two types of latches: S-R
(Set-Reset) Latches and D (Data) Latches, and they are widely used in digital
systems for various applications.

Master–slave edge-triggered
Master–slave edge-triggered D flip-flopThis allows the "master" latch to store the
input value when the clock signal transitions from low to high. As the clock signal
goes high (0 to 1) the inverted "enable" of the first latch goes low (1 to 0) and the
value seen at the input to the master latch is "locked".
They are:types
 Latch or Set-Reset (SR) flip-flop.
 JK flip-flop.
 T (Toggle) flip-flop.
 D (Delay or Data) flip-flop.

Counters

A Counter is a device which stores (and sometimes displays) the number of times a particular
event or process has occurred, often in relationship to a clock signal. Counters are used in digital
electronics for counting purpose, they can count specific event happening in the circuit. For
example, in UP counter a counter increases count for every rising edge of clock. Not only
counting, a counter can follow the certain sequence based on our design like any random
sequence 0,1,3,2… .They can also be designed with the help of flip flops. They are used as
frequency dividers where the frequency of given pulse waveform is divided. Counters are
sequential circuit that count the number of pulses can be either in binary code or BCD form. The
main properties of a counter are timing , sequencing , and counting. Counter works in two modes
Up counter
Down counter
Counter Classification
Counters are broadly divided into two categories

1. Asynchronous counter
2. Synchronous counter
1. Asynchronous Counter
In asynchronous counter we don’t use universal clock, only first flip flop is driven by main clock
and the clock input of rest of the following flip flop is driven by output of previous flip flops. We can
understand it by following diagram-

It is evident from timing diagram that Q0 is changing as soon as the rising edge of clock pulse is
encountered, Q1 is changing when rising edge of Q0 is encountered(because Q0 is like clock
pulse for second flip flop) and so on. In this way ripples are generated through Q0,Q1,Q2,Q3
hence it is also called RIPPLE counter and serial counter. A ripple counter is a cascaded
arrangement of flip flops where the output of one flip flop drives the clock input of the following flip
flop
2. Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock which drives each flip
flop so output changes in parallel. The one advantage of synchronous counter over asynchronous
counter is, it can operate on higher frequency than asynchronous counter as it does not have
cumulative delay because of same clock is given to each flip flop. It is also called as parallel
counter.

Synchronous counter circuit

Timing diagram synchronous counter

From circuit diagram we see that Q0 bit gives response to each falling edge of clock while Q1 is
dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is dependent on Q2,Q1 and Q0.

Decade Counter
A decade counter counts ten different states and then reset to its initial states. A simple decade
counter will count from 0 to 9 but we can also make the decade counters which can go through
any ten states between 0 to 15(for 4 bit counter).
 Q
Clock pulse Q2 Q1 Q0
3

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 0 0 0 0

Truth table for simple decade counter

Decade counter circuit diagram

We see from circuit diagram that we have used nand gate for Q3 and Q1 and feeding this to clear
input line because binary representation of 10 is—
1010
And we see Q3 and Q1 are 1 here, if we give NAND of these two bits to clear input then counter
will be clear at 10 and again start from beginning.
Important point: Number of flip flops used in counter are always greater than equal to (log2 n)
where n=number of states in counter.

Some previous years gate questions on Counters

Q1. Consider the partial implementation of a 2-bit counter using T flip-flops following the
sequence 0-2-3-1-0, as shown below

To complete the circuit, the input X should be

(A) Q2?
(B) Q2 + Q1
(C) (Q1 ? Q2)’
(D) Q1 ? Q2 (GATE-CS-2004)
Solution:
From circuit we see
T1=XQ1’+X’Q1—-(1)
AND
T2=(Q2 ? Q1)’—-(2)
AND DESIRED OUTPUT IS 00->10->11->01->00
SO X SHOULD BE Q1Q2’+Q1’Q2 SATISFYING 1 AND 2.
SO ANS IS (D) PART.

Q2. The control signal functions of a 4-bit binary counter are given below (where X is “don’t
care”)
The counter is connected as follows:

Assume that the counter and gate delays are negligible. If the counter starts at 0, then it
cycles through the following sequence:
(A) 0,3,4
(B) 0,3,4,5
(C) 0,1,2,3,4
(D) 0,1,2,3,4,5 (GATE-CS-
2007)
Solution:
Initially A1 A2 A3 A4 =0000
Clr=A1 and A3
So when A1 and A3 both are 1 it again goes to 0000
Hence 0000(init.) -> 0001(A1 and A3=0)->0010 (A1 and A3=0) -> 0011(A1 and A3=0) -> 0100 (A1
and A3=1)[ clear condition satisfied] ->0000(init.) so it goes through 0->1->2->3->4
Ans is (C) part.
Quiz on Digital Logic
Article contributed by Anuj Batham, Please write comments if you find anything incorrect, or you
want to share more information about the topic discussed above
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Shift Registers in Digital Logic

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Pre-Requisite: Flip-Flops
Flip flops can be used to store a single bit of binary data (1 or 0). However, in order to
store multiple bits of data, we need multiple flip-flops. N flip flops are to be connected in
order to store n bits of data. A Register is a device that is used to store such
information. It is a group of flip-flops connected in series used to store multiple bits of
data. The information stored within these registers can be transferred with the help
of shift registers.
Shift Register is a group of flip flops used to store multiple bits of data. The bits stored
in such registers can be made to move within the registers and in/out of the registers by
applying clock pulses. An n-bit shift register can be formed by connecting n flip-flops
where each flip-flop stores a single bit of data. The registers which will shift the bits to
the left are called “Shift left registers”. The registers which will shift the bits to the right
are called “Shift right registers”. Shift registers are basically of following types.

Types of Shift Registers

 Serial In Serial Out shift register
 Serial In parallel Out shift register
 Parallel In Serial Out shift register
 Parallel In parallel Out shift register
 Bidirectional Shift Register
 Universal Shift Register
 Shift Register Counter
Serial-In Serial-Out Shift Register (SISO)

The shift register, which allows serial input (one bit after the other through a single data
line) and produces a serial output is known as a Serial-In Serial-Out shift register. Since
there is only one output, the data leaves the shift register one bit at a time in a serial
pattern, thus the name Serial-In Serial-Out Shift Register. The logic circuit given below
shows a serial-in serial-out shift register. The circuit consists of four D flip-flops which
are connected in a serial manner. All these flip-flops are synchronous with each other
since the same clock signal is applied to each flip-flop.

Serial-In Serial-Out Shift Register (SISO)

The above circuit is an example of a shift right register, taking the serial data input from
the left side of the flip flop. The main use of a SISO is to act as a delay element.

Serial-In Parallel-Out Shift Register (SIPO)

The shift register, which allows serial input (one bit after the other through a single data
line) and produces a parallel output is known as the Serial-In Parallel-Out shift register.
The logic circuit given below shows a serial-in-parallel-out shift register. The circuit
consists of four D flip-flops which are connected. The clear (CLR) signal is connected in
addition to the clock signal to all 4 flip flops in order to RESET them. The output of the
first flip-flop is connected to the input of the next flip flop and so on. All these flip-flops
are synchronous with each other since the same clock signal is applied to each flip-flop.

Serial-In Parallel-Out shift Register (SIPO)

The above circuit is an example of a shift right register, taking the serial data input from
the left side of the flip-flop and producing a parallel output. They are used in
communication lines where demultiplexing of a data line into several parallel lines is
required because the main use of the SIPO register is to convert serial data into parallel
data.

Parallel-In Serial-Out Shift Register (PISO)

The shift register, which allows parallel input (data is given separately to each flip flop
and in a simultaneous manner) and produces a serial output is known as a Parallel-In
Serial-Out shift register. The logic circuit given below shows a parallel-in-serial-out shift
register. The circuit consists of four D flip-flops which are connected. The clock input is
directly connected to all the flip-flops but the input data is connected individually to
each flip-flop through a multiplexer at the input of every flip-flop. The output of the
previous flip-flop and parallel data input are connected to the input of the MUX and the
output of MUX is connected to the next flip-flop. All these flip-flops are synchronous with
each other since the same clock signal is applied to each flip-flop.
 Parallel-In Serial-Out Shift Register (PISO)

A Parallel in Serial Out (PISO) shift register is used to convert parallel data to serial data.

Parallel-In Parallel-Out Shift Register (PIPO)

The shift register, which allows parallel input (data is given separately to each flip flop
and in a simultaneous manner) and also produces a parallel output is known as Parallel-
In parallel-Out shift register. The logic circuit given below shows a parallel-in-parallel-out
shift register. The circuit consists of four D flip-flops which are connected. The clear
(CLR) signal and clock signals are connected to all 4 flip-flops. In this type of register,
there are no interconnections between the individual flip-flops since no serial shifting of
the data is required. Data is given as input separately for each flip flop and in the same
way, output is also collected individually from each flip flop.

Parallel-In Parallel-Out Shift Register (PIPO)

A Parallel in Parallel out (PIPO) shift register is used as a temporary storage device and
like SISO Shift register it acts as a delay element.

Bidirectional Shift Register

If we shift a binary number to the left by one position, it is equivalent to multiplying the
number by 2 and if we shift a binary number to the right by one position, it is equivalent
to dividing the number by 2. To perform these operations we need a register which can
shift the data in either direction. Bidirectional shift registers are the registers that are
capable of shifting the data either right or left depending on the mode selected. If the
mode selected is 1(high), the data will be shifted toward the right direction and if the
mode selected is 0(low), the data will be shifted towards the left direction. The logic
circuit given below shows a Bidirectional shift register. The circuit consists of four D flip-
flops which are connected. The input data is connected at two ends of the circuit and
depending on the mode selected only one gate is in the active state.

Bidirectional Shift Register

Universal Shift Register

Universal Shift Register is a type of register that contains the both right shift and the left
shift. It has also parallel load capabilities. Generally, these types of registers are taken
as memory elements in computers. But, the problem with this type of register is that it
shifts only in one direction. In simple words, you mean that the universal shift register is
a combination of the bidirectional shift register and the unidirectional shift
register.
 Universal Shift Register

N-bit universal shift register consists of flip-flops and multiplexers. Both are N in size. In
this, all the n multiplexers share the same select lines and this select input selects the
suitable input for flip-flops.

Shift Register Counter

Shift Register Counters are the shift registers in which the outputs are connected back
to the inputs in order to produce particular sequences. There are basically two types:
 Ring Counter
 Johnson Counter
Ring Counter
A ring counter is basically a shift register counter in which the output of the first flip-flop
is connected to the next flip-flop and so on and the output of the last flip-flop is again
fed back to the input of the first flip-flop, thus the name ring counter. The data pattern
within the shift register will circulate as long as clock pulses are applied. The logic
circuit given below shows a Ring Counter.

Ring Counter Truth Table

The circuit consists of four D flip-flops which are connected. Since the circuit consists of
four flip-flops the data pattern will repeat after every four clock pulses as shown in the
truth table. A Ring counter is generally used because it is self-decoding. No extra
decoding circuit is needed to determine what state the counter is in.

Ring Counter

Johnson Counter
A Johnson counter is basically a shift register counter in which the output of the first flip
flop is connected to the next flip flop and so on and the inverted output of the last flip
flop is again fed back to the input of the first flip flop. They are also known as twisted
ring counters. The logic circuit given below shows a Johnson Counter. The circuit
consists of four D flip-flops which are connected.

Johnson Counter Truth Table

An n-stage Johnson counter yields a count sequence of 2n different states, thus also
known as a mod-2n counter. Since the circuit consists of four flip-flops the data pattern
will repeat every eight clock pulses as shown in the truth table. The main advantage of
the Johnson counter is that it only needs n number of flip-flops compared to the ring
counter to circulate a given data to generate a sequence of 2n states.
 Johnson Counter

Applications of Shift Registers

 The shift registers are used for temporary data storage.
 The shift registers are also used for data transfer and data manipulation.
 The serial-in serial-out and parallel-in parallel-out shift registers are used to produce
time delay to digital circuits.
 The serial-in parallel-out shift register is used to convert serial data into parallel data
thus they are used in communication lines where demultiplexing of a data line into
several parallel lines is required.
 A Parallel in Serial out shift register is used to convert parallel data to serial data.

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