1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM

Features

DDR2 SDRAM SODIMM

MT16HTF12864HZ – 1GB
MT16HTF25664HZ – 2GB
MT16HTF51264HZ – 4GB

Features Figure 1: 200-Pin SODIMM (MO-224 R/C E)

• 200-pin, small-outline dual in-line memory module Module Height: 30mm (1.181 in.)
(SODIMM)
• Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
• 1GB (128 Meg x 64), 2GB (256 Meg x 64) or 4GB (512
Meg x 64)
• VDD = V DDQ = 1.8V
• VDDSPD = 1.7–3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture Options Marking
• Multiple internal device banks for concurrent • Operating temperature
operation – Commercial (0°C ≤ T A ≤ +70°C) None
– Industrial (–40°C ≤ T A ≤ +85°C)1 I
• Programmable CAS latency (CL)
• Package
• Posted CAS additive latency (AL) – 200-pin DIMM (halogen-free) Z
• WRITE latency = READ latency - 1 tCK • Frequency/CL2
• Programmable burst lengths (BL): 4 or 8 – 1.87ns @ CL = 7 (DDR2-1066) -1GA
• Adjustable data-output drive strength – 2.5ns @ CL = 5 (DDR2-800) -80E
• 64ms, 8192-cycle refresh – 2.5ns @ CL = 6 (DDR2-800) -800
– 3ns @ CL = 5 (DDR2-667) -667
• On-die termination (ODT)
• Halogen-free Notes: 1. Contact Micron for industrial temperature
module offerings.
• Serial presence detect (SPD) with EEPROM
2. CL = CAS (READ) latency.
• Gold edge contacts
3. Not recommended for new designs.
• Dual rank

Table 1: Key Timing Parameters

Speed Industry Data Rate (MT/s) tRCD tRP tRC

Grade Nomenclature CL = 7 CL = 6 CL = 5 CL = 4 CL = 3 (ns) (ns) (ns)

-1GA PC2-8500 1066 800 667 533 400 13.125 13.125 58.125
-80E PC2-6400 800 800 533 400 12.5 12.5 57.5
-800 PC2-6400 800 667 533 400 15 15 60
-667 PC2-5300 – 667 553 400 15 15 60
-53E PC2-4200 – – 553 400 15 15 55
-40E PC2-3200 – – 400 400 15 15 55

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Products and specifications discussed herein are subject to change by Micron without notice.
 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Features

Table 2: Addressing

Parameter 1GB 2GB 4GB

Refresh count 8K 8K 8K
Row address 16K A[13:0] 16K A[13:0] 32K A[14:0]
Device bank address 4 BA[1:0] 8 BA[2:0] 8 BA[2:0]
Device configuration 512Mb (64 Meg x 8) 1Gb (128 Meg x 8) 2Gb (256 Meg x 8)
Column address 1K A[9:0] 1K A[9:0] 1K A[9:0]
Module rank address 2 S#[1:0] 2 S#[1:0] 2 S#[1:0]

Table 3: Part Numbers and Timing Parameters – 1GB Modules

Base device: MT47H64M8,1 512Mb DDR2 SDRAM
Module Module Memory Clock/ Clock Cycles
Part Number2 Density Configuration Bandwidth Data Rate (CL-tRCD-tRP)
MT16HTF12864H(I)Z-80E__ 1GB 128 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT16HTF12864H(I)Z-800__ 1GB 128 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT16HTF12864H(I)Z-667__ 1GB 128 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5

Table 4: Part Numbers and Timing Parameters – 2GB Modules

Base device: MT47H128M8,1 1Gb DDR2 SDRAM
Module Module Memory Clock/ Clock Cycles
Part Number2 Density Configuration Bandwidth Data Rate (CL-tRCD-tRP)
MT16HTF25664H(I)Z-1GA__ 2GB 256 Meg x 64 8.5 GB/s 1.87ns/1066 MT/s 7-7-7
MT16HTF25664H(I)Z-80E__ 2GB 256 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT16HTF25664H(I)Z-800__ 2GB 256 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT16HTF25664H(I)Z-667__ 2GB 256 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5

Table 5: Part Numbers and Timing Parameters – 2GB Modules

Base device: MT47H256M8,1 2Gb DDR2 SDRAM
Module Module Memory Clock/ Clock Cycles
Part Number2 Density Configuration Bandwidth Data Rate (CL-tRCD-tRP)
MT16HTF51264H(I)Z-1GA__ 4GB 512 Meg x 64 8.5 GB/s 1.87ns/1066 MT/s 7-7-7
MT16HTF51264H(I)Z-80E__ 4GB 512 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 5-5-5
MT16HTF51264H(I)Z-800__ 4GB 512Meg x 64 6.4 GB/s 2.5ns/800 MT/s 6-6-6
MT16HTF51264H(I)Z-667__ 4GB 512 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5

Notes: 1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT16HTF25664HZ-80EM1.

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 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Pin Assignments

Pin Assignments

Table 6: Pin Assignments

200-Pin DDR2 SODIMM Front 200-Pin DDR2 SODIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 VREF 51 DQS2 101 A1 151 DQ42 2 VSS 52 DM2 102 A0 152 DQ46
3 VSS 53 VSS 103 VDD 153 DQ43 4 DQ4 54 VSS 104 VDD 154 DQ47
5 DQ0 55 DQ18 105 A10 155 VSS 6 DQ5 56 DQ22 106 BA1 156 VSS
7 DQ1 57 DQ19 107 BA0 157 DQ48 8 VSS 58 DQ23 108 RAS# 158 DQ52
9 VSS 59 VSS 109 WE# 159 DQ49 10 DM0 60 VSS 110 S0# 160 DQ53
11 DQS0# 61 DQ24 111 VDD 161 VSS 12 VSS 62 DQ28 112 VDD 162 VSS
13 DQS0 63 DQ25 113 CAS# 163 NC 14 DQ6 64 DQ29 114 ODT0 164 CK1
15 VSS 65 VSS 115 S1# 165 VSS 16 DQ7 66 VSS 116 A13 166 CK1#
17 DQ2 67 DM3 117 VDD 167 DQS6# 18 VSS 68 DQS3# 118 VDD 168 VSS
19 DQ3 69 NC 119 ODT1 169 DQS6 20 DQ12 70 DQS3 120 NC 170 DM6
21 VSS 71 VSS 121 VSS 171 VSS 22 DQ13 72 VSS 122 VSS 172 VSS
23 DQ8 73 DQ26 123 DQ32 173 DQ50 24 VSS 74 DQ30 124 DQ36 174 DQ54
25 DQ9 75 DQ27 125 DQ33 175 DQ51 26 DM1 76 DQ31 126 DQ37 176 DQ55
27 VSS 77 VSS 127 VSS 177 VSS 28 VSS 78 VSS 128 VSS 178 VSS
29 DQS1# 79 CKE0 129 DQS4# 179 DQ56 30 CK0 80 CKE1 130 DM4 180 DQ60
31 DQS1 81 VDD 131 DQS4 181 DQ57 32 CK0# 82 VDD 132 VSS 182 DQ61
33 VSS 83 NC 133 VSS 183 VSS 34 VSS 84 NC 134 DQ38 184 VSS
35 DQ10 85 NC/BA21 135 DQ34 185 DM7 36 DQ14 86 NC/A142 136 DQ39 186 DQS7#
37 DQ11 VDD VDD 137 DQ35 187 VSS 38 DQ15 88 VDD 138 VSS 188 DQS7
39 VSS 89 A12 139 VSS 189 DQ58 40 VSS 90 A11 140 DQ44 190 VSS
41 VSS 91 A9 141 DQ40 191 DQ59 42 VSS 92 A7 142 DQ45 192 DQ62
43 DQ16 93 A8 143 DQ41 193 VSS 44 DQ20 94 A6 144 VSS 194 DQ63
45 DQ17 95 VDD 145 VSS 195 SDA 46 DQ21 96 VDD 146 DQS5# 196 VSS
47 VSS 97 A5 147 DM5 197 SCL 48 VSS 98 A4 148 DQS5 198 SA0
49 DQS2# 99 A3 149 VSS 199 VDDSPD 50 NC 100 A2 150 VSS 200 SA1

Notes: 1. Pin 85 is NC for 1GB and BA2 for 2GB, 4GB.

2. Pin 86 is NC for 1GB, 2GB and A14 for 4GB.

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 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Pin Descriptions

Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR2
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.

Table 7: Pin Descriptions

Symbol Type Description

Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, and MR3) is loaded during the LOAD MODE command.
CKx, Input Clock: Differential clock inputs. All control, command, and address input signals are
CK#x sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DDR2 SDRAM.
DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
S#x Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
SAx Input Serial address inputs: Used to configure the SPD EEPROM address range on the I2C
bus.
SCL Input Serial clock for SPD EEPROM: Used to synchronize communication to and from the
SPD EEPROM on the I2C bus.
CBx I/O Check bits. Used for system error detection and correction.
DQx I/O Data input/output: Bidirectional data bus.
DQSx, I/O Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the con-
DQS#x troller. Output with read data; input with write data for source synchronous opera-
tion. DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command.

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 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Pin Descriptions

Table 7: Pin Descriptions (Continued)

Symbol Type Description

SDA I/O Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on
the I2C bus.
RDQSx, Output Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD
RDQS#x MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS
is output with read data only and is ignored during write data. When RDQS is disa-
bled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled
and differential data strobe mode is enabled.
Err_Out# Output Parity error output: Parity error found on the command and address bus.
(open drain)
VDD/VDDQ Supply Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the mod-
ule VDD.
VDDSPD Supply SPD EEPROM power supply: 1.7–3.6V.
VREF Supply Reference voltage: VDD/2.
VSS Supply Ground.
NC – No connect: These pins are not connected on the module.
NF – No function: These pins are connected within the module, but provide no functional-
ity.
NU – Not used: These pins are not used in specific module configurations/operations.
RFU – Reserved for future use.

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 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Functional Block Diagram – 1GB, 2GB

Functional Block Diagram – 1GB, 2GB

Figure 2: Functional Block Diagram – 1GB, 2GB

S1#
S0#
DQS0# DQS4#
DQS0 DQS4
DM0 DM4
DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS#
DQ0 DQ DQ DQ32 DQ DQ
DQ1 DQ DQ DQ33 DQ DQ
DQ2 DQ DQ DQ34 DQ DQ
DQ3 DQ U1 DQ U14 DQ35 DQ U4 DQ U11
DQ4 DQ DQ DQ36 DQ DQ
DQ5 DQ DQ DQ37 DQ DQ
DQ6 DQ DQ DQ38 DQ DQ
DQ7 DQ DQ DQ39 DQ DQ

DQS1# DQS5#
DQS1 DQS5
DM1 DM5
DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS#
DQ8 DQ DQ DQ40 DQ DQ
DQ9 DQ DQ DQ41 DQ DQ
DQ10 DQ DQ DQ42 DQ DQ
DQ11 DQ U6 DQ U18 DQ43 DQ U8 DQ U16
DQ12 DQ DQ DQ44 DQ DQ
DQ13 DQ DQ DQ45 DQ DQ
DQ14 DQ DQ DQ46 DQ DQ
DQ15 DQ DQ DQ47 DQ DQ

DQS2# DQS6#
DQS2 DQS6
DM2 DM6
DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS#
DQ16 DQ DQ DQ48 DQ DQ
DQ17 DQ DQ DQ49 DQ DQ
DQ18 DQ DQ DQ50 DQ DQ
DQ19 DQ U2 DQ U13 DQ51 DQ U5 DQ U10
DQ20 DQ DQ DQ52 DQ DQ
DQ21 DQ DQ DQ53 DQ DQ
DQ22 DQ DQ DQ54 DQ DQ
DQ23 DQ DQ DQ55 DQ DQ

DQS3# DQS7#
DQS3 DQS7
DM3 DM7
DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS#
DQ24 DQ DQ DQ56 DQ DQ
DQ25 DQ DQ DQ57 DQ DQ
DQ26 DQ DQ DQ58 DQ DQ
DQ27 DQ U7 DQ U17 DQ59 DQ U9 DQ U15
DQ28 DQ DQ DQ60 DQ DQ
DQ29 DQ DQ DQ61 DQ DQ
DQ30 DQ DQ DQ62 DQ DQ
DQ31 DQ DQ DQ63 DQ DQ

U3 Rank 0 = U1, U2, U4–U9

BA[2/1:0] BA[2/1:0]: DDR2 SDRAM
SPD/EEPROM Rank 1 = U10, U11, U13–U18
A[13:0] A[13:0]: DDR2 SDRAM SCL SDA
RAS# RAS#: DDR2 SDRAM WP A0 A1 A2
CAS# CAS#: DDR2 SDRAM CK0 U1, U2, U6, U7
VSS SA0 SA1 VSS CK0# U13, U14, U17, U18
WE# WE#: DDR2 SDRAM
CKE0 CKE0: Rank 0 VDDSPD SPD/EEPROM
CKE1 CKE1: Rank 1 VDD DDR2 SDRAM
ODT0 ODT0: Rank 0 CK1 U4, U5, U8, U9
VREF DDR2 SDRAM CK1# U10, U11, U15, U16
ODT1 ODT1: Rank 1
VSS DDR2 SDRAM, EEPROM

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 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Functional Block Diagram – 4GB

Functional Block Diagram – 4GB

Figure 3: Functional Block Diagram – 4GB

S1#
S0#
DQS0# DQS4#
DQS0 DQS4
DM0 DM4
DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS#
DQ0 DQ DQ DQ32 DQ DQ
DQ1 DQ DQ DQ33 DQ DQ
DQ2 DQ DQ DQ34 DQ DQ
DQ3 DQ U1 DQ U14 DQ35 DQ U5 DQ U12
DQ4 DQ DQ DQ36 DQ DQ
DQ5 DQ DQ DQ37 DQ DQ
DQ6 DQ DQ DQ38 DQ DQ
DQ7 DQ DQ DQ39 DQ DQ

DQS1# DQS5#
DQS1 DQS5
DM1 DM5
DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS#
DQ8 DQ DQ DQ40 DQ DQ
DQ9 DQ DQ DQ41 DQ DQ
DQ10 DQ DQ DQ42 DQ DQ
DQ11 DQ U7 DQ U18 DQ43 DQ U9 DQ U16
DQ12 DQ DQ DQ44 DQ DQ
DQ13 DQ DQ DQ45 DQ DQ
DQ14 DQ DQ DQ46 DQ DQ
DQ15 DQ DQ DQ47 DQ DQ

DQS2# DQS6#
DQS2 DQS6
DM2 DM6
DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS#
DQ16 DQ DQ DQ48 DQ DQ
DQ17 DQ DQ DQ49 DQ DQ
DQ18 DQ DQ DQ50 DQ DQ
DQ19 DQ U2 DQ U13 DQ51 DQ U6 DQ U11
DQ20 DQ DQ DQ52 DQ DQ
DQ21 DQ DQ DQ53 DQ DQ
DQ22 DQ DQ DQ54 DQ DQ
DQ23 DQ DQ DQ55 DQ DQ

DQS3# DQS7#
DQS3 DQS7
DM3 DM7
DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS#
DQ24 DQ DQ DQ56 DQ DQ
DQ25 DQ DQ DQ57 DQ DQ
DQ26 DQ DQ DQ58 DQ DQ
DQ27 DQ U8 DQ U17 DQ59 DQ U10 DQ U15
DQ28 DQ DQ DQ60 DQ DQ
DQ29 DQ DQ DQ61 DQ DQ
DQ30 DQ DQ DQ62 DQ DQ
DQ31 DQ DQ DQ63 DQ DQ

U4 Rank 0 = U1, U2, U5–U10

BA[2:0] BA[2:0]: DDR2 SDRAM
SPD/EEPROM Rank 1 = U11–U18
A[14:0] A[14:0]: DDR2 SDRAM SCL SDA
RAS# RAS#: DDR2 SDRAM WP A0 A1 A2
CAS# CAS#: DDR2 SDRAM VSS SA0 SA1 VSS
CK0 U1, U2, U7, U8
CK0# U13, U14, U17, U18
WE# WE#: DDR2 SDRAM
CKE0 CKE0: Rank 0 VDDSPD SPD/EEPROM
CKE1 CKE1: Rank 1 VDD DDR2 SDRAM
ODT0 ODT0: Rank 0 CK1 U5, U6, U9, U10
VREF DDR2 SDRAM CK1# U11, U12, U15, U16
ODT1 ODT1: Rank 1
VSS DDR2 SDRAM, EEPROM

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 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
General Description

General Description
DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
ules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM
modules use DDR architecture to achieve high-speed operation. DDR2 architecture is
essentially a 4n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM
module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data
transfers at the I/O pins.
DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is
transmitted externally, along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR2 SDRAM device during READs and by the memory con-
troller during WRITEs. DQS is edge-aligned with data for READs and center-aligned
with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
mands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.

Serial Presence-Detect EEPROM Operation

DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the mod-
ule type and various SDRAM organizations and timing parameters. The remaining 128
bytes of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect
(WP) is connected to V SS, permanently disabling hardware write protection.

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 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Electrical Specifications

Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in the device data sheet are not implied. Exposure to abso-
lute maximum rating conditions for extended periods may adversely affect reliability.

Table 8: Absolute Maximum Ratings

Symbol Parameter Min Max Units

VDD VDD supply voltage relative to VSS –1.0 2.3 V
VIN, VOUT Voltage on any pin relative to VSS –0.5 2.3 V
II Input leakage current; Any input 0V ≤ VIN ≤ Address inputs, RAS#, CAS#, –80 80 µA
VDD; VREF input 0V ≤ VIN ≤ 0.95V; (All other WE#, BA
pins not under test = 0V) S#, CKE, ODT, CK, CK# –40 40
DM –10 10
IOZ Output leakage current; 0V ≤ VOUT; DQ and DQ, DQS, DQS# –10 10 µA
ODT are disabled
IVREF VREF leakage current; VREF = valid VREF level –32 32 µA
TA Module ambient operating temperature Commercial 0 70 °C
Industrial –40 85 °C
TC 1 DDR2 SDRAM component operating tem- Commercial 0 85 °C
perature2 Industrial –40 95 °C

Notes: 1. The refresh rate is required to double when TC exceeds 85°C.

2. For further information, refer to technical note TN-00-08: "Thermal Applications," avail-
able on Micron’s Web site.

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 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
DRAM Operating Conditions

DRAM Operating Conditions

Recommended AC operating conditions are given in the DDR2 component data sheets.
Component specifications are available on Micron's Web site. Module speed grades cor-
relate with component speed grades.

Table 9: Module and Component Speed Grades

DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade Component Speed Grade
-1GA -187E
-80E -25E
-800 -25
-667 -3
-53E -37E
-40E -5E

Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully de-
signed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level. Mi-
cron encourages designers to simulate the signal characteristics of the system's memo-
ry bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to en-
sure the required supply voltage is maintained.

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 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
IDD Specifications

IDD Specifications

Table 10: DDR2 IDD Specifications and Conditions – 1GB (Die Revision G)
Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8) com-
ponent data sheet
-80E/
Parameter Symbol -800 -667 Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD), tRAS = IDD01 576 536 mA
tRAS MIN (I ); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
DD
switching; Data bus inputs are switching
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL IDD11 656 616 mA
(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE
is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data
pattern is same as IDD4W
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; IDD2P2 112 112 mA
Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, IDD2Q2 384 352 mA
S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is IDD2N2 448 400 mA
HIGH; Other control and address bus inputs are switching; Data bus inputs are switching
Active power-down current: All device banks open; tCK Fast PDN exit MR[12] = 0 IDD3P2 288 240 mA
= tCK (IDD); CKE is LOW; Other control and address bus in- Slow PDN exit MR[12] = 1 144 144
puts are stable; Data bus inputs are floating
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), IDD3N2 528 480 mA
tRP= tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and ad-
dress bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes; BL = IDD4W1 1056 976 mA
4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus
inputs are switching
Operating burst read current: All device banks open; Continuous burst read, IOUT = IDD4R1 1016 936 mA
0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Da-
ta bus inputs are switching
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; IDD52 816 776 mA
CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs
are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus in- IDD62 112 112 mA
puts are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads; IOUT = IDD71 1256 1176 mA
0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD),
tRRD = tRRD (I ), tRCD = tRCD (I ); CKE is HIGH, S# is HIGH between valid commands;
DD DD
Address bus inputs are stable during deselects; Data bus inputs are switching

Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.

PDF: 09005aef8339ef97
htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
IDD Specifications

Table 11: DDR2 IDD Specifications and Conditions – 2GB (Die Revision H)
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
-80E/
Parameter Symbol -1GA -800 -667 Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD), IDD01 656 576 536 mA
tRAS = tRAS MIN (I ); CKE is HIGH, S# is HIGH between valid commands; Address
DD
bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = IDD11 736 656 616 mA
CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data pattern is same as IDD4W
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is IDD2P2 112 112 112 mA
LOW; Other control and address bus inputs are stable; Data bus inputs are float-
ing
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is IDD2Q2 448 384 384 mA
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, IDD2N2 544 448 384 mA
S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
are switching
Active power-down current: All device banks open; Fast PDN exit MR[12] = 0 IDD3P2 368 320 240 mA
tCK = tCK (IDD); CKE is LOW; Other control and address Slow PDN exit MR[12] = 1 160 160 160
bus inputs are stable; Data bus inputs are floating
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS IDD3N2 640 528 480 mA
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Oth-
er control and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes; IDD4W1 1216 1056 976 mA
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-
ing; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read, IDD4R1 1176 1016 936 mA
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (I ); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
DD
puts are switching; Data bus inputs are switching
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) in- IDD52 1296 1216 1176 mA
terval; CKE is HIGH, S# is HIGH between valid commands; Other control and ad-
dress bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address IDD62 112 112 112 mA
bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads; IDD71 1816 1736 1536 mA
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC
= tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are stable during deselects; Data bus inputs
are switching

Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks
in IDD2P (CKE LOW) mode.

PDF: 09005aef8339ef97
htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
IDD Specifications

2. Value calculated reflects all module ranks in this operating condition.

Table 12: DDR2 IDD Specifications and Conditions – 2GB (Die Revision M)
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
-80E/
Parameter Symbol -1GA -800 -667 Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD), IDD01 680 600 560 mA
tRAS = tRAS MIN (I ); CKE is HIGH, S# is HIGH between valid commands; Address
DD
bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = IDD11 760 680 640 mA
CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data pattern is same as IDD4W
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is IDD2P2 160 160 160 mA
LOW; Other control and address bus inputs are stable; Data bus inputs are float-
ing
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is IDD2Q2 448 384 384 mA
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus in-
puts are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, IDD2N2 544 448 384 mA
S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
are switching
Active power-down current: All device banks open; Fast PDN exit MR[12] = 0 IDD3P2 512 480 448 mA
tCK = tCK (I ); CKE is LOW; Other control and address
DD Slow PDN exit MR[12] = 1 320 320 320
bus inputs are stable; Data bus inputs are floating
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS IDD3N2 640 528 480 mA
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Oth-
er control and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes; IDD4W1 1240 1080 1000 mA
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-
ing; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read, IDD4R1 1200 1040 960 mA
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (I ); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
DD
puts are switching; Data bus inputs are switching
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) in- IDD52 1400 1320 1280 mA
terval; CKE is HIGH, S# is HIGH between valid commands; Other control and ad-
dress bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address IDD62 112 112 112 mA
bus inputs are floating; Data bus inputs are floating

PDF: 09005aef8339ef97
htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
IDD Specifications

Table 12: DDR2 IDD Specifications and Conditions – 2GB (Die Revision M) (Continued)
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
-80E/
Parameter Symbol -1GA -800 -667 Units
Operating bank interleave read current: All device banks interleaving reads; IDD71 1840 1760 1560 mA
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC
= tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are stable during deselects; Data bus inputs
are switching

Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.

Table 13: DDR2 IDD Specifications and Conditions – 4GB (Die Revision C)
Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) com-
ponent data sheet
-80E/
Parameter Symbol -1GA -800 -667 Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD), IDD01 776 696 656 mA
tRAS = tRAS MIN (I ); CKE is HIGH, S# is HIGH between valid commands; Address
DD
bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = IDD11 856 784 736 mA
CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD
(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data pattern is same as IDD4W
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is IDD2P2 192 192 192 mA
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is IDD2Q2 560 480 400 mA
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, IDD2N2 640 560 480 mA
S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
are switching
Active power-down current: All device banks open; Fast PDN exit MR[12] = 0 IDD3P2 400 400 400 mA
tCK = tCK (I ); CKE is LOW; Other control and address
DD Slow PDN exit MR[12] = 1 224 224 224
bus inputs are stable; Data bus inputs are floating
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX IDD3N2 960 800 720 mA
(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes; IDD4W1 1376 1136 976 mA
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-
ing; Data bus inputs are switching

PDF: 09005aef8339ef97
htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Serial Presence-Detect

Table 13: DDR2 IDD Specifications and Conditions – 4GB (Die Revision C) (Continued)
Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) com-
ponent data sheet
-80E/
Parameter Symbol -1GA -800 -667 Units
Operating burst read current: All device banks open; Continuous burst read, IDD4R1 1376 1136 976 mA
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP
= tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are switching; Data bus inputs are switching
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) in- IDD52 1496 1456 1416 mA
terval; CKE is HIGH, S# is HIGH between valid commands; Other control and ad-
dress bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address IDD62 192 192 192 mA
bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads; IDD71 1936 1856 1696 mA
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC
= tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are stable during deselects; Data bus inputs
are switching

Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.

Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.

Table 14: SPD EEPROM Operating Conditions

Parameter/Condition Symbol Min Max Units

Supply voltage VDDSPD 1.7 3.6 V
Input high voltage: logic 1; All inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V
Input low voltage: logic 0; All inputs VIL –0.6 VDDSPD × 0.3 V
Output low voltage: IOUT = 3mA VOL – 0.4 V
Input leakage current: VIN = GND to VDD ILI 0.1 3 µA
Output leakage current: VOUT = GND to VDD ILO 0.05 3 µA
Standby current ISB 1.6 4 µA
Power supply current, READ: SCL clock frequency = 100 kHz ICCR 0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 kHz ICCW 2 3 mA

Table 15: SPD EEPROM AC Operating Conditions

Parameter/Condition Symbol Min Max Units Notes

SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1
Time bus must be free before a new transition can start tBUF 1.3 – µs

PDF: 09005aef8339ef97
htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Serial Presence-Detect

Table 15: SPD EEPROM AC Operating Conditions (Continued)

Parameter/Condition Symbol Min Max Units Notes

Data-out hold time tDH 200 – ns
SDA and SCL fall time tF – 300 ns 2
SDA and SCL rise time tR – 300 ns 2
Data-in hold time tHD:DAT 0 – µs
Start condition hold time tHD:STA 0.6 – µs
Clock HIGH period tHIGH 0.6 – µs
Noise suppression time constant at SCL, SDA inputs tI – 50 ns
Clock LOW period tLOW 1.3 – µs
SCL clock frequency tSCL – 400 kHz
Data-in setup time tSU:DAT 100 – ns
Start condition setup time tSU:STA 0.6 – µs 3
Stop condition setup time tSU:STO 0.6 – µs
WRITE cycle time tWRC – 10 ms 4

Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to
pull-up resistance, and the EEPROM does not respond to its slave address.

PDF: 09005aef8339ef97
htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Module Dimensions – 1GB, 2GB

Module Dimensions – 1GB, 2GB

Figure 4: 200-Pin DDR2 SODIMM – 1GB, 2GB

Front view 3.8 (0.15)

67.75 (2.67) MAX
67.45 (2.65)

U3
2.0 (0.079) R
(2X) U1 U2 U4 U5

30.15 (1.187)
1.80 (0.071)
29.85 (1.175)
(2X)
U6 U7 U8 U9 20.0 (0.787)
TYP

6.0 (0.236)
TYP
0.5 (0.0197) R 1.1 (0.043)
Pin 1 Pin 199
0.9 (0.035)
2.0 (0.079)
0.45 (0.018) 0.6 (0.024)
TYP
TYP TYP
16.25 (0.64)
TYP
63.6 (2.504)
TYP

Back view

U10 U11 U13 U14

U15 U16 U17 U18

3.5 (0.138)
TYP
Pin 200 4.2 (0.165) Pin 2
TYP
47.4 (1.87)
TYP 11.4 (0.45)
TYP

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for ad-
ditional design dimensions.

PDF: 09005aef8339ef97
htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
 1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Module Dimensions – 4GB

Module Dimensions – 4GB

Figure 5: 200-Pin DDR2 SODIMM – 4GB

Front view 3.8 (0.15)

67.75 (2.67) MAX
67.45 (2.65)

2.0 (0.079) R U4
(2X) U1 U2 U5 U6

30.15 (1.187)
1.80 (0.071)
29.85 (1.175)
(2X)
U7 U8 U9 U10 20.0 (0.787)
TYP

6.0 (0.236)
TYP
0.5 (0.0197) R 1.1 (0.043)
Pin 1 Pin 199
0.9 (0.035)
2.0 (0.079)
0.45 (0.018) 0.6 (0.024)
TYP
TYP TYP
16.25 (0.64)
TYP
63.6 (2.504)
TYP

45° 4X Back view

U11 U12 U13 U14

U15 U16 U17 U18

3.5 (0.138)
TYP
Pin 200 4.2 (0.165) Pin 2
TYP
47.4 (1.87)
TYP 11.4 (0.45)
TYP

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for ad-
ditional design dimensions.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

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htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.