A Report on

Design of IMC based-PID controller for Sepic converter

In the fulfilment of Internship
Semester 6
Bachelors of Technology
In
Electronics and Instrumentation Engineering

By
Dharani Illa
Roll No:-218297602006

Under the supervision of

Dr. G. UDAY BHASKAR BABU
Associate Professor
Department of Chemical Engineering
National Institute of Technology, Warangal
Telangana, INDIA - 506004
 Contents
1 Introduction 3
1.1 The Need for Versatile Voltage Regulation 4
2 System Description and Control Design 4
2.1 Steady-State Specifications 4
2.2 Transient Specifications 5
2.3 Additional Considerations: 5
3 FOIMC structure and design procedure 5
3.1 Fractional filter IMC PID Controller design 5
3.2 Controller Design 7
4 Simulation studies 8
5 Conclusion 10

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1 Introduction
The ever-growing demand for portable and efficient electronics necessitates robust power
management solutions. Within this domain, DC-DC converters play a crucial role in regulating
voltage levels to meet specific device requirements. While boost converters and buck
converters offer established solutions for voltage manipulation, the SEPIC converter (Single
Ended Primary Inductance Converter) emerges as a more versatile option.
The SEPIC converter stands out for its ability to deliver an output voltage that is either higher,
lower, or equal to the input voltage. This flexibility surpasses the limitations of boost and buck
converters, which are restricted to voltage increase and decrease, respectively. This
introductory chapter delves into the key concepts and applications of SEPIC converters,
highlighting their unique advantages in various power management scenarios.

The Single Ended Primary Inductance Converter (SEPIC) offers a versatile solution for DC-
DC power conversion. Unlike traditional boost and buck converters, the SEPIC converter can
achieve an output voltage that is either higher, lower, or equal to the input voltage. This report
delves into the operating principle, key components, and advantages of SEPIC converters.
The working principle utilizes two inductors, a capacitor, and a switching element to transfer
energy and control the output voltage. The inductors store energy, while the capacitor acts as a
bridge between them. The switching element, typically a MOSFET, regulates the energy flow
based on a control signal.
SEPIC converters offer several advantages:
Variable Output Voltage: They can provide a wider range of output voltages compared to boost
or buck converters alone.
Non-Inverting Output: The output voltage maintains the same polarity as the input, making it
suitable for specific applications.
Simple Design: The circuit topology is relatively straightforward, requiring minimal active
components.
Low Noise Operation: SEPIC converters operate with minimal electrical noise, making them
ideal for noise-sensitive applications.
These features make SEPIC converters valuable in various applications, including:
Battery-powered devices: Regulating voltage from fluctuating battery levels.
LED Drivers: Providing the specific voltage needed for diverse LED configurations.
Solar Power Systems: Boosting voltage from solar panels to match battery storage
requirements.

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Distributed Power Systems: Regulating voltage in complex power delivery networks.
This report provides a foundational understanding of SEPIC converters. Further exploration of
resources like design guides and application notes offers deeper insights for practical
implementation.
1.1 The Need for Versatile Voltage Regulation
Modern electronic devices rely on a plethora of integrated circuits (ICs) and other components,
each with specific voltage requirements. Battery-powered devices, for instance, encounter
fluctuating voltage levels as the battery discharges. Similarly, solar power systems produce
variable output voltage depending on sunlight intensity. In such cases, regulating voltage
becomes crucial to ensure optimal device operation and prevent damage.
Limitations of Traditional DC-DC Converters:
The SEPIC converter combines elements of both boost and buck converters to achieve its
versatile output voltage capability. It employs a unique circuit topology consisting of the
following key components:
Inductors (L1 & L2): These passive components store energy during the switching cycle.
Coupling Capacitor (C1): This capacitor connects the two inductors and facilitates energy
transfer between them.
Input/Output Capacitors (Cin & Cout): These capacitors filter the input and output voltages,
respectively, minimizing ripple and ensuring stable power delivery.
Switching Element (MOSFET): This active component, typically a Metal-Oxide-
Semiconductor Field-Effect Transistor (MOSFET), controls the flow of energy within the
circuit by turning on and off based on a control signal.
Through a carefully orchestrated switching pattern of the MOSFET, the SEPIC converter
manipulates the energy stored in the inductors and transferred through the coupling capacitor.
This manipulation ultimately determines the output voltage, allowing it to be higher, lower, or
equal to the input voltage.
2 System Description and Control Design
The controller for a SEPIC converter plays a crucial role in maintaining a stable and well-
regulated output voltage despite variations in input voltage or load current. Here's a breakdown
of the key design requirements for the controller:

2.1 Steady-State Specifications:

High DC Gain (Error Amplifier): This minimizes the steady-state error between the reference
voltage (desired output) and the actual output voltage. Aim for a DC gain exceeding 80 dB. A

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higher gain ensures even small errors get amplified significantly, leading to corrective action
by the PWM.

High Common-Mode Rejection Ratio (CMRR): This rejects noise on the input voltage
reference. A high CMRR (again, exceeding 80 dB) is crucial to prevent noise from affecting
the error voltage and causing unwanted output voltage variations.

2.2 Transient Specifications:

Fast Response to Error Voltage Changes (PWM): The PWM should respond quickly to changes
in the error voltage to ensure swift correction of output voltage deviations. This translates to
faster settling times after disturbances and better overall regulation performance.

Fast Gate Driver: Enables rapid switching of the MOSFET, allowing for efficient response to
sudden changes in input voltage or load current. Minimize dead time (when neither MOSFET
nor diode conducts) and switching losses for better converter efficiency.

2.3 Additional Considerations:

Bandwidth Selection (Compensation Network): The compensation network bandwidth needs

to be carefully chosen. A wider bandwidth allows for faster response to input voltage changes
and load variations but can lead to instability. Conversely, a narrower bandwidth improves
stability but can slow down transient response. Finding the optimal balance is essential.
Protection Features (Optional): Depending on your application, the controller might require
features like:
Current Limiting: Protects against overload conditions.
Soft-Start: Reduces inrush current during startup, minimizing stress on components.
Overvoltage and Undervoltage Protection: Ensures safe operation by protecting against
excessive output voltage or voltage dips.
Controller Selection:
Integrated Control ICs: Many manufacturers offer dedicated SEPIC converter control ICs that
integrate the error amplifier, PWM generator, gate driver, and sometimes additional protection
features. These can simplify design, reduce component count, and offer pre-defined control
characteristics.
Microcontrollers: For complex control algorithms or features beyond basic regulation,
microcontrollers can be used. They offer more flexibility for implementing advanced control
techniques like load current limiting and loop gain scheduling.

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3. FOIMC structure and design procedure
3.1 Fractional filter IMC PID Controller design
A simple feedback closed-loop system as shown in Fig. is considered in the present study
instead of a feedback loop with filter as considered by literature [1].
The IMC scheme and feedback control loop with internal blocks are shown in Figure 1,
where G(s), representing process, process model, IMC controller and transfer function of the
traditional controller.

Let r, y, u, and d be the set point, controlled variable, control input and disturbance
respectively. The controller design using IMC method is given as follows:
1) Decompose the model into non-invertible and invertible parts
𝐺˜ (𝑠) = 𝐺˜ + (𝑠) ∗ 𝐺˜ – (𝑠) (1)

Where, G+(s) is non-invertible contains all time delays and unstable zeros. G-s is invertible
and contains minimum phase elements.
2) The IMC controller is given by

𝐺IM f(s) where f(s) is the IMC filter. (2)

(𝑠) = G˜—
C (s)

3) The equivalent controller feedback is

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 𝐺C(𝑠) 𝐺IMC(𝑠) (3)
=
1 − 𝐺IMC(𝑠) ∗ 𝐺˜ (𝑠)

3.2 Controller Design

Considering process as in literature
2.371𝑠 + 2.508𝑒06
𝐺(𝑠) = (4)
𝑠2 + 341.2𝑠 + 3.786𝑒05

Equation (4) shows the presence and a complex conjugate pole pair.

2.371𝑠 + 2.508𝑒06 (5)

𝐺˜ – (𝑠) =
𝑠2 + 341.2𝑠 + 3.786𝑒05

Considering second order integer and fractional filter

1 (6)
𝑓ƒ(𝑠) = α 2
(𝜆𝑠 + 1)

𝑓i(𝑠) = 1 (7)
2
(𝑠 + 1)

From the equation (5) 𝐺IMC F(𝑠) takes the form for filter (6) ;

𝑠2 + 341.2𝑠 + 3.786𝑒05
∗ 1 (8)
𝐺IMCƒ(𝑠) 2.371𝑠 + 2.508𝑒06 α
(𝜆𝑠 + 1) 2
=

Similarly, the equation (5) 𝐺IMC I(𝑠) takes the form for filter (7):
𝑠2 + 341.2𝑠 + 1 (9)
𝐺IMCi(𝑠) 3.786𝑒05 2
∗ (𝑠 + 1)
Now, = 2.371𝑠 + 2.508𝑒06

With the help of (3) controller for (8) can be written as:

𝑠2 + 341.2𝑠 + 3.786𝑒05 (10)

𝐺Cƒ(𝑠) =
(2.371𝑠 + 2.508𝑒06)((𝑠α + 1)2 − 1)

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Similarly, with the help of (9) controller can be written as:

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 𝐺Ci(𝑠) = 𝑠α(𝑠 + 341.2𝑠 + (11)
3.786𝑒05) (2.371𝑠 +
2.508𝑒06)(𝜆α)

4 Simulation studies:

In this work, simulations were performed for a SEPIC converter using Simulink from
MATLAB. The plant model was based on a small-signal model obtained from reference
[Reference for SEPIC small-signal model].
Two types of tests were conducted: set point and regulatory.
Set point: Step-up reference voltage given a step of 15V to analyse the system's response for
output voltage.
Regulatory Tests:
Manipulated variable (switching frequency) disturbance: A disturbance of magnitude 0.1 is
provided at input of plant to simulate the disturbance in manipulated variable.
Load regulation: Disturbance is applied at output voltage of magnitude 2V to simulate varying
load conditions.

Fig(1) 15 V Step response for controller (10 and 11)

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 Fig (2) Input disturbance rejection for controller (10 & 11)

Fig (3) Output disturbance rejection for controller (10 & 11)
Measurement Blocks: Include scopes or measurement blocks to monitor the output voltage,
inductor currents, and capacitor voltages. This will allow you to observe how the SEPIC
converter responds to the load change.

Run Simulation: Run the simulation and analyse the results. You should see the output voltage
initially settle at a desired level. When the disturbance voltage source is activated, the output
voltage will experience a transient dip. However, if your control system (e.g., a PI controller
adjusting the PWM duty cycle) is properly designed, the output voltage should recover and
regulate back to the desired level.

Table1: Performance analysis of servo response for controller (10,11)

Step change 0 →15 15 → 19 15 → 13

IAE Integer 0.1213 0.0323 0.0161
Fractional 0.0983 0.0257 0.0136
ISE Integer 1.3064 0.0929 0.0237
Fractional 1.0315 0.0732 0.0188
TV Integer 0.4529 0.1207 0.0604
Fractional 0.4529 0.1207 0.0604

1
0
 0S (%) Integer 0.3950 0.1465 0.06
Fractional 2.4607 0.2603 0.3
ST (sec) Integer 0.0202 0.0155 0.0832
Fractional 0.0220 0.0092 0.0087

Table:2 Performance analysis of disturbance rejection for controller.

Disturbance Input disturbance (0.1) Output disturbance

IAE Integer 0.005745297 0.000683789

Fractional 0.005263707 0.011272374
ISE Integer 1.3097722 0.9853157
Fractional 1.1335354 0.9148978
TV integer 1.3097722 0.4728709
Fractional 0.4728697 0.5132615
0S (%) Integer 5.8671655 18.238838
Fractional 5.6521137 13.333814
ST (sec) Integer 0.0085925 0.0123485
Fractional 0.0081802 0.0068902

5 Conclusion:
It can be concluded from the quantitative comparison of simulation analysis of the controller's
effectiveness in regulating output voltage and rejecting disturbances, showcasing the
comparative performance between integer and fractional filter implementations. The fractional
filter performance for servo response with different step is significantly better than integer in
all step cases, with reduced settling time but at the cost of increase overshoot but still within
1% of margin. Also disturbance rejection performance of fractional is better than the integer
for input disturbance case but result is inconclusive for output disturbance.

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Reference

[1] Padhi, B. K., & Narain, A. (2013). controller design for SEPIC converter using model order
reduction. In ASAR International Conference (pp. 51-56).

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