LIST OF EXPERIMENT

Sr. Name of Experiment

No.
1 Familiarization with Digital Logic Trainer IDL-400 (Digital Logic Kit), Digital ICs and
Verify the Truth Tables of logic gates for positive logic.
2 Implement basic logic gates using universal logic gates (NAND & NOR) and verify the
Truth Tables.
3 Simplification of Boolean function using K-Map

4
Design of Combinational Code Converter circuits

5
To design and test various adder and subtractor circuits

6
Implementation of the various logic circuits of Decoders and Priority Encoder

7
Design and implementation of Boolean function with Multiplexers and De-multiplexers

8
Implementation of BCD-to-Seven Segment Decoder

9
To construct, test and investigate the operation of various latches and flip-flops

10 a) Design of Synchronous binary and BCD Counters (IC#74293)

b) Design of bcd counter with parallel load (IC#74160)
11 a) Design of Synchronous BCD Up-Down Counter (IC#74190)
b) Design of shift register with parallel load (IC#74195)
12

13

14
Lab No. 01
Familiarization with Digital Logic Trainer IDL-400 (Digital Logic Kit),
Digital ICs and Verify the Truth Tables of logic gates for positive logic

Objective:
 To get familiar with the usage of the available lab equipment.
 To get familiar with Prototyping board (breadboard)
 To describe and verify the operation for the AND, OR, NOT, NAND, NOR,
XOR gates.
 To study the representation of these functions by truth tables, logic diagrams
and Boolean algebra
 To Introduce a basic knowledge in integrated circuit devices operation
 To practice how to build a simple digital circuit using ICs and other digital
components.
 Learn how to Wire a circuit

Apparatus/ Equipment Required:

 Prototyping board (breadboard)

 DC Power Supply 5V Battery
 Light Emitting Diode (LED)
 Digital ICs: 7404: Hex Inverter
7408: Quad 2 input AND
7432: Quad 2 input OR
7400: Quad 2 input NAND
7402: Quad 2 input NOR
7486: Quad 2 input EXOR
 Logic Probe
 Digital Logic Trainer IDL-400
 Connecting Wires

Digital Logic Trainer IDL-400

IDL-400 Logic Trainer is a device which is used to study interaction of different logic and
universal gates.
“A”
Section A comprises of “POWER SWITCH” it is top left side of trainer. The function of this
switch is to use OFF or ON the power.

“B”
Section B comprises of “SHORT CIRCUIT INDICATOR”. The bulb of this section glows when
the circuit is short.

“C”
Section C consists of “8 BIT LED OUTPUT INDICATOR “. The bulb in this section glows
when there is logic 1 and remains off when there is logic 0.

“D”
Section D consists of “AND GATES”. It is a basic combinational logic device where all inputs
must b high for the output to be high.

“E”
Section E comprises of “OR GATES” It is a basic combination logic device where the output
goes high when any or two input will be high.
“F”
Section F consists of “NAND GATES”. It is a basic combinational logic device where all inputs
must be high for output to be low. A not and circuit. It is invert of AND GATE.

“G”
Section G consists of “NOR GATES” it is a basic combinational logic device where all inputs
must be low for output to be high. A NOT OR circuit. It is an invert of OR. Its meaning No OR.

“H”
Section H consists of “XOR GATES” it is basic combinational logic device where an odd
number of high inputs generates a high output.

“I”
Section I consists of “NOT GATES” it is a basic combinational logic device where the output is
always the opposite from the input. It is also called an inverter.

“J”
Section J consists of “VOLTAGE SECTION” one port is of +5V, the other is for ground
connection and the third is of -5V.
Also Section J consists of “VOLTAGE SECTION” one port is of +15V, the other is for ground
connection and the third is of -15V.

“L”
Section L consists of PULSE. It can be generator a pulse of 1 second, 0.1 second and 0.01
second.

“M”
Section M consists of DATA SWITCHES. There are four data switches in this trainer and have
four there test point in their correspondence.

“N”
Section N consists of “SOLDER LESS BREADBOARD OR PROTO BOARD” It is consisting
of so many holes.

Black Line on Proto Board

Black line shows that all the holes (test points) on below of this line are short circuit.

Red Line on Proto Board:

Red Line shows that all the holes (test points) above this line are short circuit.
Pin Diagrams:

Not Gate: IC 7404(HEX Inverter)

14 Pin
Supply voltage :5V

AND Gate: IC 7408

14 Pin
Quad 2 input AND Gate
Supply voltage :5V

OR Gate: IC 7432
14 Pin
Quad 2 input OR Gate
Supply voltage :5V

NAND Gate: IC 7400

14 Pin
Quad 2 input NAND Gate
Supply voltage :5V

NOR Gate: IC 7402

14 Pin
Quad 2 input NOR Gate
Supply voltage :5V
 EXOR Gate: IC 7486
14 Pin
Quad 2 input EXOR Gate
Supply voltage :5V

Theory:
A Digital Logic Gate is an electronic device that makes logical decisions based on the different
combinations of digital signals present on its inputs. Logic gates are the building blocks of
digital circuits. Combinations of logic gates form circuits designed with specific tasks in mind.
They are fundamental to the design of computers. Digital logic using transistors is often referred
as Transistor-Transistor Logic or TTL gates. These gates are the AND, OR, NOT, NAND,
NOR, EXOR and EXNOR gates.
AND Gate: A multi-input circuit in which the output is 1 only if all inputs are 1.The symbolic
representation of the AND gate is:

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high.
A dot (.) is used to show the AND operation i.e. A.B.

OR gate: A multi-input circuit in which the output is 1 when any input is 1.

The symbolic representation of the OR gate is shown:

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are
high. A plus (+) is used to show the OR operation.
NOT gate: The output is 0 when the input is 1, and the output is 1 when the
input is 0. The symbolic representation of an inverter is:

The NOT gate is an electronic circuit that produces an inverted version of the input at its output.
It is also known as an inverter. If the input variable is A, the inverted output is known as NOT
A. This is also shown as A', or A with a bar over the top, as shown at the outputs.
NAND gate: AND followed by INVERT. It is also known as universal gate. The symbolic
representation of the NAND gate is:

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs
of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a
small circle on the output. The small circle represents inversion.

NOR gate: OR followed by inverter. It is also known as universal gate. The symbolic
representation is:

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of
all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle
on the output. The small circle represents inversion.

EXOR gate: The output of the Exclusive –OR gate, is 0 when it’s two inputs are the same and
its output is 1 when its two inputs are different. It is also known as Anti-coincidence gate.

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its
two inputs are high. An encircled plus sign ( ) is used to show the EOR operation.

Procedure:

1. Collect the components necessary to accomplish this experiment.

2. Plug the IC chip into the breadboard.
3. Connect the supply voltage and ground lines to the chips. PIN7 = Ground
and PIN14 = +5V.
4. According to the pin diagram of each IC mentioned above, wire only one
gate to verify its truth table.
5. Connect the inputs of the gate to the input switches of the LED.
6. Connect the output of the gate to the output LEDs.
7. Once all connections have been done, turn on the power switch of the
breadboard
8. Operate the switches and fill in the truth table ( Write "1" if LED is ON and
 "0" if LED is OFF Apply the various combination of inputs according to the truth table and
observe the condition of Output LEDs.
9. Repeat the above steps 1 to 5 for all the ICs.

Observation Table:
LED ON (RED light): Logic 1
LED OFF (Green Light): Logic 0
Input variables: A,B
Output variable: Y
AND OR NOT NAND NOR EXOR
A B GATE(A.B) GATE(A+B) GATE(A’ GATE(A.B’ GATE(A+B’) GATE(A+B)
) )

Table 1.1: verification of Logic Gates

Results and Analysis:

NOT Gate: When logic 1 is applied to one of NOT gate of 7404 IC, then output becomes zero.
When input LED is ON (RED), the output LED become OFF (Green) vice versa.

OR Gate: The output of an OR gate is a 1 if one or the other or both of the inputs are 1, but a 0
if both inputs are 0. When one or the other or Both of the input LEDS are ON (RED Light), then
output LED is ON(RED) otherwise Output LED is OFF (Green Light)

AND Gate: The output of an AND gate is only 1 if both its inputs are 1. For all other possible
inputs, the output is 0. When both the LEDS are On, then output LED is ON (RED Light)
otherwise Output LED is OFF.

NOR Gate: The output of the NOR gate is a 1 if both inputs are 0 but a 0 if one or the other or
both the inputs are 1.

NAND Gate: The output of the NAND gate is a 0 if both inputs are 1 but a 1 if one or the
other or both the inputs are 0.

EXOR gate: The output of the XOR gate is a 1 if either but not both inputs are 1 and a 0 if the
inputs are both 0 or both 1.

Lab Task:
1) What are logic gates?
Ans:

2) What is the difference between Positive Logis and negative Logic?

 Ans:

3) Draw EX-OR gate using NAND and NOR gate.

Ans:

4) Why NOR gate and NAND gate called "Universal logic gate"?
Ans:

Conclusion:
Lab No. 02
Implement basic logic gates using universal logic gates (NAND&NOR) and verify
the Truth Tables

Objective:
 To learn about the Universal gates - NAND and NOR.
 To implement NOT, AND, and OR gates using NAND gates only.
 To implement NOT, AND, and OR gates using NOR gates only.
 Equivalent gates.
 Two-level digital circuit implementations using universal gates only.
 Two-level digital circuit implementations using other gates.

Apparatus Required:
 Prototyping board (breadboard)
 DC Power Supply 5V Battery
 Light Emitting Diode (LED)
 Digital ICs: 7400: Quad 2 input NAND
7402: Quad 2 input NOR
 Logic Probe
 Digital Logic Trainer IDL-400

Pin Diagram:

NAND Gate: IC 7400

14 Pin
Quad 2 input NAND Gate
Supply voltage :5V

NOR Gate: IC 7402

14 Pin
Quad 2 input NOR Gate
Supply voltage :5V

Fig 2.1: Pin diagrams of NAND & NOR gates

NAND Gate:

The NAND gate represents the complement of the AND operation. Its name is an abbreviation
of NOT AND.
The graphic symbol for the NAND gate consists of an AND symbol with a bubble on the output,
denoting that a complement operation is performed on the output of the AND gate.

The graphic symbol and the truth table of NAND gate is shown in the figure below,

Fig 2.2: Graphic symbol & Truth Table of NAND gate

The truth table clearly shows that the NAND operation is the complement of the AND.

NOR Gate:

The NOR gate represents the complement of the OR operation. Its name is an abbreviation of
NOT OR.
The graphic symbol for the NOR gate consists of an OR symbol with a bubble on the output,
denoting that a complement operation is performed on the output of the OR gate. The graphic
symbol and the truth table of NOR gate is shown in the figure below,

Fig 2.3: Graphic symbol & Truth Table of NOR gate

The truth table clearly shows that the NOR operation is the complement of the OR.

Universal Gates:
A universal gate is a gate which can implement any Boolean function without need to use any
other gate type.
The NAND and NOR gates are universal gates.
In practice, this is advantageous since NAND and NOR gates are economical and easier to
fabricate and are the basic gates used in all IC digital logic families.

In fact, an AND gate is typically implemented as a NAND gate followed by an inverter not the
other way around!!

Likewise, an OR gate is typically implemented as a NOR gate followed by an inverter not the
other way around!!

Procedure:

NAND Gate is a Universal Gate:

To prove that any Boolean function can be implemented using only NAND gates, we will show
that the AND, OR, and NOT operations can be performed using only these gates.

Implementing an Inverter Using only NAND Gate

The figure shows two ways in which a NAND gate can be used as an inverter (NOT gate).

1. All NAND input pins connect to the input signal A gives an output A’.

2. One NAND input pin is connected to the input signal A while all other input pins are
connected to logic 1. The output will be A’.

Fig 2.4: NOT gate Implementation using NAND gate

Implementing AND using only NAND Gates

An AND gate can be replaced by NAND gates as shown in the figure (The AND is replaced by
a NAND gate with its output complemented by a NAND gate inverter).
 Fig 2.5: AND gate Implementation using NAND gate

Implementing OR using only NAND Gates

An OR gate can be replaced by NAND gates as shown in the figure (The OR gate is replaced by
a NAND gate with all its inputs complemented by NAND gate inverters).

Fig 2.6: OR gate Implementation using NAND gate

Thus, the NAND gate is a universal gate since it can implement the AND, OR and NOT
functions.

NOR Gate is a Universal Gate:

To prove that any Boolean function can be implemented using only NOR gates, we will show
that the AND, OR, and NOT operations can be performed using only these gates.

Implementing an Inverter Using only NOR Gate:

The figure shows two ways in which a NOR gate can be used as an inverter (NOT gate).

1. All NOR input pins connect to the input signal A gives an output A’.

2. One NOR input pin is connected to the input signal A while all other input pins are connected
to logic 0. The output will be A’.

Fig 2.7: NOT gate implementation using NOR Gate

Implementing OR Using only NOR Gates

An OR gate can be replaced by NOR gates as shown in the figure (The OR is replaced by a
NOR gate with its output complemented by a NOR gate inverter).

Fig 2.9: OR gate implementation using NOR gate

Implementing AND Using only NOR Gates

An AND gate can be replaced by NOR gates as shown in the figure (The AND gate is replaced
by a NOR gate with all its inputs complemented by NOR gate inverters).

Fig 2.10: AND gate implementation using NOR gate

Thus, the NOR gate is a universal gate since it can implement the AND, OR and NOT functions.
Equivalent Gates:
The shown figure summarizes important cases of gate equivalence. Note that bubbles indicate a
complement operation (inverter).

A NAND gate is equivalent to an inverted-input OR gate.

Fig 2.11: Equivalent circuit of NAND gate

An AND gate is equivalent to an inverted-input NOR gate.

Fig 2.12: Equivalent circuit of AND gate

A NOR gate is equivalent to an inverted-input AND gate

Fig 2.13: Equivalent circuit of NOR gate

An OR gate is equivalent to an inverted-input NAND gate.

Fig 2.14: Equivalent circuit of OR gate

Two-Level Implementations:

We have seen before that Boolean functions in either SOP or POS forms can be implemented
using 2-Level implementations.

For SOP forms AND gates will be in the first level and a single OR gate will be in the second
level.

For POS forms OR gates will be in the first level and a single AND gate will be in the second
level.

Note that using inverters to complement input variables is not counted as a level.
Lab Task: Using a single 7400 IC, connect a circuit that produces a two input XOR.
Conclusion:
Lab No. 03
Simplification of Boolean function using K-Map
Aim: - Implement Boolean function F=xy+x’y’+y’z using AOI logic
Simplify the Boolean function F(w, x, y, z) = Σ (0, 1,2,4,5,6,8,9, 12, 13, 14) using 4-variable K-
Map, implement it and verify it using truth-table and prove that simplified circuit behaves
exactly like the original circuit.

Apparatus Required:

THEORY:
The complexity of the digital logic gates that implement a Boolean function is directly related to
the complexity of the algebraic expression from which the function is implemented. Although
the truth table representation of a function is unique, expressed algebraically, it can appear in
many different forms. Boolean functions may be simplified by algebraic means. However, this
procedure of minimization is awkward because it lacks specific rules to predict each succeeding
step in the manipulative process. The map method provides a simple straightforward procedure
for minimizing Boolean functions. This method may be regarded either as a pictorial form of a
truth table or as an extension of the Venn diagram. The map method, first proposed by Veitch
and modified by Karnaugh, is also known as the "Veitch diagram" or the "Karnaugh map."

A binary variable can take the value of 0 or 1. A Boolean function is an expression formed with
binary variables, the two binary operators OR and AND, and unary operator NOT, parentheses,
and an equal sign. For a given value of the variables, the function can be either 0 or 1.
Boolean function represented as an algebraic expression may be transformed from an algebraic
expression into a logic diagram composed of AND, OR, and NOT gates. Every Boolean
function can be realized by a And-Or-Not gates i.e. using AOI logic.
Logic Diagram - (For F=xy+x’y’+y’z)

Procedure:
1. Connect the trainer kit to ac power supply.
2. Verify the gates and make connections as per circuit diagram-A.
3. Apply various input combinations and observe output for each one.
4. Verify the truth table for each input/ output combination.
5. Repeat the process for circuit diagram-B.
6. Switch off the ac power supply.

Truth Table:
Procedure:

(i) Simplify the given Boolean function using 4-variable K-Map

(ii) Implement simplified Boolean function using logic gates.
(iii) Verify the gates and make connections as per the logic diagram.
(iv) Connect Pin-14 of all ICs to +5V and Pin-7 to ground.
(v) Feed the logic 0 (0V) or 1(5V) in different combinations at the inputs w, x, y, and z
according to truth table.
(vi) Observe and note down the output readings for F for different combinations of inputs and
verify the truth table for input/output combination

F(w, x, y, z) = Σ (0,1,2,4,5,6,8,9, 12, 13, 14)

Truth Table Representation of the Function

Simplification Using 4-Variable K-Map

Simplified Boolean function F=_______________________

Observation Table of simplified function:

Lab Task: Plot the following Boolean function in a map: F=A’D+BD+B’C+AB’D

Combine the 1’s in the map to obtain the simpilified function for F in sum of products form.
Then combine the 0’s in the map to obtain the simplified function for F’ also in sum of products
form. Obtain truth table of each circuit and show that they are the complements of each other.

Conclusion:
Lab No. 04
Design of Combinational Code-Converters circuits
Objective:
 Design of different combinational circuits and their applications using basic logic gates.
 Creation and observation of the four-bit gray code number representation sequence
 Exercising the design of code conversion logic circuits,
 Creating the truth table of conversion functions from Binary to Gray code
 Developing skills in simplification of specified logical functions

Apparatus Required:
 Prototyping board (breadboard)
 DC Power Supply 5V Battery
 Light Emitting Diode (LED)
 Digital ICs:7486: Quad 2 input EXOR
 Logic Probe
 Digital Logic Trainer IDL-400
 Connecting Wires

Pin Diagram:

Fig 4.1: Pin diagram of Binary to gray code converter using 7486 IC (Exor Gate)

Theory:
Code Converters:
A code converter is a circuit that makes two digital systems using different codes for the same
information. It means that a code converter is a code translator from one code to the other. The
code converter is used since to systems using two different codes but they need to use the same
information. So, the code converter is the solution.

Binary-to Gray Converter:

An interesting application for the exclusive-OR gate is a logic gate to change a binary number to
its equivalent in Gray Code. The logic circuit can be used to convert a 4-bit binary number
ABCD into its Gray-code equivalent, G1, G2, G3 and G4.

Application:

Some sensors send information in gray code. These must be converted to binary in order to do
arithmetic with it. Occasionally, it is necessary to convert back.

Advantages:
Higher speed or smaller code.

Circuit Diagram:

Fig 4.2: Circuit Diagram of Binary to Gray Code Converter

Truth Table:
 INPUTS OUTPUTS

A B C D G1 G2 G3 G4

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

Procedure:
1. Collect the components necessary to accomplish this experiment.
2. Plug the IC chip into the breadboard.
3. Connect the supply voltage and ground lines to the chips. PIN7 = Ground
and PIN14 = +5V.
4. Make connections as shown in the respective circuit diagram.
5. Connect the inputs of the gate to the input switches of the LED.
6. Connect the output of the gate to the output LEDs.
7. Once all the connections have been done, turn on the breadboard
8. Operate the switches and fill in the truth table (Write "1" if LED is ON and "0" if L1 is
OFF, apply the various combinations of inputs according to the truth table and observe the
condition of Output LEDs.
Observation Table:
Input Variable: A B C D
Output Variable: G3 G2 G1 G0
Table 4.1: Binary to Gray code

INPUTS(LED) OUTPUTS(LED)

A B C D G3 G2 G1 G0

Lab Task: 1. Design a combinational circuit with four input lines that represent a decimal
digit in BCD and four output lines that generate the 9’s complement of the input digit. (9’s
Complementor)
2. Design and test majority Circuit

Conclusion:
Lab No. 05

To design and test various adders and subtractor circuits

Objective:
 To understand the principle of binary addition.
 To understand and to differentiate half & full adder concept.
 To understand and to differentiate half & full Subtractor concept.
 To implement half-adder and full adder circuit using logic gates
 To Construct and test four-bit Parallel Adder
 To construct and test four-bit Adder-Subtractor

Apparatus Required:

 Prototyping board (breadboard)

 DC Power Supply 5V Battery
 Light Emitting Diode (LED)
 Digital ICs: 7408: Quad 2 input AND
7486: Quad 2 input EXOR
7432: Quad 2 input OR
 Logic Probe
 Digital Logic Trainer IDL-400
 Connecting Wires

Activity No. 01

Half Adder: A half adder is a logical circuit that performs an additional operation on two binary
digits. The half adder produces a sum and a carry value which are both binary digits.

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Fig 5.1: Circuit Diagram of Half Adder and Truth

Boolean Expression: S= A B

C=AB

Activity No. 02:

Full Adder: Full Adder is a logical circuit that performs an additional operation on three
binary digits. The full adder produces a sum and carry value, which are both binary digits. It can
be combined with other full ads or work on its own.
Input Output

A B Ci S Co

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Fig 5.2: Circuit Diagram of Full Adder and Truth Table

Boolean Expression: S= A B Ci

Co=AB+Ci(A B)

Procedure:
1. Collect the components necessary to accomplish this experiment.
2. Plug the IC chip into the breadboard.
3. Connect the supply voltage and ground lines to the chips. PIN7 = Ground
and PIN14 = +5V.
4. According to the pin diagram of each IC mentioned above, make the connections
according to circuit diagram.
5. Connect the inputs of the gate to the input switches of the LED.
6. Connect the output of the gate to the output LEDs.
7. Once all connections have been made, turn on the power switch of the
breadboard
8. Operate the switches and fill in the truth table (Write "1" if LED is ON and
"0" if LED is OFF Apply the various combination of inputs according to the truth table
and observe the condition of Output LEDs.

Observation Table:
Half Adder Input Variable: A, B
Output Variable: S, C

Table 5.1: Half Adder

 INPUTS(LED) OUTPUT
(LEDS)

A B S C

Full adder: Input Variable: A, B, Ci

Output Variable: SUM(S), Carry (Co)

Table 5.2: Full Adder

INPUT(LED)
OUTPUT(LED)

A B Ci Sum S Carry Co
Activity No. 03:

Half Subtractor:

Fig 5.3: Pin Diagram of Half Subtractor

Activity No. 04:

Full Subtractor:

Fig 5.4: Pin Diagram of Full Subtractor

Theory:
Half Subtractor: The half-Subtractor is a combinational circuit which is used to perform
subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D
(difference) and B (borrow).
 Fig 5.5: Circuit Diagram of Half Subtractor

Full Subtractor: A full Subtractor is a combinational circuit that performs a subtraction

between three bits, considering that a ‘1’ may have been borrowed by a lower significant stage.
The 3 inputs denote minuend, subtrahend and previous borrow, respectively. The 2 outputs are
different (D) and borrow (B).

Fig 5.6: Circuit Diagram of Full Subtractor

Lab Tasks:
1. Construct and test four-bit binary parallel adder with IC 7483.

2. Construct and test four-bit Adder-Subtractor with IC 7483

CONCLUSION:
Lab No. 06

Implementation of various logic circuits Of Decoder and Priority

Encoder
Objective:
 Characteristics of Encoder & Decoder.
 Design and Implement 4x2 Encoder from standard AND, NOR and NOT gates.
 Design and Implement 2x4 Decoder from standard AND, NOR and NOT gates.
 Implementation of full adder with 3x8 decoder
 Design and Implementation priority Encoder

Apparatus Required:
 Prototyping board (breadboard)
 Light Emitting Diode (LED)
 Digital ICs:
 7408: Quad 2 input AND
 7432: Quad 2 input OR
 74147: Priority Encoder
74139 2-to-4-line decoder
 Digital Logic Trainer IDL-400
Theory:

Activity N0.01
Encoder:
In digital electronic an encoder is the logic device that converts 2N input signals to N-bit
coded outputs. A simple encoder circuit is a one-hot to binary converter. That is, only one
of input lines allowed to be in 1, binary code of this 'hot' line is produced a on the N-bit
Output.

Fig 6.1: Block Diagram of 4:2 Encoder

 Fig 6.2: Truth Table of 4:2 Encoder

Fig 6.3: Circuit Diagram of 4:2 Encoder

Activity N0.02
DECODER:
n to 2n.
n = No. of input lines.
2n = No. of outputs of a Decoder.
Decoder is a circuit that converts binary information from n-input lines to max of 2n output lines
e.g. if we have 2 inputs i.e. x, y then there will be 4 outputs of a Decoder, and the size of
Decoder will be 2 X 4.

Fig 6.4: Block Diagram of 2:4 Decoder

Truth Table of 2:4 Decoder

Boolean Functions for 2 x 4 Decoder:
do = E x′y′, d1 = E x′y, d2 = E x y′, d3 = E x y

Fig 6.5: Circuit Diagram of 2:4 Decoder

Procedure:
1. Make combinational circuit of 4:2 Encoder using Basic Gates and verify its
Truth Table.
2. Make combinational circuit of 2:4 Decoder using Basic Gates and verify its
Truth Table.
Activity N0.03

Implementation of Priority Encoder with IC 74147N.

Fig 6.6: Truth Table of Priority Encoder

Pin diagram of Priority Encoder (IC 74147):

Fig 6.7: IC 74147

Lab Tasks: Implement full adder with 3x8 decoder IC74138.

Conclusion:
Lab No. 07
Design and implementation of Boolean function with Multiplexers
and De-multiplexers
Objective:
 To get familiar with the concept of multiplexing and demultiplexing
 To get familiar with MSI (medium scale integration) technology.
 Implementation of Boolean function with MUX
Apparatus Required:
 Prototyping board (breadboard)
 DC Power Supply 5V Battery
 Light Emitting Diode (LED)
 Digital ICs:74153: Dual 4:1 MUX
74139: Dual 1:4 DEMUX
 Logic Probe
 Digital Logic Trainer IDL-400
 Connecting Wires
Pin Diagram:

Fig 7.1: Pin diagram of dual 4:1 Mux (IC74153)

Fig 7.2: Pin diagram of Dual 1:4 DEMUX (IC74139)

Theory:
Multiplexer:
A data selector, more commonly called a Multiplexer, shortened to "Mux" or "MPX", is
combinational logic switching devices that operate like a very fast acting multiple position
rotary switches. They connect or control multiple input lines called "channels" consisting of
either 2, 4, 8 or 16 individual inputs, one at a time to an output. Then the job of a multiplexer is
to allow multiple signals to share a single common output.
Multiplexer Symbol:

Fig 7.3: Symbolic Representation of MUX

Truth Table of 4:1 Mux (IC 74153)( Channel A) with Active low mode:

Inputs(Channel A) Select lines Output

Ea Iao Ia1 Ia2 Ia3 S0 S1 Za
1 × × × × × × 0
0 0 × × × 0 0 0
0 1 × × × 0 0 1
0 × 0 × × 0 1 0
0 × 1 × × 0 1 1
0 × × 0 × 1 0 0
0 × × 1 × 1 0 1
0 × × × 0 1 1 0
0 × × × 1 1 1 1
Demultiplexer:

The data distributor, known more commonly as a Demultiplexer or "Demux", is the

exact opposite of the Multiplexer. The demultiplexer takes one single input data line and then
switches it to any one-off a few individual output lines one at a time. The demultiplexer converts
a serial data signal at the input to parallel data at its output lines. The function of the
Demultiplexer is to switch one common data input line to any one of the 4 output data lines.
Some standard demultiplexer IC´s also have an "enable output" input pin which disables or
prevents the input from being passed to the selected output. Also, some have latches built into
their outputs to maintain the output logic level after the address inputs have been changed.
However, in standard decoder type circuits the address input will determine which single data
output will have the same value as the data input with all other data outputs having the value of
logic "0".
Truth table of 1:4 Demux (IC 74139) with Active low mode:

Input(Channel A) Output
Ea S0 S1 D0 D1 D2 D3
1 × × 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

Procedure:
1. Collect the components necessary to accomplish this experiment.
2. Plug the IC chip into the breadboard.
3. Connect the supply voltage and ground lines to the chips. PIN7 = Ground
and PIN14 = +5V.
4. Make connections as shown in the respective circuit diagram.
5. Connect the inputs of the gate to the input switches of the LED.
6. Connect the output of the gate to the output LEDs.
7. Once all the connections have been done, turn on the breadboard
Block diagram of 4x1 MUX:
 Fig 7.4: Block Diagram of 4x1 MUX

I0, I1, I2 and I3 are inputs of Mux, S1 and S0 are select lines and Y is output

The function table of 4x1 Mux is

Select o/p
lines

S1 S0 Y

0 0 Io

0 1 I1

1 0 I2

1 1 I3

The Boolean function for 4x1 Mux is

Y = I0 S1 S0+ S1 S0 I1+ S1 S0 I2+ S1 S0I3

Logic Diagram of 4x1 Mux is

 Fig 7.5: Logic Diagram of 4x1 Mux

We check this logic circuit by Function Table of 4X1 Mux as drawn above.

Demultiplexer:
Input Variable: Ea, S0, S1
Output Variable: D0, D1, D2, D3

Table: Demultiplexer

Input(Channel A) Output
Ea S0 S1 D0 D1 D2 D3

Lab task:

Implement the following Boolean function with multiplexer and verify the truth table.

F(A, B,C,D)=∑(1,3,4,11,12,13,14,15)

Conclusion:
Lab No. 08
Implementation of BCD-to-Seven Segment Decoder

OBJECTIVE:
To display BCD numbers on seven segment display using decoder.

APPARATUS:
 IC 74LS47
 Common Anode Seven Segment Display
 330-ohm resistances

THEORY:
A Seven Segment Display, electronic device, consisting of arrangements of 7 LED’s which
operate individually. A LED gets on when a potential drop is about 3-5 volts

NUMBER SEVEN SEGMENT DISPLAY

Dp G F E D C b A

0 1 1 0 0 0 0 0 0

1 1 1 1 1 1 0 0 1
 2 1 0 1 0 0 1 0 0

3 1 0 1 1 0 0 0 0

4 1 0 0 1 1 0 0 1

5 1 0 0 1 0 0 1 0

6 1 0 0 0 0 0 1 0

7 1 1 1 1 1 0 0 0

8 1 0 0 0 0 0 0 0

9 1 0 0 1 1 0 0 0

A BCD to seven segment decoder (IC7447) accepts decimal digit and converts it into seven
segment code, BCD code is given to it using 4 switches.

PROCEDURE:

Ic PIN Diagram:
configured IC7447 such that it could take 4 inputs at pin A, D, B & C using switches, except

The sequence of switches generating these two BCD codes 1010 & 1111 and provided Vcc(5V)
on pin 16 and ground on pin 8. I have connected small resistance of 330Ω to pins from 9 to 15
and provided 5V to Common Anode of 7-Segment Decoder. IC pin outs are given below:
Hardware Result:

Software Result:

:
Lab Task Implement BCD to seven segment decoders using with IC 74147 with common
anode seven segments.

Conclusion:
Lab No. 09
To construct, test and investigate the operation of various latches
and flip-flops
Objective:
 Characteristics of R-S Latch & D-Latch.
 Implementation of R-S Flip Flop using NAND gate.
 Implementation of D-Flip Flop using IC 7474.
 Implementation of J-K Flip Flop using IC 7476

Apparatus Required:
 Prototyping board (breadboard)
 DC Power Supply 5V Battery
 Light Emitting Diode (LED)
 Digital ICs: 7400: Quad 2 input NAND
7476: JK Flip-Flop
7474: D Flip-Flop
 Logic Probe
 Digital Logic Trainer IDL-400
 Connecting Wires
Theory:
 Flip-flops are the basic building blocks of sequential circuits. The clocked Flip-flops
change their output state depending upon inputs at certain intervals of time synchronized with
the clock pulse applied to it. Different types of Flip-flops are S-R, J-K, D & T. Their operations
are described by the respective truth tables. MSI chip 7476 incorporates two negative edge
triggered Master–Slave JK flip-flops. The J-K flip-flops can be converted into D & T flip-flops
as well.

RS Latch with NAND gates:

Figure 9.1: RS Latch & its Truth Table

In case of D flip-flop, The Q output always takes on the state of the D input now of a rising
clock edge. (or falling edge if the clock input is active low). It is called the D flip-flop for this
reason, since the output takes the value of the D input or Data input and Delays it by one clock
count. The D flip-flop can be interpreted as a primitive memory cell, zero-order hold, or delay
line.

Truth Table of D-Flip Flop:

 Figure 9.2: PIN diagram of IC 7474

IC 7474 has Two D-Flip Flops in it. Do connections according to Pin configuration to use it.

Procedure:
1. Give biasing to the IC and do necessary connections according to the pin diagram
given.
2. For various combinations of inputs first verify the truth table of RS flip-flops given
above.
3. Then verify the truth table of D flip-flops implemented using RS flip-flops also given
above.
Observation Table:
Verify the characteristics tables of D flip-flops with IC 7474.

Lab Task:
Verify the characteristics tables of JK flip-flops with IC 7476.

Conclusion:
Lab No. 10
(a) Design of Synchronous Binary/BCD Counters
(b) Design of BCD counter with parallel load
Objective:
 Characteristics of Asynchronous/Ripple Counter.
 Characteristics of Synchronous Counter.
 Implementation of BCD counter with parallel load.

Apparatus Required:
  Prototyping board (breadboard)
 DC Power Supply 5V Battery
 Light Emitting Diode (LED)
 Digital ICs: 74160: 74293
 Function Generator
 Logic Probe
 Digital Logic Trainer IDL-400
 Connecting Wires
Theory:
A counter is a sequential circuit that counts in a cyclic sequence. It is essentially a register
that goes through a predetermined sequence of states upon the application of input pulses. Since
a counter circuit must remember its past states, it must possess memory. The number of flip-
flops (JK Flip Flop IC 7476) used and how they are connected determine the number of states
and the sequence of the states that the counter goes through in each complete cycle.

Counters can be classified into two broad categories according to the way they are clocked,

1. Asynchronous (Ripple) Counters - the first flip-flop is clocked by the external clock pulse,
and then each successive flip-flop is clocked by the Q or Q' output of the previous flip-flop.

2. Synchronous Counters - all memory elements are simultaneously triggered by the same
clock.

Activity No.01:
 Figure 10.1: PIN diagram for binary counter

Activity No.02:

Figure 10.2: PIN diagram for BCD counter

Lab Task: BCD counter with parallel load

Conclusion:
Lab No. 11
a) Design of Synchronous BCD Up-Down Counter (IC#74190)
b) Design of shift register with parallel load (IC#74195)
Objective:
 Implementation of BCD up-down counter
 Implementation of shift register with parallel load.

Apparatus Required:

 Prototyping board (breadboard)

 DC Power Supply 5V Battery
 Light Emitting Diode (LED)
 Digital ICs: 74190: 74195
 Function Generator
 Logic Probe
 Digital Logic Trainer IDL-400
 Connecting Wires
Theory:
A mod-n counter may also be described as a divide-by-n counter. This is because the most
significant flip-flop (the furthest flip-flop from the original clock pulse) produces one pulse for
every n pulse at the clock input of the least significant flip-flop (the one triggers by the clock
pulse). Thus, the above counter is an example of a divide-by-4 counter. A counter which can be
made to count in either the forward or reverse direction is called an up-down, a reversible or
forward-backward counter.

Down Counter: A binary counter with a reverse count is called a binary down counter. In a
down counter, the binary counter is decremented by 1 with every input count pulse. The count of
a 4-bit down counter starts from binary 15 and continues to binary counts 14, 13, 12… 0 and
then back to 15. In a binary down counter, outputs are taken from the complement terminals Q’
of all flip flops. For a down counter, when Q goes from 0 to 1, Q’ will go from 1 to 0 and
complement the next flip flop.

Up Counter: A binary counter with a normal count is called a binary up counter. In a up

counter, the binary counter is incremented by 1 with every input clock pulse. Outputs are taken
from the normal output terminal Q of all flip flops. For an up counter when Q goes from 1 to 0,
it complements the next flip flop.
Activity No.01:

Figure 11.1: BCD Up-Down Counter

Activity No.02:
 Figure 11.2: Shift Register with parallel load

Lab Task:

Ring Counters: A ring counter is a circular shift register with only one flip flop being set at any
time, all others are cleared. The single bit is shifted from one flip flop to the other to produce the
sequence of timing signals.

Figure 11.3: Ring Counter

It is a 4-bit shift register connected to a ring counter. In this counter, Serial In Da is connected to
Serial Out Qd.First of all, CLR’ is set to 0 to clear all flip flops and then it is set to 1 for the
circuit operation. After clearing all the flip flops, Pr’ of 4th flip flop is set to 0 while for all other
three flip flops, it set to 1. This is done so that the initial value of register becomes 0001 [Pr’=0,
sets the 4th flip flop to 1]. Single bit is shifted right with every clock pulse. Each flip flop is in 1
state once every four clock pulses.

Conclusion:
Lab No. 12
Introduction to Verilog HDL and Xilinx software. Basic language
constructs and design entry using Verilog HDL
Introduction:
This lab describes a hardware description language (HDL). A hardware description language is a
language that describes hardware of a digital system, in a textual form. It can be used to
represent logical diagrams, Boolean expressions and other complex digital circuits. The
language contents can be stored and retrieved easily and can be processed by computer software
in an efficient manner. Two major applications of this language are:

1. LOGICAL SIMULATION
2. SYNTHESIS

Logical simulation:

It is the representation of the structure and behavior of a digital logical system using a computer.
The code that tests the functionalities of the design is called “Stimulus” or “Test Bench”.

Synthesis:
Logical synthesis is the process of driving a list of components and their interconnections (called
a NETLIST) from the module of a digital system in HDL.

Levels of abstraction in Verilog:

The level of abstraction to describe a module can be changed without any change in the
environment there are four levels of abstraction:

Gate (Structural) Level:

A slightly higher level of abstraction would be the gate level, which refers to the ability to
describe the circuit as a net list of primitive logic gates and functions. The gates have one scalar
output and multiple scalar inputs

Switch Level:

The lowest level of abstraction for a digital HDL would be the switch level, which refers to the
ability to describe the circuit as a net list of transistor switches. A more detailed modeling
scheme that can catch some additional electrical problems when transistors are used in this
way. Now, little-used because circuits generally aren’t built this way.

Data Flow Level:

For small circuits, the gate level modeling approach works very well because the number of
gates is limited, and designers can instantiate and connect every gate individually. However, in
complex design the number of gates is very large. Thus, implementing the function at a level
higher than gate level is a good choice. Dataflow modeling has become a popular design
approach as logic synthesis tools have become sophisticated. This approach allows the designer
to concentrate on optimizing the circuit in terms of data flow.

Behavioral Modeling (Functional and Algorithmic Level):

Verilog provides the designer with the ability to describe the design functionality in an
algorithmic manner. In other words, the designer describes the behavior of the circuit. The
abstraction in this modeling is as simple as writing the logic in C language. Verilog behavioral
models contain procedural statements that control the simulation and manipulate variables of the
data types previously described. The activity starts at the control constructs initial and always.
Each initial statement and each statement start a separate activity flow. All the activity flows are
concurrent, allowing the user to model the inherent concurrence of hardware.

Register Transfer Level:

Verilog allows the designer to mix and match all four levels of abstraction in a design. In the
digital design community, the term register transfer level (RTL) is frequently used for a Verilog
description that uses a combination of behavioral and data flow constructs and is acceptable to a
logical synthesis tool.

Describes a system by the flow of data and controls signals within and between functional
blocks. It's a behavioral design concept in which you make HDL models of registered circuits
and how signals interact between them such as memories, flip flops, latches, shift registers, and
so on. RTL is a combination of Behavioral and Data flow modeling which should be
synthesized. RTL description is more complex and less technology dependent than behavior
hardware description.

What is a Module?
The module is the basic building block in Verilog. A module can be element of a collection of
lower-level design blocks.

In Verilog, a module is declared by keyword module a corresponding end module must appear
at the end of the module definition.

Lexical Conventions in Verilog:

White Spaces:

Blank space (\b), tabs (\t), and new lines (\n) comprise the white spaces. White space is ignored
by the Verilog except when it separates tokens. White space is not ignored in strings

Comments:

Comments can be inserted into the code for readability and documentation. There are two ways
to write comments. A one-line comment starts with “//”. Verilog skips from that position to the
end of the line. A multiple comment starts with “/*” and ends with “*/”.
a = b && c; //This is a one-line comment

/* This is a multiple line

Comment*/

/* This is /* an illegal */ comment */

/* This is // a legal comment */

Gate Level Modeling:

Within the logic level the characteristics of a system are described by logical links and their
timing properties. All signals are discrete signals. They can only have definite logical values
(`0', `1', `X', `Z`). The usable operations are predefined logic primitives (AND, OR, NOT etc.
gates). Using gate level modeling might not be a good idea for any level of logic design.

Gate Primitives:

Gate
Description Instantiation Syntax
Type

AND N-input AND gate and a1(out,in1,in2) ;

NAND N-input NAND gate nand a2(out,in1,in2) ;

OR N-input OR gate or a3(out,in1,in2) ;

NOR N-input NOR gate nor a4(out,in1,in2) ;

XOR N-input XOR gate xor x1(out,in1,in2) ;

XNOR N-input XNOR gate xnor x2(out,in1,in2) ;

NOT 1-input NOT gate not g1 (out , in) ;

BUF 1-input & N-output BUF gate buf b1_2 (out1,out2, in) ;

BUFIF1 1-input,1-output,1-control BUF gate bufif1 b0(out,in,control) ;

BUFIF0 1-input,1-output,1-control BUF gate bufif0 b1(out,in,control) ;

NOTIF1 1-input,1-output,1-control NOT gate notif1 b2(out,in,control) ;

NOTIF0 1-input,1-output,1-control NOT gate notif0 b3(out,in,control) ;

Lab Work:

Verilog Code For two simple inputs AND Gate.

Gate Level Verilog Code:

module and gate (Out, A, B); //Starting of module and defining inputs and outputs
input A, B; /inputs
output Out; /outputs
and A1(Out, A, B); //Gate level description of 2 inputs and 1 output AND gate
end module
modules stim; //Stimulus module
reg A, B; //Always make inputs as Reg or Registers
wire Out; //Always make outputs as wire
and gate G1(Out, A, B); //Instantiation of main module (i.e. and gate)
initial
begin
A=0; B=0.
#10 begin A=0; B=1; end
#10 begin A=1; B=0; end
#10 begin A=1; B=1; end
#10 begin A=1; B=1; end
end
end module
Truth Table for 2 Inputs AND Gate:

Truth Table For 2 Inputs AND Gate

Input A Input B Output Out

0 0 0

0 1 0

1 0 0

1 1 1

Timing Diagram Verification for the written code:

 Some important things that we can see from the above code are:
 The module always starts with the keyword module
 Inside module () we define inputs and outputs, but their sequence is not important
 But in case of gate level description, it is very imp that output must be written before
the inputs i.e. AND (Output, Input1, Input2 ……………...Input n)
 We can also define additional wires i.e. Links other than input or output as explained in
the second example below
 Some keywords for gate level description are:

 and A1(output(s), input1, input2, input3………………..input n)

 or P1(output(s), input1, input2, input3………………..input n)
 not N1(output(s), input1, input2, input3………………..input n)
 Nand D1(output(s), input1, input2, input3………………..input n)
 nor H1(output(s), input1, input2, input3………………..input n)
 xor S1(output(s), input1, input2, input3………………..input n)
 xnor Q1(output(s), input1, input2, input3………………..input n)
 buf B1(output(s), input1, input2, input3………………..input n)

 Stimulus module is used to verify the results that the code is working in the right
fashion or not.
 At the end draw the truth table for the AND gate and verify your code according to the
output in the timing diagram and in the truth table

Lab Task:
Q 1. Write Verilog code for the following code and attach the timing diagrams and the truth
table
Conclusion:
Lab No. 13
Different Combinational Logic Design circuits with Verilog using
Xilinx Software
Apparatus:
 Xilinx ISE.
 Computer with windows installed in it.

Theory:
Xilinx ISE (Integrated Synthesis Environment) is a software tool produced by Xilinx for
synthesis and analysis of HDL designs, enabling the developer to synthesize ("compile") their
designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to
different stimuli, and configure the target device.

Step by Step guide to Xilinx ISE:

How to make a Half Adder:

To learn to use Xilinx ISE design suit, we would make a half Adder as an example. So, following are the
steps to make a half Adder;
We run the Xilinx ISE design suit on our computer. We clicked on ‘new project’ as shown in figure
no. 1.

 We named our project ‘Half’ and set path for save location and clicked ‘next’ as shown in figure no.
2.
 Now we clicked on <project> and then <new source> as shown in figure no. 3.

Now we selected <Verilog module> and named it <Half> then clicked <next> as shown in
figure no. 4.
We wrote the names of terminals and declared which are <input> and <output> and declared NET
or Wires as <in out>. Then clicked <next> and <finish> in the next dialog as shown in figure no. 5 and 6.

Then we wrote the module and chose ´Synthesize-XST’

from lower left side panel and selected ‘start with top-level blocks’ and clicked ‘ok’ as shown in
figure no.7 & 8.
 The circuit diagram appeared as shown in figure no. 7. We double clicked the ‘half adder’ to check
the details which are given in figure no. 8.

After that we chose ‘Simulation’ instead of

‘Implementation’ and then ‘Half adder (Half adder. v)’ and after that ‘Simulate Behavioral Model’ as
shown in figure no. 9. Then ‘Verilog text fixture’ and named it ‘Half adder’ and then ‘next’ and again
‘next’ as shown in figure no. 10.
We changed the time delay to #60 and input values to a=0; b=1 as shown in figure no. 11.

We double clicked on ‘Simulate Behavioral Model’ as shown in figure no. 12 and we got the
response diagram which is given as,

Figure 12

Full Adder:
A full adder is a digital circuit that performs addition. Full adders are implemented with logic
gates in hardware. A full adder adds three one-bit binary numbers, two operands and a carry bit.
The adder outputs two numbers, a sum and a carry bit. The term is contrasted with a half adder,
which adds two binary digits.

Procedure:
1. Open Xilinx ISE in your computer and create a new project give this file a name and assign
number of inputs and outputs.
2. Usually for Full adder we take three inputs and two outputs named S and C (Sum and
Carry).
3. Write the code for full adder and click on synthesize XST.
4. The circuit diagram for the full adder circuit will be implemented and an external diagram
will appear. Verify it by assigning the inputs and add some delay and see the result through
behavioral simulation.
5. Observe the waveform that will change in accordance to the change in the input and output
values.

Explanation:
 First open Xilinx ISE and click on files to create a new project a window will appear as
shown in the figure below. Give the name of the project. Name the project as full adder and
click next.

Figure (10.1)

 Click on new source and click on Verilog module as shown and name its full adder as
well and click next.

Figure (10.2)
  A window as shown below will appear. Specify the inputs and outputs. For full adder there
are three inputs and two outputs. Let’s take three inputs “a”, “b” and “cin” and two outputs
“s” and “cout” after doing so click next.

Figure (10.3)

 Click Finish and Verilog programming for the full adder circuit will appear as shown
below. Write the code for full adder. Give the commands for XOR and AND operations.
After that click on synthesis-XST.

Figure (10.4)

 Click on View RTL Schematic as shown in the above figure. A diagram will appear showing
the external view of full adder. Double clicks to get the detailed view.
 Figure (10.5)

 Click on source and click on Verilog text fixture and give name full adder and click next.

Figure (10.6)

 A window as shown below will appear. Give the input commands by adding 1s and 0s for
input a, b and cin.

Figure (10.7)

 Now click on behavioral simulation and then click on check syntax. After that check the
simulation waveform by clicking simulate behavioral module.

Figure (10.8)
 The waveform for the given input combination will appear. Now check the pulse to get a
clear idea. At first note that when all inputs are zero, the outputs are also zero as shown in
the figure below.

Figure (10.9)

 Now note when a is 0 and b and cin are 1 the output s is 0 and the other one is 1.

Figure (10.10)

 Note when a is 1 and b and cin are 0 the output s is 1.

 Figure (10.11)

Lab Task:
Write Verilog code of other combinational circuits like MUX, De-MUX, Decoder and Encoder
and run on Xilinx software.

Conclusion:
Lab No. 14
Different Sequential Logic Design circuits with Verilog using Xilinx
Software
Objective:
To design and simulate S-R Latch, D flip flop, J-K flip flop in Xilinx ISE.

Apparatus:
Computer with at least 2GB RAM, OS Windows 7/8/8.1/10, Xilinx ISE and electricity.

Module:
The module for S-R Latch is given as;

Procedure:
 We run the Xilinx ISE design suit on our computer. We clicked on ‘new project’.
 We named our project ‘S_R’ and set path for save location and clicked ‘next’.
 Now we clicked on ‘project’ and then ‘new source’.
 Now we selected ‘Verilog module’ and named it ‘S_R’ then clicked ‘next´.
 We wrote the names of terminals and declared which are ‘input’ and ´output’ and declared NET or
Wires as
‘In out’. Then clicked ‘next’ and ´finish’ in the next dialog.
 Then we wrote the module and chose ´Synthesize-XST’ from lower left side panel and clicked
´run’.
 The circuit diagram appeared as shown in figure no. 1. We double clicked the ‘SR_FF’ to check the
details which are given in figure no. 2.
 After that we chose ‘Simulation’ instead of
 ‘Implementation’ and then again ‘new source’.
 Then ‘Verilog text fixture’ and named it ‘SR_FF’ and then ‘next’ and again ‘next’.
 We changed the time delay to #60 and input values to s=0; r=1.
We double clicked on ‘Simulate Behavioral Model’ and we got the response diagram.

Observation:
Designing J-K Flip-Flop in Xilinx ISE
Module:
The module for J-K Flip-Flop is given as;

Procedure:
 We run the Xilinx ISE design suit on our computer. We clicked on ‘new project’.
 We named our project ‘J_K’ and set path for save location and clicked ‘next’.
 Now we clicked on ‘project’ and then ‘new source’.
 Now we selected ‘Verilog module’ and named it ‘J_K’ then clicked ‘next´.
 We wrote the names of terminals and declared which are ‘input’ and ´output’ and declared NET or
Wires as
 ‘In out’. Then clicked ‘next’ and ´finish’ in the next dialog.
 Then we wrote the module and chose ´Synthesize-XST’ from lower left side panel and clicked
´run’.
 The circuit diagram appeared as shown in figure no. 1. We double clicked the ‘JK_FF’ to check the
details which
 are given in figure no. 2.

 After that we chose ‘Simulation’ instead of

 ‘Implementation’ and then again ‘new source’.
 Then ‘Verilog text fixture’ and named it ‘JK_FF’ and then ‘next’ and again ‘next’.
 We changed the time delay to #60 and input values to j=0; k=1.
 We double clicked on ‘Simulate Behavioral Model’ and we got the response diagram.
Observation:

Designing D Flip-Flop in Xilinx ISE

Module:
The module for D Flip-Flop is given as;

Procedure:
 We run the Xilinx ISE design suit on our computer. We clicked on ‘new project’.
 We named our project ‘DFF’ and set path for save location and clicked ‘next’.
 Now we clicked on ‘project’ and then ‘new source’.
 Now we selected ‘Verilog module’ and named it ‘D_FF’ then clicked ‘next´.
 We wrote the names of terminals and declared which are ‘input’ and ´output’ and declared NET or
Wires as
 ‘In out’. Then clicked ‘next’ and ´finish’ in the next dialog.
 Then we wrote the module and chose ´Synthesize-XST’ from lower left side panel and clicked
´run’.
 The circuit diagram appeared as shown in figure no. 1. We double clicked the ‘D_FF’ to check the
details which
 are given in figure no. 2.
 After that we chose ‘Simulation’ instead of
 ‘Implementation’ and then again ‘new source’.
 Then ‘Verilog text fixture’ and named it ‘D_FF’ and then ‘next’ and again ‘next’.
 We changed the time delay to #60 and input values to clk=0; d=1.
 We double clicked on ‘Simulate Behavioral Model’ and we got the response diagram.

Observation:

Lab Task:
Write Verilog code of other sequential circuits like counters and run on Xilinx software.

Conclusion: