SE COMPUTER SEM-I

210245
DIGITAL ELECTRONICS AND LOGIC DESIGN
UNIT –V
LOGIC FAMILIES

Prof.P.C.Patil
Department of Computer Engg
Guru Gobind Singh College of Engineering , Nasik
pcpatil.webs.com
Classification of Logic Families
Characteristics of Digital IC’c
Important Specifications of Logic families

1. Fan-in, Fan-out,
2. Current and voltage parameters,
3. Noise immunity,
4. Propagation Delay,
5. Power Dissipation,
6. Figure of Merits,
7. Operating Temperature Range,
8. Power supply requirements.
Speed of Operation

Is specified in terms of propagation delay time

The delay time is measured between 50 % voltage levels at input & output as shown
The propagation delay is average of t PHL & t PLH

i/o voltage waveform

o/p voltage waveform

tPHL tPLH
time
1. Fan-in, Fan-out,
Fan-In:
 The fan-in of a logic gate is defined as the number of inputs (coming from
similar circuits) that it can handle properly.

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Fan-Out:
• In general, a logic circuit is required to drive several logic inputs.
 The fan-out (also sometimes called the loading factor) is defined as the
maximum number of standard logic inputs that an output can drive reliably.
 For example, a logic gate that is specified to have a fan-out of 8 can drive 8
standard logic inputs.
 if this number exceeds the output logic-level voltages cannot be guaranteed.

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2. Current and voltage parameters
Four Voltage Parameters
VIH - High Level input Voltage -
It's the minimum input voltage that is recognized by gate as a Logic 1
VIL - Low Level input Voltage -
It's the maximum input voltage that is recognized by gate as a Logic 0
VOH - High Level output Voltage –
It's the minimum output voltage that is available at the output of a gate as a Logic 1
VOL - Low Level output Voltage –
VOH
It's the maximum output voltage that is available at the output of a gate as a Logic 0
∆ 1 = VOH - VIH
VIH

VIL
∆ 0 = VIL - VOL
VOL
 Six Current Parameters
IIH - High Level input Current -
minimum current that must be supplied by a driving source corresponding to Logic 1 voltage
IIL - Low Level input Current -
minimum current that must be supplied by a driving source corresponding to Logic 0 voltage
IOH - High Level output Current -
maximum current a gate can sink in Logic Level 1
IOL - Low Level out put Current -
maximum current a gate can sink in Logic Level 1
Icc(1) - High Level supply Current –
Supply current of a gate when it output = Logic 1
IIH IOH
Icc(0) - Low Level supply Current-
IIL IOL
Supply current of a gate when it output = Logic 0
3. Noise immunity,
 The input and output voltage levels are defined above are shown in figure.
 Stray electric and magnetic fields may induce unwanted voltages, known as
noise, on the connecting wires between logic circuits.
 This may cause the voltage at the input to a logic circuit to drop below VlH or
rise above VlL and may produce undesired operation..
 So, the circuit's ability to tolerate noise signals is referred to as the noise
immunity, a quantitative measure of which is called Noise Margin.

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Noise Immunity
VOH
The Output & Input voltages of a gate are
defined in earlier slide ∆ 1 = VOH - VIH
VIH
1 state DC Noise Margin = ∆ 1 = VOH - VIH
0 State DC Noise Margin = ∆ 0 = VIL - VOL
The Circuit's ability to tolerate Noise is VIL
referred to as Noise Immunity ∆ 0 = VIL - VOL
VOL
AC Noise Margin - 0 Volt
Generally Noise is thought of as ac signal with amplitude & pulse width
A Logic circuit can effectively tolerate a Large Noise amplitude if it is of very short Duration.
(as compared to Gate's propagation delay)
This is referred to as AC Noise Margin & is substantially greater than DC Noise Margin
4. Propagation Delay

TPD,HL TPD,LH

TPD,HL – input-to-output propagation delay from HI to LO output

TPD,LH – input-to-output propagation delay from LO to HI output

 Propagation delay is the average transition delay time for the signal to
propagate from input to output when the signals change in value. It is expressed
in ns.

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5. Power Dissipation
• Power Dissipation is the amount of power dissipated in the circuit and
• is given by
• Pd = Vcc X Icc where Icc - average of Icc(0) & Icc (1)
Vcc - Supply voltage
• Power dissipation is specified in milli volts . Low value is desirable
• Power dissipation is measure of power consumed by the gate when fully
driven by all its inputs.

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6. Figure of Merits,
• It is defined as the product of Speed & Power dissipation
• The speed is specified in terms of propagation delay time expressed in
nanoseconds.
• Figure of merit (pJ) = Propagation delay ( ns) X Power dissipation (mw)
• It is specified in pico joules (ns * mW = pJ).
• It's also called as Speed Power Product .
• Low value is desirable
• In a digital circuit, if it is desired to have a high speed, low propagation delay
time, then there is a corresponding increase in the power dissipation and vice
versa.

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7. Operating Temperature Range
• The temperature range by which a IC functions properly must be known.
• The accepted temperature ranges are: 0 to 70 degree Celsius for consumer
and industrial applications and -55 degree Celsius to 125 degree Celsius.

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8. Power supply requirements
• Every IC requires a certain amount of electrical power to operate.
• The power is supplied by one or more power-supply voltage connected to the
power pin (or pins) on the chip.
• Usually there is only one power-supply terminal on the chip and it is marked
Vcc for TTL or VDD for for MOS devices.
• Obviously low power consumption is desirable features in any digital ICs.

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Logic Family
A group of Compatible ICs with the same Logic Levels , using same supply
voltages for performing various logic functions, and have been fabricated using
specific circuit configuration is referred to as a Logic Family
Logic Families are classified as

• Bipolar - fabricated using bipolar devices such as a B.J.Transistors

These can be further classified as
1. Saturated - Ex. TTL (Transistor Transistor Logic) , RTL , DTL,
2. Nonsaturated - Ex. Schottky TTL , ECL (Emitter coupled Logic)
• Uni polar - fabricated using unipolar devices such as MOSFETs
Can be further divided as
a. PMOS
b. NMOS
c. CMOS
 TTL
Transistor Transistor Logic
• The TTL or Transistor-Transistor Logic logic was invented in the year 1961 by
“James L. Buie of TRW”.
• It is suitable for developing new integrated circuits.
• The actual name of this TTL is TCTL which means transistor-coupled transistor
logic.
• In 1963, the manufacturing first commercial TTL devices were designed by
“Sylvania” known as SUHL or ‘Sylvania Universal High-Level Logic family’.
• After the Texas instruments engineers launched the 5400 series ICs in the
year 1964 with the range of military temperature, then the Transistor-
Transistor Logic became very popular.
• After that, the 7400 series was launched through a narrower range in the
year 1966.
• The Transistor-Transistor Logic was applied to many bipolar logic generations
by slowly improving the speed as well as power utilization over about two
decades.
• Usually, each TTL chip includes hundreds of transistors.
• Generally, functions in a single package range from logic gates to a
microprocessor.
• The first PC like Kenbak-1 was used Transistor-Transistor Logic for its CPU as
an alternate of a microprocessor.
• In the year 1970, the Datapoint 2200 was used TTL components and it was
the base for the 8008 & after that the x86 instruction set.
What is Transistor-Transistor Logic (TTL)?
• The Transistor-Transistor Logic (TTL) is a logic family made up of BJTs (bipolar
junction transistors).
• As the name suggests, the transistor performs two functions like logic as well
as amplifying.
• The best examples of TTL are logic gates namely the 7402 NOR Gate & the
7400 NAND gate.
• TTL logic includes several transistors that have several emitters as well as
several inputs.
• The types of TTL or transistor-transistor logic mainly include Standard TTL,
Fast TTL, Schottky TTL, High power TTL, Low power TTL & Advanced Schottky
TTL.
• The designing of TTL logic gates can be done with resistors and BJTs.
Operation of TTL NAND Gate (Two input),
• The above diagram is the circuit diagram of a TTL NAND gate.
• Now, as seen, the transistor T1 has two emitters to allow two inputs into the
transistor.
• Now, as connected the base voltage will be at 5V.
• if both inputs are logic 1 (usually means about 5V too), the potential
difference across base and emitter would be zero or nearly.
• Hence, no current will flow and the transistor is turned off.
• So, the collector voltage would also be equal to about 5V.
• Hence, this potential can drive current through the emitter of the transistor
T2.
• This then will allow the collector voltage of the transistor T2 to fall.
• Now due to the current flowing through the emitter, there would be a voltage
drop across the resistor R3.
• The desired voltage drop would be about 0.7V
• As seen, this is the input of the transistor T3.
• Hence, the transistor is turned on.
• Due to saturation, the collector voltage will fall to about 0.2V which is a logic
0. A
• For the transistor T4, observe that the emitter voltage is made up of the
entire voltage of the transistor T3 plus the voltage drop across the diode D
about 0.7V.
• Hence the emitter potential would be 0.7+0.2=0.9V.
• Now the base voltage of the transistor T4 ,would be the voltage across the
base-emitter of T3 and the voltage of the entire transistor (i.e.) voltage across
emitter-collector.
• This would also be equal to about 0.9V.
• Hence the emitter voltage and the collector voltage are equal. So the
transistor T4 will be turned off too.
• So the output is zero when both inputs are 1.
 TTL NAND Gate (Basic Gate)
+ Vcc

IB1 RB1
Rc2
4K
1.4 K Rc3
B1
4k
B2 Y
T2
T1 IB3 IC3
A Load
T3
Inputs B
B3 Co Gates
RE2
C
1K
Operation of TTL Gate

o Case I – At least 1 input is Low (0)

• B-E junction of T1 is Forward Biased (Vbe=0.7V), therefore Vb1 ~ 0.2 V + 0.7 V = 0.9 V

• For T2 & T3 to be conducting Vb1 must be at least = 0.6V (B-C junction of T1) + Vbe2 +
Vbe3 = 1.6V

• Since Vb1(0.9V) < 1.6V , the transistors T2 & T3 are Cut Off.

• Hence O/P Y = V(1) =Vcc (1)

o Case II – All inputs are High (1)

• B-E junction of T1 is Reverse Biased , hence Vb1 Assuming T2 & T3 both to be saturated
,then Vc1 = VBE2sat + VBE3sat = 0.8V+0.8V= 1.6 V

• As B1 is connected to Vcc through Rb1 & Vc1=1.6 V , C-B junction of T1 is Forward biased &
Ic1 flows in reverse direction driving T2 & T3 in saturation as assumed .

• Therefore O/P Y = V(0) = 0.2V

 Operation of TTL Gate (contd...)

o Case III – All inputs are High & one input Goes Low
• T1 starts conducting & Vb1 drops to 0.9 V.
• At this point T2 & T3 are still in saturation.
• T2 & T3 will be turned OFF , only when the stored charges in the T2 & T3 are removed.

• Since Vc1= Vb2 = 1.6V , therefore collector base junction of T1 is reverse biased, and T1
operates in Active region causing large Collector current to flow in the direction to help fast
removal of stored base charge in T2 & T3 .
Important Parameters of TTL 7400
VOH = 2.4V VOL= 0.4V VIH = 2.0V VIL= 0.8V

IOH = -400 µA IOL = 16 mA I IH = 40 µA IIL = -1.6 mA

Propagation delay - 10 ns Fan-out 10 = min ( IOH / I IH , IOL / IIL )

 Active Pull up or Totem pole Output
+ Vcc

IC4
Rc2
RB1 Rc4 (100Ω)
IB
1.4 KΩ
1 4 KΩ
B1 B4
T4
B2
T2
T1 C2 Y
A
Inputs B
RE2 IB3
C T3 Load
1 KΩ Co
B3 Gates
Operation of Totem-pole Output or Active Pull-up TTL Gate

When O/P Y is in LOW state , transistor T4 & the diode D are Cut-off.
As T2 & T3 are in saturation Vc2 = Vb4 = VBE3 sat + VCE2sat = 0.8V + 0.2V = 1.0V
Since Vout = 0.2V , the voltage drop across T4 & diode D = 1.0 V – 0.2V = 0.8V
This drop is insufficient to start conduction in T4 & Diode D, hence both are Cut-off

When O/P makes transition from LOW to HIGH , transistor T4 enters into Saturation,
& supplies current for charging of Output capacitor Co with a small Time Constant.
This current IC4 is = (VCC - VCE4 sat – VD – Vo) / RC4 =( 5 – 0.2 – 0.7 – 0.2)/0.1 = 39 mA
T4 is in saturation if hFE > 16.5

The Output Voltage Vo exponentially with Time constant = ( RC4 + RCS4 + Rf ) . Co

As Vo the base current & collector current of T4 bringing T4 eventually out of conduction
V(1) = Vcc – Vγ(T4) - Vγ (diode) = 5 – 0.5 -0.6 = 3.9 V

Now if all input go HIGH , T2 is turned ON , T4 & diode D goes OFF & T3 conducts
The Capacitor Co discharge through T3 & as Vo approaches V(0) , T3 enters into saturation
Note that Ic4 = 39 mA when the output changes from V(0) to V(1) and the base
current IB4 = 2.4 mA

Thus maximum current of 39 + 2.4 = 41.4 mA . Is drawn from Power Supply when
output changes from V(0) to V(1) This current spike generates Noise in the Power
supply & increases Power dissipation

Wired AND

Must not be used with Totem-pole output circuit due to large current spike during
transition from V(0) to V(1) (41 mA)

TTL gate with Open Collector output can be used for Wired –AND connections

Open Collector Output

The basic standard TTL NAND gate with RC3 of T3 missing is the TTL with Open
Collector Output
Unconnected inputs
If any of the inputs are left un connected , they are treated as Logical 1
Clamping Diodes
Used to Suppress ringing caused from fast voltage transitions found in TTL

B1

T1 C2
A
B
C

Clamping diodes
Schottky TTL Gate

The Speed of TTL is limited mainly by the turn –off time delay involved when transistor makes
transition from saturation to Cut-off. This can be eliminated bym replacing all the transistors of TTL
gate by Schottky transistors
The transistors are prevented from entering saturation , hence saving of turn-off time.
Propagation delay = 2 ns. as compared 10 ns of standard TTL
C
Schottky Transistor
Symbol
B
E
storage delay time can be reduced by preventing transistor from going into saturation

A Schottky diode D is connected between base & collector of a D

transistor as shown. C
When transistor is in active region D is reverse biased.
Diode conducts when B-C junction voltage falls to 0.4 V & thus
does not allow Collector voltage of transistor to fall lower than B
0.4 V below base voltage . The collector junction is not sufficiently E
forward biased to enter into saturation
CMOS
CMOS

Complimentary MOS (CMOS)

• Other variants: NMOS, PMOS (obsolete)
• Very low static power consumption
• Scaling capabilities (large integration all MOS)
• Full swing: rail-to-rail output
• Things to watch out for:
– don’t leave inputs floating (in TTL these will float to HI, in CMOS you get
undefined behavior)
– susceptible to electrostatic damage (finger of death)
• Open LTspice example: CMOS NOT and NAND…

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CMOS Inverter
• A complementary MOSFET (CMOS) is obtained by
connecting a p-channel & an n-channel MOSFET in series.
CMOS Inverter
• Drains are tied together & the Output is taken at the
Common Drain. +Vcc

• Input is applied at the common Gate formed by

connecting 2 Gates together as shown S2

• When Vi= Vcc T1 turns ON (VGS1 > VT) and G2 T2 (p-channel)

T2 is OFF Since VGS2 =0. Hence VO= 0 . D2 ID
D
• ID is negligible Vi Vo
G
• When Vi= 0, T1 turns OFF (VGS1 < VT) and T2 is ON D1
T1 (n-channel)
• Since |VGS2| > |VT|. The Output voltage Vo= Vcc & ID is G1
again small.
S1
• In either Logic state the power dissipation is low as PD
= VCC X OFF state leakage drain Current
 A 2- input CMOS NAND Gate

Inputs State of MOS devices O/P

A B T1 T2 T3 T4 Y
+Vcc 0 0 OFF OFF ON ON Vcc
0 Vcc ON OFF ON OFF Vcc
T4
Vcc 0 OFF ON OFF ON Vcc
A
T3
Vcc Vcc ON ON OFF OFF 0
Vo
Y=A.B
T2 Inputs State of MOS devices O/P
A B T1 T2 T3 T4 Y
0 0 OFF OFF ON ON 1
T1
B 0 1 ON OFF ON OFF 1
1 0 OFF ON OFF ON 1
1 1 ON ON OFF OFF 0
 Inputs State of MOS devices O/P
A 2-input CMOS NOR Gate
A B T1 T2 T3 T4 Y
+Vcc 0 0 OFF OFF ON ON Vcc
0 Vcc ON OFF OFF ON 0
Vcc 0 OFF ON ON OFF 0
T4
A Vcc Vcc ON ON OFF OFF 0

T3 Logic Symbol
A
B Y
B
Y=A+B

T2 Inputs State of MOS devices O/P

T1
A B T1 T2 T3 T4 Y
0 0 OFF OFF ON ON 1
0 1 ON OFF OFF ON 0
1 0 OFF ON ON OFF 0
1 1 ON ON OFF OFF 0
Wired – Logic
Wired Logic must not be used with CMOS Logic circuits
CMOS gates with Open drain output can be used for Wired AND operation. In this the drain of the output
transistor (n-channel) is available outside , p-channel load does not exist . The resistance is connected
externally.
74C00 / 54C00 CMOS series
74C00 / 54C00 CMOS series are the 2 commonly used CMOS series ICs.
Parameter Load 74C 74HC 74HCT 74AC 74ACT
VIH (Volts) 3.5 3.85 2.0 3.85 2.0
VIL (Volts) 1.5 1.35 0.8 1.35 0.8
VOH (Volts) CMOS 4.5 4.4 4.4 4.4 4.4
TTL 3.84 3.84 3.76 3.76
VOL (Volts) CMOS 0.5 0.1 0.1 0.1 0.1
TTL 0.33 0.33 0.37 0.37
IIH (µA) 1 1 1 1 1
IIL (µA) -1 -1 -1 -1 -1
IOH (mA) CMOS -0.1 -0.02 -0.02 -0.05 -0.05
TTL -4.0 -4.0 -24..0 -24.0
IOL (mA) CMOS 0.36 0.02 0.02 0.05 0.05
TTL 4.0 4.0 24.0 24.0
TRI-STATE LOGIC
In complex digital systems such as Microprocessors, a number of Gates outputs are required
to be connected to a common line referred to as a Bus, which in turn is required to drive a
number of gates inputs.
When number of gate outputs are to be connected to the Bus, some difficulties arise as
1. Totem pole outputs can’t be connected together because of very large current drain
from supply and consequent heating of IC
2. Open-Collector outputs though can be connected together with common collector
resistance externally, but it causes loading & affects speed of Operation.
Special circuits are developed to overcome this problem.
In these circuits there is one more state of output , referred to as the third state or High
impedance state, in addition to HIGH & LOW states.
These circuits are called TRI-STATE Logic

The TSL Inverter (NOT Gate) circuit, truth table & Symbol are shown next
Difference between
TTL and CMOS