VIT Bhopal University

LABORATORY FILE
FOR

Digital Logic Design

ECE-2002
FALL-SEMESTER 2024-2025

Submitted by: Submitted to:

Name. : Priyanshu Kumar Dr. Amit Kumar Singh
Regno. : 23BCY10230 Assistant Professor, SEEE

VIT Bhopal University

 List of Experiments
S. No. Name of Experiments Page No.

1 To study and verify the truth table of following logic 3

gates: AND, OR, NOT, NAND, NOR, XOR
2 To implement Binary to Gray / Gray to Binary code 6
converter
3 To implement Half Adder & Full Adder using Logic 8
gates
4 To implement Half Subtractor & Full Subtractor using 11
Logic gates
5 To implement even parity& odd parity generator 14

6 To implement 2:1 MUX using basic gates 16

7 To implement 2:4 Decoder using basic gates 19

8 To implement and verify the truth table of Half Adder 22

using 2:4 Decoder
9
9 To study and verify the working of JK-Flip Flop using
Simulations 25
32
IC-7473
10
 Experiment 1

Verification of Logic Gates

Aim: To study and verify the truth table of following logic gates: AND, OR, NOT, NAND, NOR, XOR

Apparatus/Components Required:

1. Power supply
2. ICs
3. Connecting Wires

Theory: Logic gates are idealized or physical devices implementing a Boolean function, which it performs
a logical operation on one or more logical inputs and produce a single output. Depending on the context, the
term may refer to an ideal logic gate, one that has for instance zero rise time and unlimited fan out or it may
refer to a non-ideal physical device.

The main hierarchy is as follows :-

1. Basic Gates
2. Universal Gates
3. Advanced Gates

Basic Gates:

1. AND gate: - Function of AND gate is to give the output true when both the
inputsare true. In all the other remaining cases output becomes false.
Following table justifies the statement:-

Input A Input B Output

1 1 1

1 0 0

0 1 0

0 0 0
 IC 7408

2. OR gate: - Function of OR gate is to give output true when one of the either inputs
are true. In the remaining case output becomes false. Following table justify the
statement:-

Input A Input B Output

0 0 0
0 1 1
1 0 1
1 1 1

IC 7432
 3. NOT gate: - Function of NOR gate is to reverse the nature of the input. I t
converts true input to false and vice versa. Following table justifies the statement

Input Output

1 0

0 1

IC 7404

Universal gates:

1. NAND gate: - Function of NAND gate is to give true output when one of the
two provided input are false. In the remaining output is true case. Following table
justifies the statement

Input A Input B Output

1 1 0

1 0 1

0 1 1

0 0 1
 IC 7400

2. NOR gate: - NOR gate gives the output true when both the two provided input are
false. In all the other cases output remains false. Following table justifies the
statement: -

Input A Input B Output

1 1 0

1 0 0

0 1 0

0 0 1

IC 7402
Advanced Gates:
1. XOR gate:- The function of XOR gate is to give output true only when both theinputs are
true. Following table explains this: -

Input A Input B Output

1 1 0

1 0 1

0 1 1

0 0 0

IC 74136

Circuit Description:

 Place the IC trainer kit on a stable surface, and ensure it is properly connected to a power supply.

 Use the appropriate ICs for the logic gates (AND, OR, NOT, NAND, NOR, XOR) you wish to verify.
These ICs can be 7400 series (TTL logic) or 4000 series (CMOS logic), depending on availability.

 Connect the Vcc pin of each IC to the +5V (for TTL) or +3.3V/+5V (for CMOS) power supply
terminal on the trainer kit.

 Connect the ground (GND) pin of each IC to the ground terminal on the trainer kit.
ICs Description:

Gates IC NO.

AND 7408

OR 7432

NAND 7400

NOR 7402

NOT 7404

XOR 74136

Procedure:

1. Connections are made as per the Digital Circuit discussed in previous section.
2. The observation table is obtained for the all-possible input combinations

Results: The truth tables for the following logic gates were verified using the IC trainer kit. The observed
outputs matched the expected outputs for each logic gate, confirming their correct operation.

Circuit Connection:
Observation Table:

Input Output

A B AND OR NOT NAND NOR XOR

0 0 0 0 1 1 1 0

0 1 0 1 1 1 0 1

1 0 0 1 0 1 0 1

1 1 1 1 0 0 0 0

Conclusion: The observation table validate the outcomes of the truth table for given logic gates.
 Experiment 2

Conversion Between Binary and Gray Code

Aim: To implement Binary to Gray / Gray to Binary code converter

Apparatus/Components Required:
• C 7486 (Quad 2-input XOR gate)

• IC 7404 (Hex Inverter NOT gate)

• Connecting wires, Power supply (5V DC).

Theory:

Gray code is a non-weighted code. It is not an arithmetic code. It has a very special feature
that only one bit in the gray code will change, each time the decimal number is incremented.
As only one-bit changes at a time, the gray code is called „unit distance code‟. The gray code
is cyclic code is also exhibiting the reflective property.

Steps for converting Binary to Gray code

• 1) Record the MSB bit as it is.

• 2) Add this bit to the next bit, recording the sum and neglecting the carry bit(EX-OR
operation).

• 3) Record Successive sum until completion of all bits.

Circuit Description:

Logic Diagram: Logic Diagram:

Binary to Gray Code Convertor Gray to Binary Code Convertor

ICs Description:

1 :- IC 7486 (X-OR Gate) 2 :- IC 7404(NOT Gate)

Procedure:

Binary to Gray Code Converter:

1. Setup the Breadboard: Place the IC 7486 on the breadboard and connect
the Vcc and GND pins to the power supply.
2. Input Connections: Use switches to provide the binary input bits (B3, B2, B1, B0).
3. Gray Code Calculation:
◦ Connect B3 directly to G3.
◦ Connect B2 and B3 to an XOR gate to get G2 (G2 = B3 ➀ B2).
◦ Connect B1 and B2 to an XOR gate to get G1 (G1 = B2 ➀ B1).
◦ Connect B0 and B1 to an XOR gate to get G0 (G0 = B1 ➀ B0).
4. Output Observation: Connect LEDs to the outputs (G3, G2, G1, G0)
through resistors to visualize the Gray code.
 Gray to Binary Code Converter:

1. Setup the Breadboard: Place the IC 7486 on the breadboard and connect
the Vcc and GND pins to the power supply.
2. Input Connections: Use switches to provide the Gray code input bits (G3,
G2, G1, G0).
3. Binary Code Calculation:
◦ Connect G3 directly to B3.
◦ Connect G2 and B3 to an XOR gate to get B2 (B2 = G2 ➀ B3).
◦ Connect G1 and B2 to an XOR gate to get B1 (B1 = G1 ➀ B2).
◦ Connect G0 and B1 to an XOR gate to get B0 (B0 = G0 ➀ B1).
4. Output Observation: Connect LEDs to the outputs (B3, B2, B1, B0)
through resistors to visualize the binary code.

Circuit Connection:
Observation Table:

Binary To Gray Code:

| Binary Input | | Gray Code Output |

B2 B1 B0 G2 G1 G0
0 0 0 0 0 0

0 0 1 0 0 1

0 1 0 0 1 1

0 1 1 0 1 0

1 0 0 1 1 0

1 0 1 1 1 1

1 1 0 1 0 1

1 1 1 1 0 0

Gray Code to Binary:

| Gray Code Input | | Binary Output |

G2 G1 G0 B2 B1 B0
0 0 0 0 0 0

0 0 1 0 0 1

0 1 1 0 1 0

0 1 0 0 1 1

1 1 0 1 0 0

1 1 1 1 0 1

1 0 1 1 1 0

1 0 0 1 1 1

Conclusion: Thus, result for Binary-to-gray conversion and that for Gray-To-Binary is verified
 Experiment 3

Half Adder & Full Adder using Logic gates

Aim: To implement Half Adder & Full Adder using Logic gates.

Apparatus/Components Required:
Connecting wires, Power supply (5V DC).

• IC 7408 (Quad 2-input AND gate)

• IC 7486 (Quad 2-input XOR gate)
• IC 7432 (Quad 2-input OR gate) - for full adder

Theory:
Half Adder: A half adder is a combinational logic circuit that adds two single-bit binary
numbers. It produces a sum and a carry output. The sum is the XOR of the two input bits, and
the carry is the AND of the two input bits.

Full Adder: A full adder is a combinational logic circuit that adds three single-bit binary
numbers (two significant bits and a carry bit from the previous lower significant position). It
produces a sum and a carry output. The sum is the XOR of the three input bits, and the carry
is determined by the combination of the inputs using AND & OR gates.

Half Adder:

• Sum (S) = A ➀ B
• Carry (C) = A · B
Full Adder:

• Sum (S) = A ➀ B ➀ Cin

• Carry (Cout) = (A · B) + (Cin · (A ➀ B))

Circuit Description & Connection:

Half Adder:
 Full Adder:

ICs Description:
1 . IC 7408: Quad 2-input AND gate.
2 . IC 7486: Quad 2-input XOR gate.
3 . IC 7432: Quad 2-input OR gate.

Procedure:

Half Adder:
1. Setup the Breadboard: Place the IC 7486 (XOR gate) and IC 7408 (AND gate) on the breadboard
and connect the Vcc and GND pins to the power supply.
2. Input Connections: Use switches to provide the inputs A and B.
3. Sum Calculation: Connect A and B to an XOR gate (IC 7486) to get the Sum (S=A➀B).
4. Carry Calculation: Connect A and B to an AND gate (IC 7408) to get the Carry (C=A·B).
5. Output Observation: Connect LEDs to the Sum and Carry outputs through resistors to visualize the
results.

Full Adder:
1. Setup the Breadboard: Place the IC 7486 (XOR gate), IC 7408 (AND gate), and IC 7432 (OR
gate) on the breadboard and connect the Vcc and GND pins to the power supply.
2. Input Connections: Use switches to provide the inputs A, B, and Cin.
3. Sum Calculation:
◦ Connect A and B to an XOR gate to get the intermediate sum (S1 = A ➀ B).
◦ Connect S1 and Cin to another XOR gate to get the final Sum (S = S1 ➀ Cin).
 4. Carry Calculation:
◦ Connect A and B to an AND gate to get the intermediate carry (C1 = A · B).
◦ Connect S1 and Cin to another AND gate to get the second intermediate carry (C2 = S1 ·
Cin).
◦ Connect C1 and C2 to an OR gate to get the final Carry (Cout = C1 + C2).
5. Output Observation: Connect LEDs to the Sum and Carry outputs through resistors to visualize
the results.

Observation Table:

Half Adder: Full Adder:

A B Sum(S) Carry(C) A B Cin Sum(S) Carry(C)

0 0 0 0 0 0 0 0 0

0 1 1 0 0 0 1 1 0

1 0 1 0 0 1 0 1 0

1 1 0 1 0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Conclusion:

The half adder and full adder circuits successfully perform binary addition for the given inputs, demonstrating the
principles of binary arithmetic and the use of basic logic gates in implementing arithmetic operations in digital circuits.
 Experiment 4

Implementing Even Parity / Odd Parity

Aim: To implement even parity/ odd parity generator

Apparatus/Components Required:
IC 7486 (Quad 2-input XOR gate)
Connecting wires
Power supply (5V DC)

Theory:
Parity Bit: A parity bit is an extra bit included with a binary message to make the total number
of 1s either even (even parity) or odd (odd parity). It is used for error detection in digital
communication systems.

Even Parity: An even parity bit is set to 1 if the number of 1s in the data is odd, making the
total number of 1s even. If the number of 1s is already even, the parity bit is set to 0.

Odd Parity: An odd parity bit is set to 1 if the number of 1s in the data is even, making the
total number of 1s odd. If the number of 1s is already odd, the parity bit is set to 0.

Circuit Description:
An XOR gate can be used to generate parity bits because the XOR operation effectively counts
the number of 1s in the input. The output of an XOR gate is 1 if the number of 1s in the inputs
is odd.

For multiple bits, cascading XOR gates can be used to create a parity generator.

Even Parity Generator: P=A➀B➀C➀D

Odd Parity Generator: P=(A➀B➀C➀D)’

ICs Description:
1: IC 7486: Quad 2-input XOR gate.
Procedure:

Even Parity Generator:

1. Setup the Breadboard: Place the IC 7486 on the breadboard and connect the Vcc
and GND pins to the power supply.
2. Input Connections: Use switches to provide the input bits A, B, C, and D.
3. Parity Calculation:
◦ Connect A and B to the first XOR gate to get an intermediate result X1 (X1 =
A ➀ B).
◦ Connect C and D to the second XOR gate to get another intermediate result
X2 (X2 = C ➀ D).
◦ Connect X1 and X2 to the third XOR gate to get the final Even Parity Bit (P =
X1 ➀ X2).
4. Output Observation: Connect an LED to the parity output through a resistor to
visualize the even parity bit.
Odd Parity Generator:

1. Setup the Breadboard: Place the IC 7486 on the breadboard and connect the Vcc
and GND pins to the power supply.
2. Input Connections: Use switches to provide the input bits A, B, C, and D.
3. Parity Calculation:
◦ Follow the same steps as the even parity generator to get the intermediate
result X3 (X3 = A ➀ B ➀ C ➀ D).
◦ Connect X3 to an inverter (NOT gate) to get the final Odd Parity Bit (P =(X3)’
4. Output Observation: Connect an LED to the parity output through a resistor to
visualize the odd parity bit.
Circuit Connection:

Observation Table:

Even Parity Generator (EPG): Odd Parity Generator (OPG):

A B C EPG A B C OPG
0 0 0 0 0 0 0 1
0 0 1 1
0 0 1 0
0 1 0 1
0 1 0 0
0 1 1 0
0 1 1 1
1 0 0 1
1 0 0 0
1 0 1 0

1 1 0 0 1 0 1 1

1 1 1 1 1 1 0 1

1 1 1 0

Conclusion:

The parity generators successfully produce the correct even or odd parity bit for the given input
combinations, demonstrating the use of XOR gates in implementing parity generation for error detection
in digital communication systems.
 Experiment 5
To implement 2:1 MUX using basic gates

Aim: To implement 2:1 MUX using basic gates

Apparatus/Components Required:
• IC 7408 (Quad 2-input AND gate) Connecting wires, Power supply (5V DC).
• IC 7432 (Quad 2-input OR gate)
• IC 7404 (Hex Inverter/NOT gate)

Theory:

A multiplexer (MUX) is a combinational circuit that selects one of several input signals and
forwards the selected input to a single output line. A 2:1 multiplexer has two data inputs, one
selects input, and one output. The select input determines which data input is connected to the
output.

Circuit Description:

S0 A B Output
0 0 X 0

0 1 X 1

1 X 0 0

1 X 1 1

ICs Description:

IC 7408: Quad 2-input AND gate. IC 7432: Quad 2-input OR gate.

IC 7404: Hex Inverter/NOT gate.

Truth Tables:

AND gate: OR gate:

Input Output Input Output

A B AND A B OR
0 0 0 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1

NOT gate:

Input Output
A NOT
0 1
1 0

Procedure:
1. Setup the Breadboard: Place the IC 7408 (AND gate), IC 7432 (OR gate), and IC
7404 (NOT gate) on the breadboard and connect the Vcc and GND pins to the power
supply.
2. Input Connections: Use switches to provide the input bits I0, I1, and the select input
S.
3. Inverting Select Signal: Connect the select input S to a NOT gate to get S’.
4. AND Operations:
• Connect I0 and S’ to the first AND gate (output = S’.I0)
• Connect I1 and S to the second AND gate (Output = S.I1)
 5. OR Operation: Connect the outputs of the two AND gates to an OR gate to get the
final output Y (Y = (S’. I0) + (S.I1)).
6. Output Observation: Connect an LED to the MUX output through a resistor to
visualize the result.

Circuit Connection:

Observation Table:
S0 A B Output
0 0 X 0

0 1 X 1

1 X 0 0

1 X 1 1

Conclusion:

The 2:1 MUX successfully selects one of the two input signals based on the select input,
demonstrating the use of basic logic gates (AND, OR, NOT) to implement a multiplexer in
digital circuits.
 Experiment 6

Implementing 2:4 Decoder using basic gates

Aim: To implement 2:4 Decoder using basic gates

Apparatus/Components Required:
• IC 7408 (Quad 2-input AND gate) Connecting wires, Power supply (5V DC).
• IC 7404 (Hex Inverter/NOT gate)

Theory:
A decoder is a combinational circuit that converts binary information from the n coded inputs
to a maximum of 2^n unique outputs. A 2:4 decoder has 2 inputs and 4 outputs. Each output
corresponds to one of the combinations of the input bits.

Circuit Description:

ICs Description:
IC 7408: Quad 2-input AND gate. IC 7404: Hex Inverter/NOT gate.

Truth Table:

Input A Input B Output D3 Output D2 Output D1 Output D0

0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
Procedure:
Setup the Breadboard: Place the IC 7408 (AND gate) and IC 7404 (NOT gate) on the
breadboard and connect the Vcc and GND pins to the power supply.
Input Connections: Use switches to provide the input bits A and B.
Inverting Input Signals:
• Connect input A to a NOT gate to get A'.
• Connect input B to another NOT gate to get B'.
AND Operations:
• Connect A' and B' to the first AND gate to get Y0 (Y0 = A' * B').
• Connect A' and B to the second AND gate to get Y1 (Y1 = A' * B).
• Connect A and B' to the third AND gate to get Y2 (Y2 = A * B').
• Connect A and B to the fourth AND gate to get Y3 (Y3 = A * B).
Output Observation: Connect LEDs to the outputs Y0, Y1, Y2, and Y3 through resistors to
visualize the results.

Circuit Connection:

Observation Table:

Input A Input B Output D3 Output D2 Output D1 Output D0

0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

Conclusion: The 2:4 decoder successfully decodes the binary input into the corresponding one-hot
output, demonstrating the use of basic logic gates (AND, NOT) to implement a decoder in digital circuits.
 Experiment 7

Implementing and verifying the truth table of Half Adder using 2:4 Decoder

Aim: To implement and verify the truth table of Half Adder using 2:4 Decoder

Apparatus/Components Required:
• IC 7408 (Quad 2-input AND gate) Connecting wires, Power supply (5V DC).
• IC 7404 (Hex Inverter/NOT gate)
• IC 74139 or IC 74155 (2:4 Decoder)

Theory:
A Half Adder is a combinational circuit that adds two single-bit binary numbers (A and B). It
has two outputs, the Sum (S) and the Carry (C).
Boolean Expressions:

• Sum (S) = A XOR B

• Carry (C) = A AND B

Circuit Description:

A B Q3 Q2 Q1 Q0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

ICs Description:

IC 7408: Quad 2-input AND gate. IC 7404: Hex Inverter/NOT gate.

IC 74139 or IC 74155: 2:4 decoder

Truth Table:

A B Sum(S) Carry(C)
0 0 0 0 Boolean Expressions:
• Sum (S) = A XOR B
0 1 1 0 • Carry (C) = A AND B
1 0 1 0 A 2:4 decoder can be used to generate
the required outputs for the Half Adder.
1 1 0 1

Procedure:

Setup the Breadboard: Place the IC 74139 or IC 74155 (2:4 Decoder), IC 7408 (AND gate),
and IC 7404 (NOT gate) on the breadboard and connect the Vcc and GND pins to the power
supply.
Input Connections: Use switches to provide the input bits A and B to the decoder.
Decoder Outputs:
• The decoder will provide four outputs based on the input combinations (A and B).
• The outputs will be:
◦ D0 (00)
◦ D1 (01)
◦ D2 (10)
◦ D3 (11)
Sum Calculation:
• Sum (S) can be obtained by combining the outputs D1 and D2.
• Connect D1 and D2 to an OR gate to get the Sum (S = D1 + D2).
Carry Calculation:
• Carry (C) is directly given by the output D3.
Output Observation:
• Connect LEDs to the Sum and Carry outputs through resistors to visualize the results.
Circuit Connection:

Observation Table:

Input A Input B Output Output Output Output Sum(S) Carry(c)

D3 D2 D1 D0
0 0 0 0 0 1 0 0
0 1 0 0 1 0 1 0
1 0 0 1 0 0 1 0
1 1 1 0 0 0 0 1

Conclusion: The Half Adder circuit using the 2:4 Decoder successfully generates the correct Sum
and Carry outputs for each combination of the input bits, verifying the truth table of the Half
Adder.
 Experiment 8

Working of J.K. Flip-Fop

Aim: To study and verify the working of JK-Flip Flop using IC-7473/ D-Flip Flop using IC-
7474

Apparatus/Components Required:
• IC 7473 (Dual J-K Flip-Flop) Connecting wires, Power supply (5V DC).
• IC 7474 (Dual D Flip-Flop)

Theory:
JK Flip-Flop: A JK Flip-Flop is a sequential logic circuit with two inputs, J and K, and one
output, Q. It can operate in three modes: set, reset, and toggle, depending on the input
conditions.

D Flip-Flop: A D Flip-Flop has one data input (D) and one clock input (CLK). It captures the
value of the D input at a particular instance of the clock pulse and outputs this value until the
next clock pulse.

Circuit Description:

JK Flip-Flop D Flip-Flop

ICs Description:
IC 7473(Dual J-K Flip-Flop) IC 7474(Dual D Flip-Flop)
Truth Table (JK Flip-Flop):

J K Q(n) Q(n+1) State

0 0 0 0
Hold
0 0 1 1
0 1 0 0
Reset
0 1 1 0
1 0 0 1
Set
1 0 1 1
1 1 0 1
Toggle
1 1 1 0

Truth Table (D Flip-Flop):

D Q(n) Q(n+1) State

0 0 0
Reset
0 1 0
1 0 1
Set
1 1 1

Procedure:
JK Flip-Flop using IC 7473:

1. Setup the Breadboard:

◦ Place the IC 7473 on the breadboard.
◦ Connect Vcc to Pin 16 and GND to Pin 8.
◦ Connect push-button switches to the J1 (Pin 1), K1 (Pin 2), and CLK1 (Pin 3)
inputs.
◦ Connect LEDs to the Q1 (Pin 6) and Q1' (Pin 7) outputs through resistors.
2. Input Connections:

◦ Connect the J1 and K1 inputs to the push-button switches to provide the

desired logic levels (0 or 1).
 ◦ Connect the clock input CLK1 to a clock pulse generator or manually provide
clock pulses using a push-button switch.
3. Observe the Outputs:

◦ Press the J and K switches according to the truth table and observe the
changes in the output Q1.
◦ Verify the operation of the flip-flop by observing the LED states.
D Flip-Flop using IC 7474:

1. Setup the Breadboard:

◦ Place the IC 7474 on the breadboard.
◦ Connect Vcc to Pin 14 and GND to Pin 7.
◦ Connect push-button switches to the D1 (Pin 2) and CLK1 (Pin 3) inputs.
◦ Connect LEDs to the Q1 (Pin 5) and Q1' (Pin 6) outputs through resistors.
2. Input Connections:

◦ Connect the D1 input to a push-button switch to provide the desired logic level
(0 or 1).
◦ Connect the clock input CLK1 to a clock pulse generator or manually provide
clock pulses using a push-button switch.
3. Observe the Outputs:
◦ Press the D switch and provide a clock pulse to the CLK input.
◦ Verify the operation of the flip-flop by observing the LED states.
Circuit Connection:

Observation Table:

JK Flip-Flop:

J K Q(n) Q(n+1) State

0 0 0 0
Hold
0 0 1 1
0 1 0 0
Reset
0 1 1 0
1 0 0 1
Set
1 0 1 1
1 1 0 1
Toggle
1 1 1 0
D Flip-Flop:

D Q(n) Q(n+1) State

0 0 0
Reset
0 1 0
1 0 1
Set
1 1 1

Conclusion: By performing this experiment, we have successfully studied and verified the
working of JK Flip-Flop using IC 7473 and D Flip-Flop using IC 7474. The observed outputs
matched the expected results based on the truth tables.