「Course」

RISC-V Computer System Integration

「 Lecture 3」Rocket Computer System:
Introduction and System Modification
Hoang Trong Thuc
2022/11
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1. Introduction
Outline
2. System architecture
3. Git clone and prepare
4. Make the system
5. Program Arty-A7
6. Using IntelliJ IDEA-IC
7. Modifying system by Scala config
8. Practice: system modification 2
1. Introduction
Outline
2. System architecture
3. Git clone and prepare
4. Make the system
5. Program Arty-A7
6. Using IntelliJ IDEA-IC
7. Modifying system by Scala config
8. Practice: system modification 3
 1. Introduction (1/4) Rocket core
Rocket core
• Github: https://github.com/chipsalliance/rocket-chip
• Document: https://chipyard.readthedocs.io/en/stable/Generators/Rocket-Chip.html
https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.pdf
Rocket is the most popular
processor in RISC-V community.

Rocket is a 5-stage in-of-order

processor. Its pipeline architecture:

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 1. Introduction (2/4) Chipyard
Chipyard library
• Github: https://github.com/ucb-bar/chipyard
• Document: https://chipyard.readthedocs.io/en/stable/
You can see that there are many
processors ready for use.
We will use the Rocket core in here.

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 1. Introduction (3/4) Arty-A7 FPGA
Arty-A7 FPGA
• Link: https://digilent.com/reference/programmable-logic/arty-a7/start

We will use Arty-A7 FPGA for this course

• A Xilinx FPGA
• Relatively cheap
• License-free to build (license is provided by
Digilent, not Xilinx)
• Convenient with PMOD headers (easy-to-use
SD-card, Flash, etc.)
• Has two versions of FPGA: 35T and 100T
(be careful, you have to check the FPGA
version before compiling)

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 1. Introduction (4/4) FPGA-shells
FPGA-shells library
• Github: https://github.com/sifive/fpga-shells

Common FPGA IPs

can be found in here.
We will use the Arty’s
memory IP in here.

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1. Introduction
Outline
2. System architecture
3. Git clone and prepare
4. Make the system
5. Program Arty-A7
6. Using IntelliJ IDEA-IC
7. Modifying system by Scala config
8. Practice: system modification 8
 2. System architecture (1/9) Processor
In this course, we will working with an example of Rocket computer system at here:
• Github: https://github.com/uec-hanken/RISCVConsole

Coreplex
RISC-V 32/64
IMAFDC

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2. System architecture (2/9) Memory
SDRAM DDR3
Controller Controller
For DE2 For ArtyA7

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 2. System architecture (3/9) UART

UART Controller
- TX and RX channels
- 8-entry FIFO with interrupts

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 2. System architecture (4/9) SD-card

SPI Controller
- To communicate with SD cards
- Read the partition and execute

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 2. System architecture (5/9) GPIO

GPIO Controller
- Input and Output registers
- Masked interrupts supported

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 2. System architecture (6/9) Interrupt

Interrupt Controllers
- Platform Interrupts (External)
- Core Local Interrupts (Time & Software)

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 2. System architecture (7/9) SPI

SPI Controller (as ROM)

- Mapped to main memory to act as
an optional program

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 2. System architecture (8/9) Boot ROM

ROM
- Contains the SD load boot
- Always fixed

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 2. System architecture (9/9) Debug module

Debug
- JTAG-capable debug module
- Interrupts processor and debug

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1. Introduction
Outline
2. System architecture
3. Git clone and prepare
4. Make the system
5. Program Arty-A7
6. Using IntelliJ IDEA-IC
7. Modifying system by Scala config
8. Practice: system modification 18
3. Git clone and prepare (1/4) $ git clone and folder structure
To clone the project: $ git clone https://github.com/uec-hanken/RISCVConsole.git
$ cd RISCVConsole/
$ ./update.sh

The folder structure: FPGA makefile

Supported FPGA boards

chipyard library:
provides processors
Scala sources fpga-shells library:
provides FPGA IPs

our Scala sources

Software sources
after boot software sources

boot ROM sources 19

 3. Git clone and prepare (2/4) Prepare for Arty-A7-35T
If you use the Arty-A7-100T version, please skip the next two steps.
If you use the Arty-A7-35T version, please do the following:

$ vi hardware/fpga-shells/xilinx/arty_a7_100/tcl/board.tcl

Change from here: To here:

(type i to write and esc to release) (type :wq to save and exit)

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 3. Git clone and prepare (3/4) Prepare for Arty-A7-35T
$ vi hardware/fpga-
shells/src/main/scala/ip/xilinx/arty100tmig/arty100tmig.scala

Change from here: To here:

(type i to write and esc to release) (type :wq to save and exit)

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 3. Git clone and prepare (4/4) Prepare Arty-A7 license
Arty-A7 license is free. You can download and install the Arty-A7 license to Vivado.
Download the link from the Digilent website.
Guide to install the license:
https://digilent.com/reference/programmable-logic/guides/installing-vivado-and-vitis

1. Extract the ZIP file

2. Copy all the content in
new/board_files
3. Paste them to
Xilinx/Vivado/2022.1
/data/boards/board_f
iles/

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1. Introduction
Outline
2. System architecture
3. Git clone and prepare
4. Make the system
5. Program Arty-A7
6. Using IntelliJ IDEA-IC
7. Modifying system by Scala config
8. Practice: system modification 23
 4. Make the system (1/9) Makefile in fpga folder
Makefile SBT (.scala) FIRRTL (.fir) FPGA (.v) FPGA (.bit)

At RISCVConsole/fpga/ArtyA7100T/Makefile:

At RISCVConsole/variables.mk:

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 4. Make the system (2/9) Equivalent in Scala config
Makefile SBT (.scala) FIRRTL (.fir) FPGA (.v) FPGA (.bit)

At RISCVConsole/hardware/riscvconsole/src/ At RISCVConsole/fpga/
ArtyA7100T/Makefile:
main/scala/riscvconsole/RVCConfig.scala:

At RISCVConsole/variables.mk:

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 4. Make the system (3/9) Scala structure
Makefile SBT (.scala) FIRRTL (.fir) FPGA (.v) FPGA (.bit)

FPGA Shell folder FPGA folder

RVC. System RVC. Subsystem
GPIO Pins
UART Pins
● General Purpose IO ● TileLink Buses
SPI Pins
● UART ● Debug Module
I2C Pins
● SPI Flash ● Boot ROM
DDR Ports
● I2C ● Core Local Interrupts
SDRAM Ports
● SDRAM/DDR ● Platform Level Interrupt
CODEC Ports
● TL Serial (For simulations) Controller
JTAG Pins
● FFT/CODEC ● Coreplex
Other Ports
● Any additional peripherals ○ Rocket
○ BOOM

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 4. Make the system (4/9) $ make default
Makefile SBT (.scala) FIRRTL (.fir) FPGA (.v) FPGA (.bit)

Now, to make the system, from the RISCVConsole, go to the Arty build folder:
$ cd fpga/ArtyA7100T/

Export the RISC-V toolchain to the PATH:

$ export RISCV=/opt/riscv
$ export PATH=$RISCV/bin/:$PATH
Export Vivado to the PATH:
$ export PATH=/opt/Xilinx/Vivado/2022.1/bin/:$PATH

For the compilation:

$ make default
This will compile Scala to Verilog (also compile the boot ROM C/C++ sources)

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 4. Make the system (5/9) $ make default
Makefile SBT (.scala) FIRRTL (.fir) FPGA (.v) FPGA (.bit)
After $ make default, the
generated-src folder is created:
Inside the generated-src folder, there are many files:
Verilog files, FIRRTL files, temporary Java files, boot ROM files, device tree, etc.

Some
important files

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 4. Make the system (6/9) Verilog files
Makefile SBT (.scala) FIRRTL (.fir) FPGA (.v) FPGA (.bit)

Top file:
riscvconsole.fpga.ArtyA7
Top.ArtyA7Config.top.v

File that contains all

the memories used in
the system:
riscvconsole.fpga
.ArtyA7Top.ArtyA7
Config.top.mems.v

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 4. Make the system (7/9) Verilog files
Makefile SBT (.scala) FIRRTL (.fir) FPGA (.v) FPGA (.bit)
Boot ROM file:
riscvconsole.fpga.ArtyA7Top.
ArtyA7Config.rom.v Other Verilog files:
• EICG_wrapper.v
• plusarg_reader.v

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 4. Make the system (8/9) Device tree file
Makefile SBT (.scala) FIRRTL (.fir) FPGA (.v) FPGA (.bit)

Device tree file:

(needed for software)
riscvconsole.fpga.ArtyA7Top.
ArtyA7Config.dts

Its binary version:

riscvconsole.fpga.ArtyA7Top.
ArtyA7Config.dtb

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 4. Make the system (9/9) $ make bit
Makefile SBT (.scala) FIRRTL (.fir) FPGA (.v) FPGA (.bit)

The $ make default is just for generating Verilog.

Now, to compile the FPGA:
$ make bit
This will compile Verilog to .bit file for programming the FPGA

After $ make bit, you can find the .bit file for programming the FPGA in:
generated-src/riscvconsole.fpga.ArtyA7Top.ArtyA7Config/obj/

*Note: if the $ make bit has an

error related to timing, it is fine as
long as the .bit file was generated.
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1. Introduction
Outline
2. System architecture
3. Git clone and prepare
4. Make the system
5. Program Arty-A7
6. Using IntelliJ IDEA-IC
7. Modifying system by Scala config
8. Practice: system modification 33
 5. Program Arty-A7 (1/10) Prepare SD-card
Before programming the Arty-A7 FPGA board,
you must prepare the software on the SD card.

First, you’ll need the gptfdisk tool to format the SD card.

If you don’t have it already, do the following to install it:
From your home folder:
$ git clone https://github.com/tmagik/gptfdisk.git
$ cd gptfdisk/
$ make -j`nproc`

Put the SD-card to your PC, then:

Go to gptfdisk folder:
$ cd gptfdisk/
$ sudo ./gdisk /dev/sd?
The ? points to the SD card. For example: /dev/sdb

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 5. Program Arty-A7 (2/10) Prepare SD-card
Some commands to use while in the gptfdisk tool:
$ p : print partitions information
$ d : delete partition
$ n : create new partition
$ w : write partition
$ q : exit gptfdisk

You’ll need to format the SD card to look like this:

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 5. Program Arty-A7 (3/10) Prepare SD-card
Example commands:
$ sudo ./gdisk /dev/sdb
$ d
$ n
$ (Enter)
$ +1024
$ 5202
$ p
$ w
$ y

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 5. Program Arty-A7 (4/10) Prepare software
Now, prepare the after-boot software:
From your RISCVConsole folder:
$ cd RISCVConsole/
Go to:
$ cd software/RISCVConsoleCode/
Remember to have the RISC-V toolchain available in the PATH:
$ export PATH=/opt/riscv/bin/:$PATH
Finally, compile the software:
$ make bin

Terminal after $ make bin :

After $ make bin, the compiled software are under the build folder:

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 5. Program Arty-A7 (5/10) Prepare software
Now, to write the compiled software to the SD card:
From your RISCVConsole/software/RISCVConsoleCode folder:
$ sudo dd if=./build/out.bin of=/dev/sd?1 conv=fsync bs=4096
Again, the ? points to the SD card.
For example: $ sudo dd if=./build/out.bin of=/dev/sdb1 conv=fsync bs=4096
After $ sudo dd :

Now, remove the SD card Remember to connect

from your PC. the microUSB-to-USB to
Put it in the PMOD-SD-card your PC.
and connect to the Arty-A7.
Like this:

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 5. Program Arty-A7 (6/10) Program the Arty-A7
To program the board, open Vivado: Open hardware manager:

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 5. Program Arty-A7 (7/10) Program the Arty-A7
Open target → Auto connect :

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 5. Program Arty-A7 (8/10) Program the Arty-A7
Right-click on the xc7a100t (1) → Program device…

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 5. Program Arty-A7 (9/10) Program the Arty-A7
Browse to the ArtyA7Top.bit under
RISCVConsole/fpga/ArtyA7100T/generated-
src/riscvconsole.fpga.ArtyA7Top.ArtyA7Config/obj folder

Finally, OK then Program. 42

 5. Program Arty-A7 (10/10) UART terminal
To open the UART terminal:
$ sudo minicom -b 115200 -D /dev/ttyUSB?
Where ? points to the Arty-A7 microUSB connection.
For example: $ sudo minicom -b 115200 -D /dev/ttyUSB1
Printing in the UART terminal:
Reset button

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1. Introduction
Outline
2. System architecture
3. Git clone and prepare
4. Make the system
5. Program Arty-A7
6. Using IntelliJ IDEA-IC
7. Modifying system by Scala config
8. Practice: system modification 44
6. Using IntelliJ IDEA-IC (1/3) Download and install
To write/modify Scala sources efficiently,
we need an IDE (Integrated Development Environment) tool.
• SBT is the compiler for Scala • IntelliJ IDEA-IC is the GUI for SBT
→ IntelliJ IDEA-IC for Scala is like Visual Studio for C++

To install IntelliJ IDEA-IC,

just follow their website:
https://www.jetbrains.com/idea/
They have a free version: Community

The first time it opens,

remember to install
the Scala plugin.
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 6. Using IntelliJ IDEA-IC (2/3) Import project
To import existing project, Open: Choose the project to import:

It could take a while for the

importing to finish. 46
 6. Using IntelliJ IDEA-IC (3/3) Import project

Now all the variables

are properly linked.
You can:
• Find usages
• Go to

When it
finishes.

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1. Introduction
Outline
2. System architecture
3. Git clone and prepare
4. Make the system
5. Program Arty-A7
6. Using IntelliJ IDEA-IC
7. Modifying system by Scala config
8. Practice: system modification 48
 7. Modifying system by Scala config (1/10) Peripheral
At RISCVConsole/hardware/riscvconsole/src/
main/scala/riscvconsole/RVCConfig.scala:

UART, GPIO, SPI and I2C added

(Debug, CLINT, PLIC, error devices and
ROM are mandatory for the system)
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 7. Modifying system by Scala config (2/10) Peripheral
At RISCVConsole/hardware/riscvconsole/src/ For example: remove
main/scala/riscvconsole/RVCConfig.scala: I2C from the system.

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 7. Modifying system by Scala config (3/10) Processor
At RISCVConsole/hardware/riscvconsole/src/
main/scala/riscvconsole/RVCConfig.scala:

WithNMedCores(1) ++
● Supports VM
● Suitable for Linux booting
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 7. Modifying system by Scala config (4/10) Processor
At RISCVConsole/hardware/riscvconsole/src/
main/scala/riscvconsole/RVCConfig.scala:

Change to: WithNSmallCores (1) ++

● Does not support VM

● Usually for Micontrollers

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 7. Modifying system by Scala config (5/10) Processor
At RISCVConsole/hardware/riscvconsole/src/
main/scala/riscvconsole/RVCConfig.scala:

Change the number from (1) to (2)

will increase the number of
processors accordingly
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 7. Modifying system by Scala config (6/10) Addressing
At RISCVConsole/hardware/riscvconsole/src/
main/scala/riscvconsole/RVCConfig.scala:

The system is 64-bit by default.

So if you disable the WithRV32 ++ line,
you’ll get the 64-bit system back.
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 7. Modifying system by Scala config (7/10) FPU
At RISCVConsole/hardware/riscvconsole/src/
main/scala/riscvconsole/RVCConfig.scala:

Then, right-click on the

WithNMedCores and Go to:

It’ll lead you to the

Configs.scala file:
To bring back the FPU, first, disable
the WithoutFPU() ++ line.
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7. Modifying system by Scala config (8/10) FPU

Change from here: To here:

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7. Modifying system by Scala config (9/10) L1 caches
To reduce the L1 caches, for example, from the Configs.scala file:

Change from here: To here:

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7. Modifying system by Scala config (10/10) L1 caches
The result after that:

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1. Introduction
Outline
2. System architecture
3. Git clone and prepare
4. Make the system
5. Program Arty-A7
6. Using IntelliJ IDEA-IC
7. Modifying system by Scala config
8. Practice: system modification 59
 8. Practice: system modification (1/1)
Exercise 1:
Try these combinations ($ make default → $ make bit) and report the resources in
Arty-A7:
• RV32IMAC small single-core Rocket
• RV64GC small single-core Rocket
• RV32IMAC medium single-core Rocket
• RV64GC medium single-core Rocket
• RV32IMAC small single-core Rocket with reduced caches ($I=1KB, $D=1KB)
• RV64GC medium single-core Rocket with increased caches ($I=64KB, $D=64KB)

Exercise 2:
Try multiple configurations to see if the Arty-A7 can support dual-core Rocket.
And check on both 35T and 100T versions of the Arty-A7. So the questions are:
1. Which configuration will use the most of the Arty-A7-35T?
2. Which configuration will use the most of the Arty-A7-100T?
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THANK YOU

2022/11
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