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    3-RTL Modifications SV

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    studentwelfare.cb2024

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    3-RTL Modifications SV

    Uploaded by

    studentwelfare.cb2024
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    1 views2 pages

    3-RTL Modifications SV

    Uploaded by

    studentwelfare.cb2024

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    Om Namah Shivaya

    Modification in RTL between Verilog and system Verilog

    module RTL_Modifications_SV ;

    ////// NEW OPERATORS////


    // +=, -=, == used similar to C //

    ///// LOOP STATEMENTS ////


    // while, do-while, break, continue, enhanced 'for' loop, 'foreach'//

    int a[4];
    initial
    begin
    $display("--------------FOR LOOP---------------------------------------------------");
    for(int i=0;i<5;i++) $display("\t Value of i = %0d",i);
    $display("-----------------------------------------------------------------");

    $display("--------------FOREACH LOOP---------------------------------------------------");
    foreach(a[i]) a[i] = i;
    foreach(a[i]) $display("\tValue of a[%0d]=%0d",i,a[i]);
    $display("-----------------------------------------------------------------");
    end

    // Labeling: In Verilog, we label only in the begining of block eg :


    // begin : a_label ..
    // In system verilog we can label any procedural statement and this label may be put in begining and
    end.
    // module MyModule ...
    // ...
    // endmodule : MyModule

    // PORT CONNECTION SHORT forms


    // In verilog we use Design DUT ( .Clock(Clock), .Reset(Reset), .Data(Data), .Q(Q) );
    // System verilog :
    // Design DUT ( .Clock, .Reset, .Data, .Q ); (If signal names in module and top level are same, no
    need to repeat
    // Design DUT ( .* );

    // SYNTHESIS IDIOMS : 3 key words always_comb, always_ff, always_latch

    // always_comb is used to describe combinational logic.


    // It implicitly creates a complete sensitivity list by looking at the variables and nets that are read in
    the process, just like always @* in Verilog-2001.
    // it implicitly puts its sensitivity list at the end of the process, so that it is evaluated just once at time
    zero and therefore all its outputs
    // take up appropriate values before simulation time starts to progress.

    // always_ff and always_latch are used for infering latches and flipflops.
    /*
    always_ff @(posedge clock or posedge reset)
    if (reset)
    q <= 0;
    else if (enable)
    q++;
    */

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