THE UNIVERSITY OF BRITISH COLUMBIA

Department of Electrical and Computer Engineering

ELEC 401 – Analog CMOS Integrated Circuit Design
Take-Home Midterm Exam
Due: Monday, October 18th, 2021 at 11:59 pm

This is an open book take-home exam and calculators are allowed. Please attempt to answer all
problems. A blank sheet will not receive any marks! Please do not consult and/or discuss the
questions and/or your solutions with anyone. Your solutions/answers should be based on your
individual effort! Please also note that each question has its own transistor parameters.

Good luck!

This exam consists of 6 − 6/6 (= 5) questions and including the cover page has 6+6(=12)
pages. Please check that you have a complete copy.

# MAX GRADE
1 20
Surname First name 2 20
3 20
4 20
READ THIS

Student Number
5 20
TOTAL 100

IMPORTANT NOTE:

Candidates guilty of any of the following, or similar, dishonest practices shall be liable to disciplinary
action:
Speaking or communicating with other candidates or non-candidates regarding the exam questions.
Purposely exposing their solution to the view of other candidates.
The plea of accident or forgetfulness shall not be received.

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1. In the following circuit assume that the bulks of the two NMOS transistors are
connected to ground, and furthermore assume that the current source is ideal with Ibias=4 mA,
and for both transistors we have λ = 0, γ = 1 V1/2, 2ΦF=0.64 V, VTH0 = 0.4 V, µnCox = 500 µA/V2,
and (W/L) = 100.
a) Find the voltage of node X? [8 marks]
b) Find the voltage of node Y? [10 marks]
c) If we were to implement the current source with a single PMOS transistor which
would had a effective voltage of 0.5 (i.e., VSG-|VTHP| = 0.5 V), then, what was the
minimum required VDD for the circuit to operate properly? [2 marks]

VDD

Ibias

M2

M1

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Voltage of Node X:______________, Voltage of Node Y: ______________

Minimum required VDD = ____________

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2. In the following circuit, assume that VDD = 3V and the total dc power consumption of the
circuit is 2.25mW, and the dc level of the output is 1.5 V. Furthermore, assume that M1 is
operating in saturation region, and for transistors we have λ = 0, VTH0(NMOS)= 0.5V, VTH0(PMOS)= –
0.5V, µnCox = 200 µA/V2, µpCox=100 µA/V2, and (W/L)1 =80.

VDD

M2

Vout
M1

Vin RL

Vbias

a) Find the required Vbias for which the dc bias current of M1 is 0.5 mA. [4 marks]
b) Find (W/L)2. [4 marks]
c) Find RL. [4 marks]
d) What is the small-signal gain of the circuit? [4 marks]
e) Is the assumption that M1 is operating in saturation correct. If so, why? [2 marks]
f) What is the maximum peak-to-peak symmetric signal swing of the output? [2 marks]

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For your convenience the circuit and its parameters are duplicated below:
VDD = 3V and the total dc power consumption of the circuit is 2.25mW, and the dc level of the
output is 1.5 V. Furthermore, λ = 0, VTH0(NMOS)= 0.5V, VTH0(PMOS)= –0.5V, µnCox = 200 µA/V2,
µpCox=100 µA/V2, and (W/L)NMOS =80.

VDD

M2

Vout
M1

Vin RL

Vbias

Vbias =________________. (W/L)2=______________, RL=__________________

small-signal gain___________________, region of operation of M1=_____________________

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output symmetric peak-to-peak signal swing=____________ ,
3. In the following circuit, assuming that the transistor is biased properly so that it is not
operating in the cut-off region, show that in the small-signal domain, even when λ > 0 and γ > 0
(i.e., in the presence of channel length modulation and body effect), Vout1 and Vout2 are related by:
Vout1/Vout2= −RD/RS. [20 marks].

VDD

RD

Vout1

Vout2
Vsig
RS
Vbias

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7
4. Design the following two-stage amplifier with the schematic shown below and these design
specifications:
 VDD=1.8 V
 Total power consumption of the amplifier is 1.8 mW
 Vbias1 and the level of Vout1 and Vout2 are all 0.9 V
 L=0.25 µm for both transistors
 The output impedance of the circuit, that is the impedance seen at Vout2 is 1.8 kΩ

Assume the following technology parameters:

λ=0, VDD=1.8V, VTH(NMOS) =0.4V, VTH(PMOS) =−0.4V, µnCox=500 µA/V2, µpCox=250 µA/V2.
Furthermore, assume that Vin is a small-signal source.

VDD VDD VDD

Vbias1
R2
Vin
Vout2
M1
M2
Vout1
R1

a) Find R1, R2, W1 and W2. [12 marks]

b) What is the overall gain of the system, i.e., Vout2/Vin. [3 marks]
c) What is the maximum symmetric peak-to-peak output swing. [3 marks]
d) If the input Vin is a small-signal sinusoid, what would be the maximum amplitude of the input
signal for which the circuit operates as expected. [2 marks]

8
W1= __________µm, W2=_________µm, R1=__________kΩ, R2=__________kΩ,

Vout2/Vin=_________V/V, Maximum pea-to-peak symmetric output swing=_______V

Maximum amplitude of the small-signal input sinusoid = __________mV

9
5. Consider the following circuit:
VDD

Vout(t)
M1
Vin(t)
C1

Vbias

The technology parameters are:

λ(NMOS)=0 V-1, γ=0, VDD=3.3 V, VTH(NMOS)=0.5V, µnCox=0.1 mA/V2, and Cox= 5 fF/µm2.

Assume C1 = 2 pF and for the transistor we have: L1= 0.5 µm and W1= 5 µm.
a) If Vbias=0.8 V, what is the region of operation of the transistor and why? [6 marks]
b) If the input signal, Vin(t), is a step function with a small magnitude of 10 mV (i.e., Vin
abruptly changes from 0 V to 10 mV at time t = 0), what is Vout(t) for t ≥ 0? [6 marks]
c) Repeat parts (a) and (b) for Vbias=1.8V. [8 marks]

10
For Vbias=0.8V: Region of operation of M1: ____________, Vout(t)=________________

For Vbias=1.8V: Region of operation of M1: ____________, Vout(t)=________________

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This is intentionally left blank.

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