SDC (Synopsys Design Constraints) checks are part of sanity checks that ensure the correctness

and completeness of constraints specified for the design. SDC files are used in the design process
to define timing constraints, design constraints, and other attributes necessary for ensuring proper
operation.
STA (Static Timing Analysis) Result refers to the outcome of the analysis performed to evaluate
the timing performance of a digital circuit. STA is a method to verify whether a design meets its
specified timing requirements, ensuring that the circuit operates correctly at its intended speed.
Linking Related Checks in the context of sanity checks for digital design refer to verifying that
all design elements are properly connected and associated with their respective libraries,
modules, or files. This ensures that the design can be correctly analyzed, synthesized, or
implemented without missing references or inconsistencies.
Electromigration refers to the movement of metal atoms in a conductor due to high current
density. Over time, this can cause open circuits (due to voids) or short circuits (due to material
accumulation).
IR Drop refers to the voltage drop across a power delivery network (PDN) due to the resistance
(R) of metal wires and the current (I) flowing through them. This results in a lower voltage
reaching the transistors, potentially impacting circuit performance.
What is a Power Plan?
A power plan is the strategy for delivering power (VDD) and ground (VSS) to all parts of the
chip efficiently and reliably, while addressing issues like Electromigration (EM) and IR Drop.

Objective: Ensure a stable power supply to all circuit components without significant voltage
drop or reliability concerns.
Components of the Power Plan:
Rings:

Power and ground rings surround the core of the chip.

Distribute power evenly around the chip and act as primary connection points to power pads.
Stripes:

Vertical or horizontal power lines within the core area.

Distribute power across the chip interior from the rings.
Rails:

Power and ground lines directly connected to standard cells or macros.

Provide local power supply to individual circuit components.
Power Vias:

Vertical connections between metal layers in the design.

Help reduce resistance and provide robust paths for current flow.
Trunks:

Larger power paths that connect rings, stripes, and other elements.
Serve as "main roads" for power distribution.
Diagram Explanation:
The image illustrates a hierarchical view of the power plan:
Rings: Highlighted as outer rectangles around the chip.
Stripes: Shown as internal vertical/horizontal lines.
Rails: Connected to specific blocks or standard cells.
Pads: Entry points for external power sources into the chip.
Trunks: Wider connections distributing power from rings to the internal structures.

What is Floorplanning?
Floorplanning is the initial phase in physical design that determines the physical locations of
macros, standard cells, and I/O pins within the chip area. It is crucial for optimizing
performance, power, and area.

Step-by-Step Process (Flow Diagram):

Bind the Netlist with Physical Library:

The netlist (logical design) is linked with the physical library, which contains layout information
about standard cells and macros.
Create Initial Core:

Define the chip's core dimensions and aspect ratio, which forms the working area for component
placement.
Create the I/O Pin Placement and Pad Ring:

Place the input/output pins and surround the core with a pad ring to connect external signals.
Place the Macros or Standard Cells:

Position the macros (large functional blocks) and standard cells in an organized manner,
considering connectivity and power distribution.
Create Placement Blockages:

Define restricted areas where cells or blocks cannot be placed, ensuring sufficient space for
routing or other constraints.
Specify Power and Ground Nets:

Define the power (VDD) and ground (VSS) distribution network for the design.
Create Power and Macros Rings:

Generate power rings for macros and the overall design for stable power distribution.
Create Power, Ground Nets:

Extend the power and ground connections to the entire design.

Route Power and Ground Nets:

Route the power and ground lines across the design to ensure accessibility for all components.
Check Violations in Floorplan:

Verify the floorplan for issues like overlaps, insufficient routing space, or unconnected power
rails.
Is Floorplan OK?:

If the floorplan meets the design criteria, proceed to placement; otherwise, revisit earlier steps.

Placement
Definition: It is the process of assigning locations to all standard cells (logic gates) on the die
(silicon chip).
Purpose: Ensures that the design adheres to performance, area, and power constraints.
Components in the Slide:
Left Diagram
Site Rows: Horizontal rows where standard cells can be placed.
Macros: Larger circuit blocks, such as memory or functional units, that are predefined and placed
manually or by the tool.
EndCap Cells: Special cells placed at the edges of standard cell rows to ensure design rule
compliance.
WellTap Cells: Cells used to prevent latch-up by connecting the substrate to the power supply or
ground.
IO Buffers and IO Ports: Elements for communication between the chip and the outside world.
Antenna Diodes: Used to mitigate antenna effects during fabrication.
Right Diagram
Placement Steps:

Input Information: Includes the netlist (logical connectivity of cells), floorplanning data, and
libraries (logical and physical characteristics of cells).
Global Placement: A rough placement ensuring cells are distributed evenly without considering
detailed constraints.
Detailed Placement: Fine-tunes the placement to meet timing, power, and routing requirements.
Placement Optimization: Adjusts placement to improve performance, reduce area, and meet
constraints.
Output Information:

Physical layout of the design.

Locations of each cell.
Timing and technology information.
Objective:
Placement aims to create an efficient physical layout while meeting design constraints for
performance, power, and manufacturability.
Definition:
CTS is the process of designing a clock distribution network to ensure that the clock signal
reaches all sequential elements (like flip-flops, denoted as FFs) with minimal clock skew and
latency.
The goal is to make the clock signal arrive at all clocked components at approximately the same
time.
Goals of CTS:
Minimize Clock Skew:

Clock skew is the difference in arrival times of the clock signal at different sequential elements.
Reducing skew ensures proper synchronization of the circuit.
Reduce Clock Latency:

Latency is the delay between the clock source (e.g., I/O port or clock generator) and the clock
sink (sequential elements).
Lower latency improves circuit performance.
Balance Power, Timing, and Area:
Optimize the clock tree design to maintain low power consumption, good timing performance,
and minimal area usage.
Diagram Explanation:
Clock Tree:

The red lines represent the clock distribution network.

The clock signal is propagated hierarchically from a clock source to various sequential elements
(FF1, FF2, FF3, FF4).
Flip-Flops (FFs):

Sequential elements are placed at different locations, requiring the clock tree to handle varying
distances while maintaining synchronization.
I/O Port:

The clock source where the clock signal is generated.

Why CTS is Critical:
Synchronization:

Ensures that all sequential components are synchronized to avoid timing violations such as setup
or hold time errors.
Enhances Performance and Reliability:

A well-designed clock tree improves the circuit's timing performance and overall reliability by
reducing skew and latency.
CTS is an essential step in physical design as it directly impacts the chip's functionality, power,
and timing performance.