Syllabus:

Module 1: Fundamentals of 8086 Microprocessor: Overview of 8086 Microprocessor Architecture,

8086 Programming Model, Pin Diagram, Signals, Min/Max Mode, register organization, Physical
memory organization, Timing diagram, Addressing Modes: Register Addressing, Immediate
Addressing, Direct Addressing, Register Indirect Addressing, Base-Plus-Index Addressing, Register
Relative Addressing, Base Relative-Plus-Index Addressing, Memory Addressing Mode. (10 Hrs)
[Blooms level selected: Understand Level]
Module 2: 8086 Instruction Set and Interfacing: Instruction Sets: Data movement instructions,
Program control instructions, Arithmetic and Logical Instructions, Stack Instructions, Assembler
Directives and operators. 8086 Assembly language programs involving logical, branch and call
instructions. I/O Interfacing, Memory Interfacing, Interrupts. Peripheral Devices, Programmable
Peripheral Interface (Intel 8255A). (14 Hrs) [Blooms level selected: Understand Level]
Module 3: Fundamentals of 8051 Microcontroller: Microprocessor Vs Microcontroller, Embedded
Systems, Embedded Microcontrollers, 8051 Architecture- Registers, Pin diagram, I/O ports functions,
Internal Memory organization. External Memory (ROM & RAM) interfacing. Addressing Modes,
Data Transfer instructions, Arithmetic instructions, Logical instructions, Branch instructions, Bit
manipulation instructions. Simple Assembly language program examples (without loops) to use these
instructions. 8051 Timers and Counters – Operation and Assembly language programming to generate
a pulse using Mode-1 and a square wave using Mode-2 on a port pin. 8051 Serial Communication-
Basics of Serial Data Communication. (18 Hrs) [Blooms level selected: Apply Level]
 1. Architecture and register organization of 8086

and
2. Register organization of 8086

Fig. 1 Architecture of 8086

Internal block diagram has been partitioned into two logical units;
(1) The Bus Interface Unit (BIU) (2) the Execution Unit
The Execution Unit (EU)
The EU contains the arithmetic and logic unit (ALU), the control unit, an internal bus, plus a
few registers.
Register sets:
8086 has four 16-bit general-purpose registers labeled as AX, BX, CX and DX. Each of these
registers can also be used as two separate and exclusive 8-bit registers also i.e., AX has two
parts AH and AL, where H and L stands for the high and low portions respectively.
AX: AL /AX is sometimes called the accumulator, but the relevance of the accumulator is
less for 8086 compared to the earlier 8085 in which one operand is implied to be in the A
register for many instructions.
BX, CX and DX:
These are the other working registers of the 8086, which means that temporary data storage,
arithmetic calculations and data manipulation can be done with these registers
Base register BX is frequently used as an address register in many based addressing modes.
Counting register CX is used as a counter in many instructions.
Data register DX is used in I/O instructions as a pointer to data by storing the address of the
I/O port.
Pointer and Index Registers: SP, BP, SI and DI are address registers, and can be used only
as
16-bit registers
BP and SP: They are the Base pointer and Stack pointer respectively. SP always points to the
top of the stack, while BP can point to any location in the stack.
SI and DI: These are Index registers, labeled as Source Index and Destination Index
respectively. They function as address registers in various addressing modes

Fig.2 Register organization of 8086

Flag Register
It is a 16-bit register, of which 7 bits are unused. 6 bits are used as conditional flags. The
others are control flags. The conditional flags available are the Carry (CF), Zero (ZF),
Parity (PF), Overflow (OF) and the Sign Flag (SF).
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

× × × × OF DF IF TF SF ZF × AF × PF × CF

OF=1 if
i) There is an overflow into the MSB (8th or 16th bit) from the bit of lower significance, but
no carry out from the MSB,
ii) There is a carry out from the MSB, but no carry into the MSB.
SF=1 if the result contains a negative number
ZF=1 if arithmetic or logic operation is zero,
AF =1 if there is carry from bit D3 into D4.
PF=1 if there is even number of 1s in lower 8-bits
CF=1 if there is a carry out from the MSB
Control Flags: There are three control flags; the Trap flag, Direction flag & Interrupt flag.
The control flags have to be deliberately set or reset according to the requirements of the
program. The Trap flag (TF) is set to perform step by step execution, during debugging. The
Interrupt flag (IF) is set to enable interrupts. The Direction flag (DF) is used in string
operations.
Arithmetic Logic Unit: It is the part of a computer that performs all arithmetic and logic
computations. The ALU is the most important unit of the processor. Instructions that are
fetched and decoded are executed in the ALU. Thus the ALU has direct access to the general
purpose registers and flags.
Bus Interface Unit (BIU)
This unit BIU is responsible for address calculations, pre-fetching instructions for the queue
and sequencing instructions one by one.
The Instruction Queue
 Instructions are found in memory, from where they are fetched and decoded as and
when they need to be executed.
 However in 8086, there is a queue which fetches instructions ahead of the execution
time and places them in a 6-byte first-in-first-out (FIFO) queue. This pre-fetching is
done when the buses are free i.e., not being used for the execution of the current
instruction.
 The advantage of pre-fetching is that when a particular instruction is to be executed,
there is a good chance of finding it in the queue (which is on-chip), rather than having
to go to memory to fetch it.
 This pre-fetching belongs to a class of ideas called pipelining, which means that both
execution and fetching take place at the same time i.e., while the execution of one
instruction is going on, the fetching of another one can be done.
 Pipelining greatly speeds up processing.
3. Pin diagram and Signal description of 8086
 Min. mode Max. mode

Fig. 3 Pin diagram of 8086

 Intel 8086 is a 16-bit HMOS microprocessor.
 It is available in 40 pin DIP chip.
 It uses a 5V DC supply for its operation.
 The 8086 uses 20-line addresses bus.
 It has a 16-line data bus.
 The 20 lines of the address bus operate in multiplexed mode. The 16-low order
address bus lines have been multiplexed with data and 4 high-order address bus lines
have been multiplexed with status signals

Pin No. Designation Function Type

16 to 2, 39 AD0–AD14, 16 multiplexed address / data lines which carry Bidirectional

AD15 address when ALE is high, and later functions as
data lines D0–D15, when ALE is low
35 to 38 A19 / S6– Address lines A19 to A16, which are multiplexed Output
A16 / S3 with status signals S6 to S3. The status bits function
are as follows:
S6 – always 0
S5 – condition of the interrupt flag (IF)
S4 and S 3 show the current segment in
use as below:
S4 S3 Segment
0 0 Extra Segment
 0 1 Stack Segment
1 0 Code or no Segment
1 1 Data Segment

32 RD When this signal is low, data can be received from Output

memory or input devices

29 WR When this signal is low, it is an indication that the Output

data on the data lines are available for writing into
memory or outputting to output devices

19 CLK This is the clock pin to which a clock with at least Input
33% duty cycle is to be supplied

21 RESET This is an active high signal which signals the Input

microprocessor to reset itself provided the pin is held
high for at least 4 clock periods

22 READY For the bus cycle to proceed normally, the READY Input
pin should be found to be at logic high when it is
sampled. If it is at logic low, WAIT states are
inserted into the current bus cycle

23 TEST This pin is used usually when an arithmetic co- Input

processor is in the system. This pin is tested by the
WAIT instruction. If the pin is at logic zero, the
‘WAIT’ instruction becomes a NOP instruction.
Otherwise, the processor waits until this pin becomes
logic zero

25 ALE Address Latch Enable – this signal goes high in the Output
beginning of a bus cycle and indicates that the
multiplexed address bus contains address
information

26 DEN Data Enable – This active low signal functions as an Output

activation signal for the external data bus buffers

27 DT/ R Data Transmit / Receive – The logic value of this Output

signal indicates whether the data is received (in a
read cycle DT / R = 0) or transmitted (in a write
cycle DT / R = 1). Thus, it is used as a direction pin
for external data bus buffers

28 M/ IO For I / O access this pin is low, and for Output

memory access, it is high
31 HOLD This is a signal from a peripheral requesting direct Input
memory access (DMA). If the signal is high, the
processor issues a Hold Acknowledge signal and tri-
states its data, address and control bus

30 HLDA Hold Acknowledge’ indicates the acknowledgement Output

of the HOLD request

33 MN /MX This pin is used to select the mode of operation – Input

minimum or maximum. For minimum mode, the pin
is to be connected to the 5 V supply

34 BHE /¿ S 7 ¿ BHE stands for Bus High Enable. It is available at Output

pin 34 and used to indicate the transfer of data using
data bus D8-D15. This signal is low during the first
clock cycle, thereafter it is active.

1, 20 GND Ground’ – The common point is to be connected to -----

two pins. Two Ground pins are used so as to prevent
having to connect them together internally, due to
possible noise in the internal routing of the pins

40 VCC The power supply must be + 5V + /−10% -----

18 INTR Interrupt Request – this is used by an external device Input

to interrupt the processor, which responds, only if the
interrupt flag (IF) is set, by lowering the INTA line,
and initiating an ‘interrupt acknowledge’ machine
cycle input

24 INTA Interrupt Acknowledge‘ is an active low signal Output

acknowledging the interrupt request placed on the
INTR pin

17 NMI Non maskable interrupt request which is placed by Input

an external device – similar to INTR, but the
Interrupt Flag (IF) does not have to be set for it to be
serviced. It is a high priority interrupt

4. Physical Memory organization of 8086

 Fig.4 Memory organization of 8086
The Code Segment and the Instruction Pointer
 The code segment is the area of memory where code alone is stored.
 The offsets within the code segment are referenced using the Instruction Pointer (IP),
which is a 16-bit register.
 The IP sequences the instructions, and always points to the next instruction to be
executed.
 Whenever an instruction byte has to be fetched from memory, the bus interface unit
(BIU) performs the address calculation using the contents of CS register and the IP.
 This 20-bit address is then placed on the address bus and the instruction byte is
fetched. Thus the logical address for an instruction bye is of the form CS : IP.
The Stack Segment and the Stack Pointer
 The stack is an area of memory that is used in a special way.
 There is a 16-bit register called Stack Pointer (SP) which points to the top of the
stack.
 The upper 16 bits of its base address is available in the SS register.
 The 8086 has a stack which grows downwards (i.e., to lower memory addresses).
 Thus the format SS : BP is also a logical address.
The Data Segment and Extra Segment
 Both these segments store data, but in certain special cases (string instructions), it
may be necessary to list them separately.
 There is an Extra Segment (ES) register to store the upper 16 bits of the base address
of the extra segment.
  The offset within the data segment is also termed as an ‘effective address’.
 The effective address calculation depends on the mode of addressing.

Table 1: Segments and Corresponding Registers Used for Specifying Offsets

Segment Offset Registers Function

CS IP Address of the next instruction
DS BX, DI, SI Address of data
SS SP, BP Addresses in the stack
ES BX, DI, SI Address of destination data (for string
instructions)

Advantages of Segmentation
1. It allows all address registers to have the same size as the data registers (16-bit), while
allowing the use of 20-bit physical addresses.
2. All addresses in memory are re-locatable. This means that any program or data can be
loaded in any address in memory. A re-locatable program is one which can be placed
in any area of memory and executed without change. Data is also re-locatable.
Changing the base address of the corresponding segment is the only action we need to
perform, in order to re-locate. All addresses within the program are relative to the
base address, as they are of the form Base address: off set. All processors in the x86
family have this kind of segmentation.

5. General bus operation

A bus is collection of signal wires which connect between the components of the computer
systems – the figure shows that the CPU is connected to the memory as well as I/O through
the system bus, but only one at a time – if the memory and I/O wants to use the bus at the
same time, there is a conflict, as there is only one system bus. The system bus comprises of
the address bus, data bus and the control bus.
The Data Bus: The set of lines used to transfer data is called the data bus. It is a bidirectional
bus, as data has to be sent from the CPU to memory and I/O, and has to be received as well
by the CPU. The width of the data bus determines the data transfer rate, size of the internal
registers of the CPU and the processing capability of the CPU. The 8086 has a data bus width
of 16 bits and therefore it can handle 16 bits.
The Address Bus: The address bus width determines the maximum size of the physical
memory that the CPU can access. With an address bus width of 20 bits, the 8086 can address
220 different locations. It can use a memory size of 2 20 bytes or 1 MB. When a particular
memory location is to be accessed, the corresponding address is placed on the address bus by
the CPU. I/O devices also have addresses. In both cases, it is the CPU which supplies the
address, and as such, the address bus is unidirectional.
The Control Bus: The control bus is a set of control signals which needs to be activated for
activities like writing/reading to/from memory/I/O, or special activities of the CPU like
interrupts and DMA. Thus, signals like Memory Read, I/O Read, Memory Write and
Interrupt Acknowledge are part of the control bus. These control signals dictate the actions
taking place on the system bus that involve communications with devices like memory or
I/O. For example, the Memory Read signal will be asserted for reading from memory. It is
sent to memory from the processor. A signal such as ‘Interrupt’ is received by the processor
from an I/O device. Hence in the control bus, we have signals traveling in either direction.
Some control lines may be bidirectional too.

Fig. 5 System bus and its component

6. I/O addressing capability

For a computer to communicate with the outside world there is the need for what are called
peripherals. Some of these peripherals are purely input devices like the keyboard and mouse;
some are purely output devices like the printer and video monitor and some like the modem
transfer data in both directions. All this just means that such I/O devices are needed for us to
use a computer. However, it is difficult for a processor to deal directly with I/O devices,
because of their incompatibility with the processor – each peripheral is different and the
operating conditions, voltages, speeds and standards are not understandable to the processor.
The processor does not have the necessary control signals to deal with different peripherals.
Hence, the normal practice is for each peripheral to have a controller which acts as an
interface between the peripheral and the processor. This controller, which may be a special
purpose chip, understands the characteristics of the particular device and provides the
necessary control signals to the processor to communicate with the peripheral. Thus, we have
specialized controllers for most peripherals – like the keyboard display interfacing chip,
parallel port interfacing chip and serial communication chip. All these chips are
programmable – they have registers for commands, data and status. By suitably programming
these chips, we can get the processor to communicate correctly with any peripheral.
 Fig. 6 I/O system
7. Special processor activities : Find it yourself
8. Minimum mode and maximum mode operation

Some pins have dual functions, and this corresponds to two modes of operation- minimum
and maximum modes. The minimum mode is used when the 8086 is used in single processor
systems, and the maximum mode is used when the system is a multi-processor system, in
which the 8086 / 8088 is one of the processors.
Minimum Mode Pins
For minimum mode operation, pin no. 33 MN / MX should be at logic high. Refer section 4
for minimum mode pin function explanation.
Maximum Mode Pins
It is necessary to use the maximum mode if the processor is to be used in multiprocessor
configurations. The most important issues in a multiprocessor environment are inter-
processor communication and bus contention. In this mode, 8086 has special pins for
resolving these issues. To use the maximum mode, pin No. 33 MN / MX must be connected
to ground.
 Modes of operation of 8086

Minimum mode Maximum mode

Minimum mode is used when the 8086 is used in single Maximum mode is used when the system is a multi-
processor systems processor system, in which the 8086 is one of the
processors

This mode of operation was designed by Intel for allowing the 8086 to communicate with
other processors like the arithmetic co-processor (8087) and the input /output processor 8089.
It was also used to allow 8086 to be used in large loosely coupled multiprocessor systems.
This mode was dropped from Intel’s designs from 80286 onwards. Later processors (80486
onwards) had the arithmetic co-processor integrated on the processor chip itself. From pin
number 24 to 31 in maximum mode, the functions of INTA, ALE, DT / R, M / IO, and WR are
generated externally by 8288 bus controller.
Table 2 Control Signals Generated by the Bus Controller 8288

Status signal Machine cycle Control signal

generated by 8288
S2 S1 S0
0 0 0 Interrupt acknowledge INTA
 0 0 1 I/O Read IORC
0 1 0 I/O Write IOWC
0 1 1 Halt NONE
1 0 0 Instruction Fetch MRDC
1 0 1 Memory Read MEMR
1 1 0 Memory write MEMW
1 1 1 Inactive NONE

Fig. 8 Connection between 8086 and 8288

Fig. 7 Pin diagram of 8288

Request / Grant pins ( RQ)/(¿) (Pin numbers 30 & 31 )
As the name implies, they cater to ‘request’ and ‘grant’. Each pin acts similar to the HOLD
and HLDA pin. In the minimum mode, HOLD is for bus request, and HLDA is for bus grant.
In the maximum mode, one pin performs both functions. When one processor is using the
bus, another processor may request the use of the bus and the current bus master may
relinquish the bus (subject to conditions). Thus, requests from another processor will be
placed on these lines and the grant signal is also placed on these pins, but in the opposite
direction, obviously. That is how these pins are ‘bidirectional’. Three pulses are needed to
complete a request / grant / release of the bus.
 The RQ / GT pins are examined at the rising edge of each clock pulse. If a request (low
logic for one T state) is detected, and if the conditions are conducive for granting the
request, the grant pulse appears on the same pin immediately following the next T4 or T1
state.
Queue Status pins QS0, QS1
These pins are inputs to the 8086. It becomes useful when an arithmetic coprocessor is the
second processor in the system. Since the co-processor is expected to work in step with
8086, the co-processor can interrogate the 8086 about its queue status, on these lines, and
decide its course of action accordingly.
LOCK
This is an output signal from the 8086. If this processor wants to prevent any other bus
masters from accessing the bus, this signal will be asserted low. The 8086 can use an
instruction with a LOCK prefix to cause the hardware LOCK signal to be asserted.
9. Timing diagram

Clock
All activities on the system bus is synchronized by the system clock which provides the basic
timing.
List of activities on the bus are:
i) Reading from memory / IO
ii) Writing to memory / IO
Depending on the type of activity, different control signals are activated. Any read or write
cycle is called a bus cycle. For 8086, a bus cycle takes 4 T states, where one T state is defined
as the ‘period’ of the clock. If the clock frequency is 10 MHz, one T state = 0.1μs or 100
nsecs.

A bus cycle is also called a machine cycle. During a machine cycle, a specific operation –
say, reading or writing is accomplished. So, we can have the following basic machine cycles:
i) Memory Read
ii) Memory Write
iii) I / O Read
iv) I / O Write

Read Machine Cycle

The steps involved in a typical read machine cycle are:
1. Place on the address bus, the address of the location whose content is to be read. This
action is performed by the processor.
2. Assert the read control signal which is part of the control bus.
3. Wait until the content of the addressed location appears on the data bus.
4. Transfer the data on the data bus to the processor.
5. De-activate the read control signal. The read operation is over and the address on the
address bus is not relevant anymore.
 Fig. 9 Read machine cycle
 In T1, the address is placed on the lines AD0 to AD15 and A16 to A19 .
 BHE is high or low depending on the type of data (byte / word) to be accessed. ALE
goes high.
 M / IO signal is high from T1 to T4.
 Also the DT/ R is low from T1 to T4 indicating that data is to be ‘received’ by the
processor
 In T2, the address information is removed from AD0 to AD15. The address
information is removed from A16 / S3 to A19 / S6 and BHE / S7 also, and these lines
now carry status information. In T2, the RD signal (which is the READ control
signal) is made low. In T2, DEN goes low to enable the data bus buffer outputs
 The clock cycle T3 is to allow ‘access time’ for bringing data from memory / IO and
put it on the data bus. Thus, after the data appears on the data bus, it is transferred to
the 8086 at the end of T3.
 In T4, all the bus signals are de-activated in preparation for the next bus cycle. This
machine cycle ends with T4, and the next machine cycle is scheduled to start.
Write Machine Cycle
The steps in a write machine cycle are:
1. Place on the address bus, the address of the location to which data is to be written.
2. On the data bus, place the data to be written.
3. Assert the write control signal which is part of the control bus.
4. Wait until the data is stored in the addressed location.
5. De-activate the memory write signal. This ends the memory write operation.
For the 8086, the control signals for a write machine cycle is WR. Also the DT / R signal will
be high (for ‘data transmit’) for writing. The write bus cycle also uses 4 T states normally.
 Fig. 10 Write machine cycle

1. Addressing modes of 8086

For computations in assembly language, we need an opcode and operands. The way in which
operands are specified in an assembly language instruction is called its addressing mode. Let
us use the MOV instruction for understanding these modes. This has the format
MOV destination, source ………. source data is copied into the destination.

The basic assumptions in this context are

I. The operands can be in registers, in memory, or may be in the instruction itself.
However the 8086 does not have an addressing mode in which both operands are in
memory locations,
e.g. MOV [3456H], [3001H] --------------is wrong.
 II. in the case of two operands, one of them can be in memory, but the other will have to
be placed in a register,
e.g. MOV [3456], BX ----------is right.
III. data types should match – i.e., the source and destination should both be either bytes
or words.
1. Register Addressing
Here both the source and destination are registers. No memory access is involved.
MOV AL, AH; copy the content of AH to AL
MOV CH, BL; copy the content of BL to CH
MOV SI, BX; copy the content of BX to SI
MOV ES, AX ; copy the content of AX to ES
Note that the first two are byte operations, while the other two are word operations.
MOV AX, BL ; gives an error as AX is 16 bit and BL is 8 bit
MOV BL, AX ; gives an error for the same reasons
2. Immediate addressing mode
In this mode, the source will be a constant data
MOV AL, 45H ; copy 45H to AL
MOV BX, 34E3H ; move the hex number 34E3H to BX
MOV CL, ‘Q’ ; move the ASCII value of Q to CL
MOV PRICE, 40 ; move the hex number 40 to the memory location with label PRICE
MOV NUMS, 0FC6H ; move the hex number 0FC6H to the memory location NUMS
Segment registers are not allowed to use this mode of addressing.
MOV DS, 2300H ; gives an error as DS is a segment register
3. Direct addressing modes
Here either the source or the destination will be a memory address.
MOV AX, [2345H] ; move the word in location 2345H into AX
MOV [1089H], AL ; the byte in AL is moved to location 1086H
It is to be remembered that the addresses in the instructions are off sets within the data
segment (i.e., the logical address). We need to know the content of DS to calculate the
physical address.
The size of the registers indicates the size of the operand. Hence, in the first instruction, a
data word is referred to; while in the second, a data byte is moved. The square brackets are
necessary to indicate that the number is an address and not data. However, we may use labels
for addresses, and re-write the above two instructions.
MOV AX, PRICE
MOV COST, AL
We must then ensure that the referred addresses have been defined earlier with these labels.
4. Register indirect addressing mode
In this mode, the address of the data is held in a register. The register acts as a pointer to the
data.
The registers must be enclosed in square brackets to indicate that they function as pointers.
We also use the term effective address (EA) for the address of the operand. For this mode of
addressing, the address registers allowed are BX, SI and DI.
EA = {[BX]/[DI]/[SI]}
MOV AL, [BX] ; move into AL the content of the location whose address is in BX
MOV [SI], CL ; move the content of CL to the address pointed by SI
MOV [DI], AX ; move the content of AX to the address pointed by DI
In the third instruction, AX contains two bytes. Hence the content of AL will be moved to the
address pointed by DI. The content of AH will be moved to the address [DI + 1].

5. Register relative addressing mode

In relative addressing mode, a number or displacement is part of the effective address.
EA = {[BX]/[DI]/[SI]/[BP]} + 8-bit or 16-bit displacement
MOV CL, 10[BX] ; move the content of the address specified by adding the content of BX &
10.
Thus the effective address is [BX + 10 ]. Once the effective address is computed, the physical
address is calculated as the sum of the segment base address and the effective address. The
displacement can be a 16-bit signed/unsigned number or an 8-bit sign extended number.
However the displacement should not be so large as to make the effective address go beyond
the range of the maximum size of a segment. The above instruction can also be written as
MOV CL, [BX + 10]
MOV CL, [BX] + 10 or
MOV CL, [BX][10] or
MOV CL, PRICE [BX]
In the last case, PRICE has to be defined earlier as a displacement of 10

6. Base indexed addressing mode

In this mode, an index register and a base register together carry the effective address. The
content of these two registers are added and called the effective address.
MOV AL, [BX][SI] ;move the content of the effective address pointed by [BX] and [SI] into
AL
The effective address is obtained by adding the content of BX and SI. Since the destination
register is an 8-bit register, this is a byte operation. The following is a word operation as the
source register CX is 16-bit in size.
MOV [BX][DI], CX ;move the content of CX to the effective address pointed by [BX] and
[SI]

7. Relative based indexed mode

This is the case when the ‘effective address’ is specified with a base register, an index
register as well as a displacement. The ‘effective address’ is the sum of the two registers and
the displacement.
For example, the following use the relative-based indexed mode of addressing
MOV DL, 5[BX][DI] ; EA = 5 + BX + DI
MOV 5[BP][SI], AX ; EA = 5 + BP + SI
MOV CL, COST[BX][SI] ; EA = COST + BX + SI ;COST has to be defined as a
displacement earlier.

2. Instruction set of 8086

Refer to the presentation (slide)
3. Assembler directives & operators
Refer to the presentation (slide)
1. Program to find the factorial of a number
2. Program to divide a 16 bit number by an 8 bit number
3. Program to add two 16-bit numbers with or without carry
4. Program to subtract two 16-bit numbers with or without borrow
5. Program to count the number of 1s in the contents of Accumulator
6. Program to transfer a block of 4-bytes by using string instruction
7. program to find 1’s and 2’s complement of 8-bit number
8. Program to find sum of ‘n’ numbers
 9. Program to find average of ‘n’ numbers
10. Program to sort numbers in ascending order

4. Program to find the factorial of a number

Solution:
The factorial of a number ‘n’ is n × ( n−1 ) × ( n−2 ) × ( n−3 ) …
i.e. factorial of 4 is 4*3*2*1 = 24
Assumptions –
Starting address of program: 0400
Input memory location: 0500
Output memory location: 0600 and 0601

MNEMONICS COMMENTS
MOV CX, [0500] Move the content of memory address 0500 in register CX
MOV AX, 0001 Move 1 in the register AX
MOV DX, 0000 Move 0 in the register DX
MUL CX Multiply the contents of CX & DX and store product in
DX:AX
LOOP 040A Go to address [040A] till CX->00
MOV [0600], AX Move the content of AX in memory address 0600
MOV [0601], DX Move the content of DX in memory address 0601
HLT Stop Execution

Note –
The result of multiplication is stored in AX for byte data type.
For the word data type, the result of multiplication is stored in AX-DX. i.e.
90C3×12DA=AA8FC0E;
After multiplication AX=FC0E & DX=AA8

5. Program to divide a 16 bit number by an 8 bit number

Algorithm –
1. Assign value 500 in SI and 600 in DI
2. Move the contents of [SI] in BL and increment SI by 1
3. Move the contents of [SI] and [SI + 1] in AX
4. Use DIV instruction to divide AX by BL
5. Move the contents of AX in [DI].
6. Halt the program.
 MNEMONICS COMMENT

MOV SI, 500 Assign value 500 in SI

MOV DI, 600 Assign value 600 in DI

MOV BL, [SI] Move the content of SI in Register BL

INC SI Increment SI by 1 (500+1=501)

MOV AX, [SI] Increment the content of memory

address specified by SI in register AX
DIV BL Divide the content of AX by content of
BL and store the result in AX
MOV [DI], AX Assign the value of AX to the memory
address pointed by DI
HLT End of program

6. Program to add two 16-bit numbers with or without

carry

Problem – Write a program to add two 16-bit numbers where starting address is 2000H and
the numbers are at 3000H and 3002H memory address and store result
into 3004H and 3006H memory address
Mnemonics Comment

MOV CX, 0000 Assign 0 into the reg. CX

MOV AX, [3000] Move the data of address [3000] to reg. AX

MOV BX, [3002] Move the data of address [3002] to reg. BX

ADD AX, BX AX  AX + BX
Add the contents of AX & BX and store the result in
AX
JNC L2 Jump to address 2010 if there is no carry
 INC CX CX CX+ 1(0+1=1CX)

MOV [3004], AX [3004] AX

L2:
MOV [3006], CX [3006]  CX

HLT Stop

7. Program to subtract two 16-bit numbers with or without borrow

Problem – Write a program to subtract two 16-bit numbers where starting address
is 2000 and the numbers are at 3000 and 3002 memory address and store result
into 3004 and 3006 memory address
Mnemonics Comment
MOV CX, 0000 [CX]  0000
Assign 0 into the reg. CX
MOV AX, [3000] [AX]  [3000]
Move the data of address [3000] to reg. AX
MOV BX, [3002] [BX]  [3002]
Move the data of address [3002] to reg. BX
SUB AX, BX AX  AX - BX
JNC 2010 Jump to memory address 2010 if there is
no borrow
INC CX CX <- CX + 1
MOV [3004], AX [3004] AX
MOV [3006], CX [3006]CX
HLT Stop
8. Program to count the number of 1s in the contents of Accumulator

Solution: Let AL=50H=0101 0000 has two 1s.

We have written program in which the count in register BL will give the numbers of 1s:
MOV AL, 50H Load the number in Accumulator

MVI BL, 00H Initialize register B as a counter with initial value

00H; BL0
MVI CL, 08H Initialize register C as a counter for looping with
initial value of 08H; CL8

L1: SAR AL, 1 Rotate the content of the accumulator right

through carry
JNC NEXT If Carry bit is not 1, go to NEXT

INC BL If the bit is 1, increment BL

NEXT: DEC CL Decrement counter CL(CL-1=6)

JNZ L1 If the counter CL is not zero, jump to loop
HLT Terminate program execution

After Five number iterations of CL, the content of BL=1. This process will continue until
BL is not equal to 2
 9. Program to transfer a block of 4-bytes by using string instruction

Problem – Write a program to transfer a block of 4 bytes, starting address is 0500 and
transfer the block at address 0600 by using string instructions

04 18 AD 0504 18 AD 05

0500 0501 0502 0600

0503 0601 0602 0603

Mnemonics Comments
MOV SI, 500 SI500 Move the offset address 500 of Data segment to SI
MOV DI, 600 DI600 Move offset address 600 of Extra segment to DI
MOV AX, 0000 AX0000
MOV DS, AX Move 0000H to DS register so that base address of data segment is
0000H
MOV ES, AX Move 0000H to ES register so that base address of Extra segment is
0000H
MOV CX, 0004 CX0004 since four data have to be moved
CLD Clear directional Flag
REP reduce CX and repeat till CX≠ 0
MOVSB Move the string byte from DS:[SI] to ES:[DI]
HLT End of the program

7. Program to find 1’s and 2’s complement of 8-bit number

Problem – Write a program to convert a string of data to its two’s compliment form
Mnemonics Comment
MOV SI, 3000H SI  [3000]
MOV DI, 4000H DI  [4000]
MOV CX, 000AH CX  000A
LODSB Load the string byte at DS:[SI] into AL
 NEG AL Negative of AL
STOSB Load the string byte from AL into ES:[DI]
LOOP NZ Loop through a sequence of instructions till CX>0
HLT Stop

8. Program to find sum of ‘n’ numbers

Problem – Write a program to find sum of ‘n’ numbers. Assume four numbers stored in
memory address 500, 501, 502, 503. Store the sum in address 600
04 03 02 01 0A
0500 0501 0502 0503 0600

Mnemonics Comments
MOV AX, 0000H Initialize AX equal to 0
MOV SI, 500 SI500 Move the offset address 500 to SI
MOV DI, 600 DI500 Move the offset address 600 to DI
MOV CX, 0004 Assume 4 data whose sum has to be found
L1: ADD AX, [SI] AXAX+[SI]
 INC SI Increment SI; 500+1=501(SI)……… so on
LOOP L1 Decrement CX. Go to L1 if CX≠ 0
MOV [DI], AX Assign the value of AX to the memory address pointed by DI
HLT Stop

9. Program to find average of ‘n’ numbers

Problem – Write a program to find sum of ‘n’ numbers. Assume four numbers stored in
memory address 500, 501, 502, 503. Store the sum in address 600
04 03 02 01 2.5
0500 0501 0502 0503 0600

Mnemonics Comments
MOV AX, 0000H Initialize AX equal to 0
MOV SI, 500 SI500 Move the offset address 500 to SI
MOV DI, 600 DI500 Move the offset address 600 to DI
MOV CX, 0004 Assume 4 data whose sum has to be found
L1: ADD AX, [SI] AXAX+[SI]
INC SI Increment SI; 500+1=501(SI)……… so on
LOOP L1 Decrement CX. Go to L1 if CX≠ 0
DIV CX AX=AX/CX (Average of four numbers)

MOV [DI], AX Assign the value of AX to the memory address pointed by DI

HLT Stop
10. Program for Sorting an array in ascending order

• The array can be sorted in ascending order by bubble sorting.

• In bubble sorting, n-1 comparisons are performed by taking two data at a time.
• After each comparison, the two data can be rearranged in the ascending order in the
same memory location, i.e., smaller first and larger next.
• When the above n-1 comparisons are performed n-1 times, the array will be sorted
in ascending order in the same locations.
In general
For array of size ‘n’ There will be (n-1) comparison & (n-1) iterations
i.e., array of size 5  4 no. of comparisons & 4 no. of iterations
Procedure to do sorting is explained below
 Flow chart to do sorting is shown below

Label MNEMONICS COMMENT

MOV SI, 500 SI<-500
MOV CL, [SI] CL<-[SI]
DEC CL CL<-CL-1
L1: MOV SI, 500 SI<-500
MOV CH, [SI] CH<-[SI]
DEC CH CH<-CH-1
INC SI SI<-SI+1
M1: MOV AL, [SI] AL<-[SI]
INC SI SI<-SI+1
CMP AL, [SI] AL-[SI]
JC L2 JUMP to label L2 If CY=1
XCHG AL, [SI] SWAP AL and [SI]
DEC SI SI<-SI-1
L2: DEC CH CH<-CH-1
JNZ M1 JUMP to label M1 If ZF=0
DEC CL CL<-CL-1
JNZ L1 JUMP to label L1 If ZF=0
HLT END
 1. Memory Interfacing to 8086 (Static RAM and EPROM)

The memory can be RAM or ROM – the difference is that ROM can only be read from, so the
MEMWR signal from the processor does not have any relevance for ROM. A typical RAM has the
pin lines as shown in Fig 1. As shown, it has data lines D o to DM−1. If it is a byte organized memory,
the data lines are D0 to D7. The number of address lines (A0 to AN−1) depends on the number of
locations it contains.

Fig.1 RAM with control pins

For example in a 256 × 8 RAM chip, it has 8 data lines and a storage capacity of 256 locations – thus
it needs 8 address lines as 256 = 2 8. Thus, it is the capacity of the chip which decides the number of
address lines. The active low signals WE is to be connected to the MEMWR signal from the
processor side. Only if this pin is activated, can the write operation be done in the addressed
location. For reading, the pin MEMRD (from the processor side) is to be connected to the OE
(output enable) pin of the memory chip for reading. When this pin is low, the output lines are
activated. The pin CS (chip select) is the pin which enables the memory chip. No activity is possible if
this pin is inactivated, as the chip remains turned off.

A ROM chip is similar except that it does not have the WE pin, as it can only be read from.
The ROMs that are used are usually EPROM, which have a pin to enable the chip to be programmed
(PGM).

Memory Address Decoding: Refer to the slides

Address Decoding Using Block Decoders: Refer to slides

Memory Banks
8086 has a 16-bit memory bus – which means that data transfer can occur at a maximum rate
of 16 bits (one word) per bus cycle. However, sometimes only a byte needs to be accessed.
This means that the processor must have both options – i.e., both byte and word transfer must
be possible. We know that for a word transfer, two byte locations must be accessed i.e., two
addresses are actually needed. A 16-bit data can be obtained by accessing two memory chips
in parallel, each having 8 bits each of the word as shown in Fig 2.

Fig.2. 16-bit memory realized using two 8-bit memory chips

This is the way memory is organized in 8086. A 16-bit word is obtained as the concatenation of two
bytes in two ‘memory banks’ i.e., memory is organized as two banks – one, the upper bank or high
bank with the data corresponding to the upper byte D8–D15, and the other, the lower bank or low
bank which has the data lines D0–D7. The upper bank is also called the odd memory bank, because it
has the odd addresses mapped to it – in the same way, the lower bank is called the even bank (Fig
3). Remember that a 16-bit word has one byte with an odd address and one byte with an even
address. If a byte alone is to be accessed, it may be in the odd bank or even bank. Thus for reading /
writing a byte, only one of the banks is to be accessed, but to access a word, both memory banks
have to be accessed.

Fig.3. Memory banks of 8086

The two banks differentiated by A0. An even address implies that the LSB of its address i.e., A 0 is low.
Thus A0 is be used to enable the even bank. To enable the high (odd) bank, 8086 generates a signal
BHE (Bus High Enable) which goes low whenever the addressed byte is in the high (odd) bank.

Fig.4. Memory banks with the respective bank enable signals, along with the decoder

2. 8255 PPI (Programmable Peripheral Interface) various modes of operation

This chip is also called a parallel port chip and it eases out the problems and issues related to parallel
data transfer to/from memory or I/O devices. When I/O devices are more versatile and have more
features, a PPI is be very useful, especially when more than one I/O device is to be interfaced to the
processor. This chip ensures that no other extra hardware is required to interface peripheral devices
that perform parallel data transfer. As shown in Fig.5, the 8086 microprocessor is connected to 8255
using data bus. When data transfer takes place between microprocessor and 8255 then these data
are need storage (registers) in 8255. Therefore 8255 has registers called ‘ports’ – there are three
ports here – A, B and C, and these ports have pins connecting it to external devices. Thus, port A has
8 pins PA0 to PA7 – so also ports B and C, as well. To these port pins, external devices like keyboards,
displays, printers can be connected.
 Fig.5. The connection between 8086, 8255 and three peripherals

8255 pin configuration and Internal block diagram

Fig.6 (a) shows the pin configuration of the DIP (dual-in-line) version of the chip. It has 40 pins, which
consist of three 8-bit ports named Port A (PA), Port B (PB) and Port C (PC), each of which can be
programmed as input or output ports. Fig.2 (b) shows the internal block diagram of the chip with
various functional blocks as explained below

Data Bus Buffer There is a three state bi-directional 8-bit buffer which is used to interface the chip to
the data bus of the system. Upon execution of the processor’s input or output instructions, data and
control/status words are received or transmitted by the buffer.

Read/Write Control Logic It manages all data transfer between the chip and the processor, on
accepting control signals from the control and address buses of the system.

Group A and B Controls Functionally this chip has been divided as Group A and B and they have their
corresponding controls. The way the chip is to act is decided by a register called the control/status
register which can be written to and read from.

Programming the PPI

Programming the chip involves only the writing of a particular word to the control register.
 Fig.6 (a) Pin diagram of 8255 (b) Internal block diagram of 8255

The control register is an 8-bit register which can be written into. The bits of this word (called the
control word) will decide the way the ports of the chip are to be configured. The Fig.7 shows the
control word format.

Fig.7. Control word format of 8255

The ports A, B and C are grouped into two – Groups A and B. Group A consists of Port A and upper 4
bits (PC4–PC7) of Port C. Group B includes Port B and Port C lower (PC0–PC3). Thus Group A ports
has three operational modes (0, 1 and 2), but Group B ports have only two modes of operation.
Modes of Operation

The 8255 can be made to work in three modes as decided by the system designer. They are:

 Mode 0: Basic input/output

 Mode 1: Strobed input/output
 Mode 2: Bi-directional bus

Mode 0: This is the simplest and most widely used mode. In this mode, the two 8-bit ports A and B,
and the 4-bit ports Port C upper and Port C lower, may be used independently. Here data is simply
taken in from an input port or given to an output port.

The specifications of this mode are:

(1) Two 8-bit ports and two 4-bit ports.

(2) Any port can be input or output.
(3) Outputs are latched.
(4) Inputs are not latched.
(5) 16 different input/output combinations possible.

Mode 1: This is the ‘handshaking’ mode. Handshake implies data transfer in which the
communicating devices exchange request and acknowledge control signals with each other. For an
8255 operating in this mode, Ports A and B pins are used for data transfer, while 4 bits of each of
Port C are used for generating the handshaking signals for each of the 8-bit ports.

The specifications of this mode are:

(1) Each group contains one 8-bit port and one 4-bit port. The 4-bit port is used for
‘handshaking’.
(2) The 8-bit port can be either an input or an output.
(3) Input and output are latched.
(4) The 4-bit port is used for control and status of the 8-bit data port.
(5) Interrupt logic is supported.

Mode 2: This is the bidirectional mode. Only Group A can use this mode. Here Port A is used for
transmitting as well as receiving data. Handshaking signals generated by the upper 4 bits of Port C
maintain bus discipline for proper flow of data in the required direction. Now, let us use the different
modes.

The specifications of this mode are:

(1) Used in Group A only.

(2) One 8-bit, bi-directional bus port (Port A) and a 5-bit control port (Port C).
(3) Both inputs and outputs are latched.
(4) The 5-bit control port (Port C) is used for control and status for the 8-bit, bi-directional bus
port (Port A).

3. Interrupt structure of 8086

8086 has hardware interrupts, software interrupts and error generated interrupts. For the three
cases mentioned here, the interrupting mechanism is different, but the way the processor responds
is similar. After every instruction cycle, the processor checks if any interrupt is awaiting service. If, it
finds an interrupt request and decides to acknowledge and service it, the response is the following
sequence of steps:

(1) The flag register is pushed on to the stack.

(2) The interrupt flag is disabled (IF = 0).
(3) The trap flag is disabled (TF = 0).
(4) The CS register is pushed on to the stack.
(5) The IP register is pushed on to the stack.
(6) Control is transferred to the location in which the corresponding ‘Interrupt Service Routine’
(ISR) is stored. This in effect, would be a far jump.
(7) The program corresponding to the ISR is executed. The last instruction in the ISR will be IRET.
(8) Then IP is popped off the stack.
(9) CS is popped off the stack.
(10)The Flag register is popped off the stack.
(11)Control returns to the point at which it had left off .

Fig.8. Steps in processing an interrupt request

4. Interrupt Service Routine

When an interrupt occurs, the processor suspends the execution of its current task and takes
on another task as required by the interrupting source. This program, or routine as it may be
called, is designated as an ‘interrupt service routine’. This routine corresponds to the request
of a particular source of interrupt and it is also called its ‘interrupt handler’. This means that
for any interrupt that occurs, there is a particular interrupt service routine (ISR).

5. Interrupt Vector table (IVT)

ISR is available in memory and must be accessed on occurrence of the specific interrupt. For that,
the address of the ISR must be obtained. The address of an ISR is called its ‘interrupt vector’. For
an 8086 based system, any address of code is in the following form, CS: IP. Thus, the interrupt
 vector for any interrupt has 4 bytes – two for the CS value and two for the IP value. Thus, if the
interrupt vector for a particular interrupt is obtained, control can be transferred to the new location
by using the new values of CS and IP specified as the ‘interrupt vector’. The 8086 has 256
interrupt vectors and since each vector is specified by 4 bytes, it implies that 256 × 4 = 1024
bytes (1K) of memory are allocated to store the interrupt vectors. These 256 vectors are stored
in a table called the ‘Interrupt Vector Table’ (IVT) in system RAM from locations 00000 to
003FFH.

Fig. 9 Interrupt vector table of 8086

How is an Interrupt Different from a ‘Call’?

An interrupt seems to perform actions similar to a far CALL instruction. It differs in a few points,
however. An interrupt causes the flag register to be pushed on the stack in addition to CS and IP
values. It clears the trap and interrupt flags. The action of clearing the flags is not associated with
a CALL, but is part of the automatic response due to an interrupt. Also, note that the ISR ends
with IRET rather than a RET instruction. The IRET instruction ensures that the flag register is
also popped off the stack, rather than just the CS and IP.
Dedicated Interrupt Types
Intel has dedicated certain interrupt types for specific applications directly related to CPU
operations. These are listed below.
INT 0 (Divide by Zero Error)
The interrupt with type number 0 is dedicated to the ‘divide by zero’ error. This interrupt is an ‘error
generated’ interrupt (also called an ‘exception’). On division, if the quotient register is not large
enough to contain the quotient, this interrupt is generated automatically. Dedicating Type 0 for this
case means that the corresponding interrupt vector in the interrupt vector table is available at
0000:0000.
INT 1 (Single Stepping)
This type number is dedicated for ‘single stepping’ or ‘trace’. Single stepping is an important idea in
debugging. During logical debugging of our programs, we would like to stop after the execution of
each instruction and check the contents of registers, memory and so on. We usually perform the action
of ‘trace’ this way. Intel has provided the ‘Trap’ flag for this, and this flag has to be set to let this
happen.

D1 D1 D1 D1 D1 D1 D D D D D D D D D D

5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

U U U U OF DF IF TF SF ZF U AF U P U CF

INT 2 (Non Maskable Interrupt)

This interrupt corresponds to the vector (pointer) of the hardware interrupt NMI. When an interrupt is
received on the pin NMI (Non Maskable Interrupt) of the processor, a type 2 interrupt occurs – this
means that the ISR for NMI must be written in the address pointed by the corresponding IVT content.
INT 3 (Breakpoint Interrupt)
This is the breakpoint interrupt, which is useful for de-bugging. We need to set breakpoints (stop after
executing a group of instructions) and check the content of registers and memory after executing
instructions up to the breakpoint.
INT 4 (Overflow Interrupt)
This interrupt corresponds to the overflow flag. If the overflow flag is set, this interrupt occurs, but
not automatically. An instruction INTO (interrupt on overflow) must be written after the program
segment which is likely to cause the overflow flag (OF) to be set.
Software Interrupts
When an interrupt is initiated by an instruction, it is called a software interrupt. The format of this
instruction is:
INT type number.
The type numbers can vary from 0 to 255. This is a very important and interesting way of using
procedures whose vectors are inserted into the IVT. Thus, the user can write any procedure as an ISR,
store it in some address in memory and call it by using the instruction INT n.
Hardware Interrupts
There are two pins on which interrupt requests can be received – they are the INTR pin and the NMI
pin.
NMI
This is a positive edge triggered interrupt. This is a non maskable interrupt, in that it does not depend
on the setting of the interrupt flag (IF). It cannot be masked or prevented from being activated. It is a
Type 2 interrupt, meaning that its vector is obtained from the corresponding location in the interrupt
vector table. NMI caters to applications of the highest priority, like power failure.
INTR
This is the non-vectored interrupt pin of the 8086, which means that when an interrupt request is
received on this pin, it does not get automatically directed towards any particular entry in the interrupt
vector table. Another feature of this interrupt is that the interrupt flag (IF) is required to be set for an
interrupt request on the INTR line to be honored. It is to be ensured that the IF is set by the instruction
STI if interrupts on the INTR lines are to be acknowledged. INTR is a high level triggered interrupt.
Priority of Interrupts
When many interrupts occur at the same time, which source gets its request honored first? The
processor decides the priority. The order of priority is set in the following manner:
1) Internal interrupts and Software interrupts – get the highest priority,
2) NMI,
3) INTR – gets the lowest priority

6. 8259 Programmable Interrupt Controller (PIC) architecture and interfacing cascading

of interrupt controller and its importance

There are only two hardware interrupt lines for the 8086. An external device can place its interrupt
request on either of these pins. One pin called NMI is a ‘vectored’ interrupt, in the sense that its
interrupt handler is pointed to, by a particular type number and that is ‘2’. Thus, NMI is a Type 2
interrupt, and since it is non-maskable it is used for important and high priority services. As such, this
interrupt pin is not available for general interrupt requests from various peripherals. That leaves just
one pin for accepting hardware interrupt requests, and if many peripherals want to use this pin,
obviously a number of issues have to be resolved. It is in this context that a dedicated interrupt
controller like 8259 is necessary.
The PIC has eight interrupt request lines IR0 to IR7, on which peripherals can place their
interrupt requests. If one interrupt request alone is received on the chip, that request is channeled to
the INTR line of the processor. As is the usual sequence, the processor sends back an acknowledge
request in the form of the INTA signal. Then the PIC (on behalf of the peripheral which has made the
request) sends to the 8086 the interrupt type number corresponding to that specific interrupt.
Another activity of the chip is to resolve priorities. Suppose interrupt requests arrive at more
than one interrupt input of the chip. Which one of these requests should be channeled to the
processor? This decision is made by the PIC.
Block Diagram of 8259
 Fig. 10 Block diagram of PIC 8259

The function of various blocks is explained below:

Int (Interrupt) This output goes directly to processor interrupt input and causes the processor to
send back the INTA as an acknowledgement, to the 8259.

Interrupt Request Register (IRR) and In-Service Register (ISR): The interrupts at the IR input lines are
handled by two registers in cascade, the Interrupt Request Register (IRR) and the In-Service Register
(ISR). The IRR is used to store all the interrupt levels which are requesting service; and the ISR is used
to store the interrupt levels which are being serviced.

Priority Resolver This logic block determines the priorities of the bits set in the IRR. The highest
priority is selected and strobed into the corresponding bit of the ISR (in service register) during the
INTA pulse.

Interrupt Mask Register (IMR) The IMR stores the bits which mask the interrupt lines to be masked.
The IMR operates on the IRR. Masking of a higher priority input will not affect the interrupt request
lines of lower priority.

CAS0–CAS2: These three bi-directional lines can be used to cascade several such chips to expand the
number of interrupts up to 64, in a master or slave mode. The associated three I/O pins (CAS0-2) are
outputs when the 8259 is used as a master and are inputs when the 8259 is used as a slave.
 SP / EN: This stands for Slave Program/Enable Buffer. This is also a bidirectional pin. In the buffered
mode, it can be used to control buffer transceivers (EN ). In other modes, it indicates whether the
8259 is a master (SP = 1), or whether it is a slave (SP = 0).

R / W LOGIC: Just as in the case of any other peripheral chip, the decoding logic on the CS and A0
determine the addresses of the registers within the chip, and in conjunction with the RD and WR
signals, the registers can be written into and read from (to get status information).

10. Evolution of Microcontrollers

In 1981, Intel introduced an 8-bit microcontroller called the 8051. It was referred as system on
a chip because it had 128 bytes of RAM, 4K byte of on-chip ROM, two timers, one serial port,
and 4 ports (8-bit wide), all on a single chip. When it became widely popular, Intel allowed
other manufacturers to make and market different members of 8051 with its code compatible
with 8051. It means that if we write our program for one member of 8051, it will run on other
members too, regardless of the manufacturer. This has led to several versions with different
speeds and amounts of on-chip RAM.
Comparison between 8051 Family Members

Features 8051 8052 8031

ROM (on-chip space in bytes) 4K 8K 0K
RAM (bytes) 128 256 128
Timers 2 3 2
 I/O pins 32 32 32
Serial port 1 1 1
Interrupt sources 6 8 6

8031 Microcontroller
 Another member of 8051 family is the 8031 chip.
 This chip is often referred to as a ROM-less 8051 since it has 0K bytes of on-chip
ROM.
 To use this we have to add external ROM to it.
 This external ROM must contain the program that 8031 will fetch and execute.
 In process of adding external ROM, we loose two ports.
 That leaves only 2 ports (of the 4 ports) for I/O operations.
 To solve this problem, we can add external I/O to the 8031.
8751 Microcontroller
 The UV-EPROM version of 8051 is the 8751.
 8751 chip has 4K bytes of on-chip UV-EPROM.
 Using this chip for development requires access to a PROM burner, as well as a UV-
EPROM eraser to erase the contents of UV-EPROM inside the 8751 chip before we
can program it again.
 It takes around 20 minutes to erase the 8751 before it can be programed again.
 This has led many manufacturers to introduce flash NV-RAM version of 8051
DS89C4×0 from Dallas semiconductor
 To eliminate the waiting needed to erase the chip and thereby speed up the
development time, AT89C51 from Amtel corp. was introduced with flash ROM.
 The erasing of flash is done by the PROM burner itself, which is why a separate
eraser is not needed.
 To eliminate the need for a PROM burner, Dallas semiconductor has a version of
8051/52 called DS89C4×0 that can be programmed via the serial COM port of a IBM
PC.
2. Architecture of 8051 Microcontroller

Fig.1 shows the architecture of 8051, the system bus connects all the support devices to the
CPU. The system bus consists of an 8-bit data bus, a 16-bit address bus and bus control signals.
All other devices like program memory, ports, data memory, serial interface, interrupt control,
timers, and the CPU are all interfaced together through the system bus
Central Processor Unit (CPU)
The CPU is the brain of any processing device of the microcontroller. It monitors and
controls all operations that are performed on the Microcontroller units. The User has no
control over the work of the CPU directly. It reads program written in ROM memory and
executes them and do the expected task of that application.
Interrupts
Interrupt is a subroutine call that interrupts the microcontrollers main operations and causes it
to execute any other program, which is more important at the time of operation. The feature
of Interrupt is very useful as it helps in case of emergency operations. An Interrupts gives us
a mechanism to put on hold the ongoing operations, execute a subroutine and then again
resumes to another type of operations. The Microcontroller 8051 can be configured in such a
way that it temporarily terminates or pause the main program at the occurrence of interrupts.
When a subroutine is completed, then the execution of main program starts. Generally five
interrupt sources are there in 8051 Microcontroller. There are 5 vectored interrupts: INT0,
TF0, INT1, TF1, R1/T1.
Memory
Microcontroller requires a program which is a collection of instructions. This program tells
microcontroller to do specific tasks. These programs require a memory on which these can be
saved and read by Microcontroller to perform specific operations of a particular task. The
memory which is used to store the program of the microcontroller is known as code memory
or Program memory of applications. It is known as ROM memory of microcontroller also
requires a memory to store data or operands temporarily of the micro controller. The data
memory of the 8051 is used to store data temporarily for operation is known RAM memory.
8051 microcontroller has 4K of code memory or program memory (ROM) and also 128 bytes
of data memory of RAM.
BUS
Basically Bus is a collection of wires which work as a communication channel or medium for
transfer of Data. These buses consist of 8, 16 or more wires of the microcontroller. Thus,
these can carry 8 bits, 16 bits simultaneously.
Address Bus:

Microcontroller 8051 has a 16 bit address bus for transferring the data. It is used to address
memory locations and to transfer the address from CPU to Memory of the microcontroller.
Data Bus:
Microcontroller 8051 has 8 bits of the data bus, which is used to carry data of particular
applications.
Oscillator
It requires clock pulses for its operation of microcontroller applications. For this purpose,
microcontroller 8051 has an on-chip oscillator which works as a clock source for Central
Processing Unit of the microcontroller. The output pulses of oscillator are stable. Therefore, it
enables synchronized work of all parts of the 8051 Microcontroller.
Input/output Port
Normally microcontroller is used in embedded systems to control the operation of machines
in the microcontroller. Therefore, to connect it to other machines, devices or peripherals we
require I/O interfacing ports in the microcontroller interface. For this purpose microcontroller
8051 has 4 input, output ports to connect it to the other peripherals
Timers/Counters
8051 microcontroller has two 16 bit timers and counters. These counters are again divided
into a 8 bit register. The timers are used for measurement of intervals to determine the pulse
width of pulses.
3. Pin diagram of 8051

Fig. 2 Pin diagram of 8051

 Pins 1 to 8 − These pins are known as Port 1. This port doesn’t serve any other
functions. It is internally pulled up, bi-directional I/O port.
 Pin 9 − It is a RESET pin, which is used to reset the microcontroller to its initial
values.
 Pins 10 to 17 − These pins are known as Port 3. This port serves some functions like
interrupts, timer input, control signals, serial communication signals RxD and TxD,
etc.
  Pins 18 & 19 − These pins are used for interfacing an external crystal to get the
system clock.
 Pin 20 − This pin provides the power supply to the circuit.
 Pins 21 to 28 − These pins are known as Port 2. It serves as I/O port. Higher order
address bus signals are also multiplexed using this port.
 Pin 29 − This is PSEN pin which stands for Program Store Enable. It is used to read a
signal from the external program memory.
 Pin 30 − This is EA pin which stands for External Access input. It is used to
enable/disable the external memory interfacing.
 Pin 31 − This is ALE pin which stands for Address Latch Enable. It is used to
demultiplex the address-data signal of port.
 Pins 32 to 39 − These pins are known as Port 0. It serves as I/O port. Lower order
address and data bus signals are multiplexed using this port.
 Pin 40 − This pin is used to provide power supply to the circuit.

4. External memories

Internal RAM of 8051 Microcontroller

The 8051 has 128-bytes of internal RAM from location 00H to 7FH. These 128-bytes of
space is also divided into some other parts. These are as follows
 The first one is 32-bytes of working registers. The address range is 00H to 1FH.
These 32-bytes of spaces are again divided into four register banks.
o Register Bank 0. Address range (00H to 07H)
o Register Bank 1. Address range (08H to 0FH)
o Register Bank 2. Address range (10H to 17H)
o Register Bank 3. Address range (18H to 1FH)
 The second part is 16-bytes of bit addressable registers. It ranges from 20H to 2FH.
 The last part is 80-bytes of general purpose area. This space also used as a stack. It
ranges from 30H to 7FH.
 Fig.3 Internal RAM allocation
External RAM addressing of 8051 Microcontroller
The 8051 has only 128-bytes of internal RAM. So if it is needed to expand the RAM
memory, we have to use the external RAMs with proper addressing schemes. In 8051, the pin
P3.7 is used for Reading signal (RD) and the pin P3.6 is used for Write signal (WR). These
read and write pins are connected to the RAM for reading and writing data. The port P2 (8-
bit) is used for higher order 8-bit addressing, and port P0 (8-bit) is used for lower order
addressing. The lower order 8-bit (P0) can also be used as a data bus. For the multi-tasking

Fig.4 A typical example of external RAM connected to 8051

facility, we need another chip called 74LS373 to hold the lower order addresses while the
port P0 is acting like data bus. The higher order address pins can be used for chip selection in
case of multiple RAMs.
 Fig.4 shows 16K-bytes of external RAM connected to 8051. For 16K it needs 14-bits
for address selection. Other two pins A14 and A15 are connected to the chip enable (CE) pin
of the RAM chip.
5. Counters & Timers
Many of the microcontroller applications require counting of external events such as
frequency of the pulse trains and generation of precise internal time delays between computer
actions. Both these tasks can be implemented by software techniques, but software loops for
counting, and timing will not give the exact result rather more important functions are not
done. To avoid these problems, timers and counters in the micro-controllers are better options
for simple and low-cost applications. These timers and counters are used as interrupts in 8051
microcontroller.
There are two 16-bit timers and counters in 8051 microcontroller: timer 0 and timer 1.
Both timers consist of 16-bit register in which the lower byte is stored in TL and the higher
byte is stored in TH. Timer can be used as a counter as well as for timing operation that
depends on the source of clock pulses to counters.

Fig.5 Timer & control

Counters and Timers in 8051 microcontroller contain two special function registers: TMOD
(Timer Mode Register) and TCON (Timer Control Register), which are used for activating
and configuring timers and counters.
Timer Mode Control (TMOD): TMOD is an 8-bit register used for selecting timer or
counter and mode of timers. Lower 4-bits are used for control operation of timer 0 or counter
0, and remaining 4-bits are used for control operation of timer 1 or counter 1.This register is
present in SFR register, the address for SFR register is 89th.
Gate: Every timer has a means of starting and stopping. Some timers do this by software,
some by hardware, and some have both software and hardware controls. 8051 timers have
both software and hardware controls. The start and stop of a timer is controlled by software
using the instruction SETB TR1 and CLR TR1 for timer 1, and SETB TR0 and CLR
TR0 for timer 0.
 Fig. 6 Timer Mode control (TMOD)
The SETB instruction is used to start it and it is stopped by the CLR instruction. These
instructions start and stop the timers as long as GATE = 0 in the TMOD register. Timers can
be started and stopped by an external source by making GATE = 1 in the TMOD register.
C/T: If the C/T bit is ‘1’, then it is acting as a counter mode, and similarly when set C/T=0
then it is acting as a timer mode.
Mode select bits: The M1 and M0 are mode select bits, which are used to select the timer
operations. There are four modes to operate the timers.
Mode 0: This is a 13-bit mode that means the timer operation completes with “8192” pulses.
Mode 1: This is a16-bit mode, which means the timer operation completes with maximum
clock pulses that “65535”.
Mode 2: This mode is an 8-bit auto reload mode, which means the timer operation completes
with only “256” clock pulses.
Mode 3: This mode is a split-timer mode, which means the loading values in T0 and
automatically starts the T1.
Timer Control Register (TCON): TCON is another register used to control operations of
counter and timers in microcontrollers. It is an 8-bit register wherein four upper bits are
responsible for timers and counters and lower bits are responsible for interrupts.
TF1 TR1 TF0 TR0 IE1 IT0 IE0 IT0

Fig. 7 Timer Control Register (TCON)

TF1: The TF1 stands for ‘timer1’ flag bit. Whenever calculating the time-delay in timer1, the
TH1 and TL1 reaches to the maximum value that is “FFFF” automatically.
TR1: The TR1 stands for timer1 start or stop bit. This timer starting can be through software
instruction or through hardware method.
TF0: The TF0 stands for ‘timer0’ flag-bit. Whenever calculating the time delay in timer1, the
TH0 and TL0 reaches to a maximum value that is ‘FFFF’, automatically.
TR0: The TR0 stands for ‘timer0’ start or stop bit; this timer starting can be through software
instruction or through hardware method.
7. Serial Communication

Microcontrollers need to communicate with external devices such as sensors, computers and
so on to collect data for processing. Data communication is generally done by means of two
methods – Parallel and Serial mode. In parallel mode data bits are transferred faster using
more data pins. But when comes to a Microcontroller, we cannot afford to dedicate many
pins for data transfer.
Serial communication may be synchronous or asynchronous. In synchronous communication,
the transmitter also transmits a clock along with data. This clock is used for synchronization
between transmitter and receiver devices In an asynchronous transfer of data, there is no
clock.
Method of serial communication:
There are two methods of Serial Communication:
SYNCHRONOUS: Transfer the block of data (characters) between sender and receiver
spaced by fixed time interval. This transmission is synchronized by an external clock.

Fig.8 Synchronous & Asynchronous communication

ASYNCHRONOUS: There is no clock involved here and transmission is synchronized by

special signals along the transmission medium. It transfers a single byte at a time between
sender and receiver along with inserting a start bit before each data character and a stop bit at
its termination so that to inform the receiver where the data begins and ends.
We use USART and UART for serial communications. USART or UART is a
microcontroller peripheral which converts incoming and outgoing bytes of data into a serial
bit stream. Both have same work but with different methods which is explained below.
USART:
USART stands for Universal Synchronous/Asynchronous Receiver-Transmitter. USART
uses external clock so it needs separate line to carry the clock signal. Sending peripheral
generates a clock and the receiving peripheral recover from the data stream without knowing
the baud rate ahead of time. By use of external clock, USART’s data rate can be much higher
(up to rates of 4 Mbps) than that of a standard UART.
UART:
It stands for Universal Asynchronous Receiver-Transmitter. A UART generates its internal
data clock to the microcontroller. It synchronizes that clock with the data stream by using the
start bit transition. The receiver needs the baud rate to know ahead of time to properly receive
the data stream.
8051 SERIAL COMMUNICATION programming registers
8051 microcontroller has a built-in serial port called UART. We can easily read and write
values to the serial port. For using serial port we simply need to configure the serial port:
 Operation mode (how many data bits we want)

 Baud rate

There are 21 Special function registers (SFR) in 8051 microcontroller and 21 unique
locations are for these 21 SFR. Each of these register is of 1 byte size. The “Serial Control”
(SCON) is the SFR which is used to configure serial port.
SM0 SM1 SM2 REN TB8 RB8 T1 R1

Fig. 9 SCON Register

SM0 SM1 Mode Baud rate

0 0 Serial mode 0 1/12 Oscillator frequency
0 1 Serial mode 1 Determined by timer
1 0 Serial mode 2 1/64 or 1/32 Oscillator frequency
1 1 Serial mode 3 Determined by timer

SM2: Enable multiprocessor

Enable multiprocessor communication in modes 2 and 3 (for 9 bit UART).
REN: Receiver Enable
Set/clear by software to enable/disable receive operation
TB8: Transmit bit 8
Set or clear by software. The 9 bits will be transmitted in mode 2 and 3.
TB8 = 1, a value is written to the serial port, 9th bit of data = 1.
TB8 = 0, 9th bit of data = 0, RI will not set.
RB8: Receive bit 8
Set or clear by software. The 9 bits will be received in mode 2 and 3. First eight bits are the
data received and 9th bit received will be placed in RB8.
TI: Transmit Interrupt flag
Set by hardware when a byte is transmitted completely. Now the port is free and ready to
send the next byte. This bit must be cleared by software.
RI: Receive Interrupt flag
Set by hardware when a byte has been completely received. This lets the program to know
that it needs to read the value quickly before another byte is read. This bit must be cleared by
software.
7. Interrupts

Interrupts are the events that temporarily suspend the main program, pass the control to the
external sources and execute their task. It then passes the control to the main program where
it had left off.
Interrupts are of different types like software and hardware, maskable and non-maskable,
fixed and vector interrupts, and so on. Interrupt Service Routine (ISR) comes into the picture
when interrupt occurs, and then tells the processor to take appropriate action for the interrupt,
and after ISR execution, the controller jumps into the main program.
Types of Interrupts in 8051 Microcontroller
The 8051 microcontroller can recognize five different events that cause the main program to
interrupt from the normal execution. These five sources of interrupts in 8051are:
1. Timer 0 overflow interrupt- TF0

2. Timer 1 overflow interrupt- TF1

3. External hardware interrupt- INT0

4. External hardware interrupt- INT1

5. Serial communication interrupt- RI/TI

The Timer and Serial interrupts are internally generated by the microcontroller, whereas the
external interrupts are generated by additional interfacing devices or switches that are
externally connected to the microcontroller. These external interrupts can be edge triggered
or level triggered. When an interrupt occurs, the microcontroller executes the interrupt
service routine so that memory location corresponds to the interrupt that enables it. The
Interrupt corresponding to the memory location is given in the interrupt vector table below
Table 3 Interrupt vector table

Interrupt Interrupt vector address

 External INT 0 0003H
Timer/Counter 0 000BH
External INT 1 0013H
Timer/Counter 1 001BH
Serial Port 0023H

Interrupt Structure of 8051 Micro controller

Upon ‘RESET’ all the interrupts get disabled, and therefore, all these interrupts must be
enabled by software. In all these five interrupts, if anyone or all are activated, this sets the
corresponding interrupt flags as shown in the figure. All these interrupts can be set or cleared
by bit in some special function register that is Interrupt Enabled (IE), and this in turn depends
on the priority, which is executed by IP interrupt priority register.
Interrupt Enable (IE) Register: This register is responsible for enabling and disabling the
interrupt. It is a bit addressable register in which EA must be set to one for enabling
interrupts. The corresponding bit in this register enables particular interrupt like timer,
external and serial inputs. In the below IE register, bit corresponding to 1 activates the
interrupt and 0 disables the interrupt.

EA --- --- ES ET1 EX1 ET0 EX0

Fig. 10 IE (Interrupt Enable) Register

It disables all interrupts. When EA = 0 no interrupt will be

EA IE.7
acknowledged and EA = 1 enables the interrupt individually.

- IE.6 Reserved for future use.

- IE.5 Reserved for future use.

ES IE.4 Enables/disables serial port interrupt.

ET1 IE.3 Enables/disables timer1 overflow interrupt.

EX IE.2 Enables/disables external interrupt1.

1

ET0 IE.1 Enables/disables timer0 overflow interrupt.

EX IE.0 Enables/disables external interrupt0.

0

Interrupt Priority Register (IP): It is also possible to change the priority levels of the
interrupts by setting or clearing the corresponding bit in the Interrupt priority (IP) register as
shown in the figure. This allows the low priority interrupt to interrupt the high-priority
interrupt, but prohibits the interruption by another low-priority interrupt. Similarly, the high-
priority interrupt cannot be interrupted. If these interrupt priorities are not programmed, the
microcontroller executes in predefined manner and its order is INT0, TF0, INT1, TF1, and
SI.

--- --- ---- PS PT1 PX1 PT0 PX0

Fig. 11 IP (Interrupt Priority) Register

Bit 7,6,5 – Reserved bits
Bit 4 – PS: Serial Interrupt Priority Bit
1 = Assign a high priority to serial interrupt.
0 = Assign low priority to serial interrupt.

Bit 3 – PT1: Timer1 Interrupt Priority Bit

1 = Assign high priority to Timer1 interrupt.
0 = Assign low priority to Timer1 interrupt.

Bit 2 – PX1: External Interrupt 1 Priority Bit

Bit 1 – PT0: Timer0 Interrupt Priority Bit
Bit 0 – PX0: External0 Interrupt Priority Bit

TCON Register: In addition to the above two registers, the TCON register specifies the type
of external interrupt to the 8051 microcontroller, as shown in the figure. The two external
interrupts, whether edge or level triggered, specify by this register by a set, or cleared by
appropriate bits in it. And, it is also a bit addressable register.

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Fig. 12 TCON Register

This bit is set by the processor when there is an interrupt INT1
This bit is cleared by the processor when there is jump to ISR of INT1

Set this bit (0) for an interrupt generated by a low level signal at INT1
Clear this bit (0) for an interrupt generated by a falling edge signal at INT1

This bit is set by the processor when there is an interrupt INT0

This bit is cleared by the processor when there is jump to ISR of INT0

Set this bit (0) for an interrupt generated by a low level signal at INT0
Clear this bit (0) for an interrupt generated by a falling edge signal at INT0

External Hardware Interrupt Programming

8051 microcontrollers consists of two external hardware interrupts: INT0 and INT1 as
discussed earlier. These are enabled at pin 3.2 and pin 3.3. These can be edge triggered or
level triggered. In level triggering, the low at pin 3.2 enables the interrupt, while at pin 3.2 –
the high to low transition enables the edge triggered interrupt.
8. Instruction set of 8051
Refer to the slides
7. Addressing Modes of 8051
Refer to the slides

8. Assembly Language Programming examples using 8051

Refer to the slides