DAYANANDA SAGAR ACADEMY OF TECHNOLOGY & MANAGEMENT

CURRICULUM

Scheme and Syllabus III to IV Semester

Outcome Based Education

(Academic Year 2024-2025)
Department of Electronics & Communication Engineering
3rd & 4th Semester B.E
ABOUT THE INSTITUTE
Dayananda Sagar Academy of Technology and Management- DSATM was established in 2011 with 5 UG Programmes
and 1 PG Program, the programmes are approved by All India Council for Technical Education (AICTE) New Delhi,
Affiliated to Visvesvaraya Technological University (VTU), Belagavi and DSATM is an autonomous institute from 2023-
2024.

The Dayananda Sagar Institutions is one of pioneer institutions in India and abroad with six decades of excellence in
Academic and Research. The newer campuses were necessary to accommodate the growing need of the technology
and innovation.

DSATM nurtures the students in academic, research, sports, cultural and extracurricular activities.

 Creating an academic environment to nurture and develop competent entrepreneurs, leaders and
professionals who are socially sensitive and environmentally conscious.

 Integration of Outcome Based Education and cognitive teaching and learning strategies to enhance learning
effectiveness.

 Developing necessary infrastructure to cater to the changing needs of Business and Society.

 Optimum utilization of the infrastructure and resources to achieve excellence in all areas of relevance.

 Adopting learning beyond curriculum through outbound activities and creative assignments.

 Imparting contemporary and emerging techno-managerial skills to keep pace with the changing global trends.

 Facilitating greater Industry-Institute Interaction for skill development and employability enhancement.

 Establishing systems and processes to facilitate research, innovation and entrepreneurship for holistic
development of students.

 Implementation of Quality Assurance System in all Institutional processes.

VISION OF THE INSTITUTE

To strive at creating the institution a centre of highest calibre of learning, so as to create an overall intellectual
atmosphere with each deriving strength from the other to be the best of engineers, scientists with management
& design skills.

MISSION OF THE INSTITUTE

 To serve its region, state, the nation and globally by preparing students to make meaningful contributions in
an increasing complex global society challenges.

 To encourage, reflection on and evaluation of emerging needs and priorities with state-of-the-art
infrastructure at institution.

 To support research and services establishing enhancements in technical, economic, human and cultural
development.

 To establish interdisciplinary centre of excellence, supporting/ promoting student’s implementation.

 To increase the number of Doctorate holders to promote research culture on campus.

 To establish IIPC, IPR, EDC, innovation cells with functional MOU’s supporting student’s quality growth.

QUALITY POLICY

Dayananda Sagar Academy of Technology and Management aims at achieving academic excellence through
continuous improvement in all spheres of Technical and Management education. In pursuit of excellence cutting
– edge and contemporary skills are imparted to the utmost satisfaction of the students and the concerned
stakeholders.
ABOUT THE DEPARTMENT

The Department of Electronics and Communication Engineering (ECE) was established in the year 2011. Now
a days we cannot imagine the world without Electronics & Communication Engineering that has become an
essential and inevitable part of our daily lives in almost all the fields. The Department focus is to train our
students to get strong academic knowledge in the frontier areas of both Electronics & Communication
engineering and also to make the students ready to meet real-world challenges. The Department has always
been on a high growth path and has a rich blend of young and highly-experienced regular faculty members,
most of them holding PhD from reputed universities.

The faculty members display a high level of dedication and enthusiasm towards both teaching and state-of-
the-art research with strong commitment to engineering education who work with zeal and enthusiasm to
provide a vibrant and optimum learning environment. The Department has been accredited by NBA and NAAC
for providing high standards of education. To impart quality education by establishing research and learning
environment to meet global needs and industrial standards is our department vision.

VISION OF THE DEPARTMENT

To impart quality education in the field of Electronics and Communication Engineering by

establishing research and learning environment to meet global needs and industrial
standards.

MISSION OF THE DEPARTMENT

M1: To provide quality and contemporary knowledge on latest technologies.

 M2: To develop innovation and creativity among students enabling leadership and
entrepreneurship skills with ethical values.
M3: To empower faculty with the knowledge in emerging areas of research.

M4: To ensure industry ready professionals with a research outlook.

M5: To establish center of excellence with industry and university collaborations.

PROGRAM EDUCATION OBJECTIVES (PEO’S):

PEO1: To ensure graduates with strong foundation in engineering, science and
technology for successful career in Electronics and Communication Engineering.
PEO2: Graduates shall be technically competent with ability to analyze, design,
develop, optimize and implement Electronics and Communication systems to meet
global needs.
PEO3: Graduates shall build leadership and entrepreneurship qualities with
professional ethics for the development of emerging technologies.

PROGRAM OUTCOMES (PO’s)

Engineering Graduates will be able to:

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an
engineering specialization to the solution of complex engineering problems.

2. Problem analysis: Identify, formulate, review research literature, and analyze complex engineering problems
reaching substantiated conclusions using first principles of mathematics, natural sciences, and engineering
sciences.

3. Design/development of solutions: Design solutions for complex engineering problems and design system
components or processes that meet the specified needs with appropriate consideration for the public health
and safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research methods
including design of experiments, analysis and interpretation of data, and synthesis of the information to
provide valid conclusions.

5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering
and IT tools including prediction and modelling to complex engineering activities with an understanding of
the limitations.

6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health,
safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering
practice.

7. Environment and sustainability: Understand the impact of the professional engineering solutions in societal
and environmental contexts, and demonstrate the knowledge of, and need for sustainable development.

8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the
engineering practice.

9. Individual and team work: Function effectively as an individual, and as a member or leader in diverse teams,
and in multidisciplinary settings.

10. Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write effective reports and
design documentation, make effective presentations, and give and receive clear instructions.

11. Project management and finance: Demonstrate knowledge and understanding of the engineering and
management principles and apply these to one’s own work, as a member and leader in a team, to manage
projects and in multidisciplinary environments.

12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in independent
and life-long learning in the broadest context of technological change.

PROGRAM SPECIFIC OUTCOMES (PSO’s)

PSO1: Ability to design analyze and interpret data using modern tools with strong
fundamentals of Electronics, Signal Processing and Communication, Embedded
system, Computer science, Mathematics and Management.
PSO2: Adapt to emerging technologies with innovative idea and solution for novel
problems.
PSO3: Ability to create innovative career path to be an entrepreneur and zest for
higher studies.
IPCC Course – Integrated Professional Core Course
Teaching Hours/Week (L: T:P: S) 3:0:2:0
Total Hours of Pedagogy 40 hours Theory + 20 Hours of Practical Classes
Credits: 04
Theory - Each Module 8 Hrs
Practical’s 8-10 Programs / Experiments
CIE Marks 50
SEE Marks 50
Total Marks 100
Exam Hours 3
Examination nature (SEE) Theory

 The theory part of the IPCC shall be evaluated both by CIE and SEE.
 The practical part shall be evaluated by only CIE (no SEE).
 However, questions from the practical part of IPCC shall be included in the SEE question paper.

Integrated Professional Core Course (IPCC) - 4 Credit Course

Assessment Details (both CIE and SEE)

 The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is
50%.
 The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the
SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks).
 A student shall be deemed to have satisfied the academic requirements and earned the credits allotted
to each subject/ course if the student secures a minimum of 40% (40 marks out of 100) in the sum total
of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation (CIE) for the Theory component of the IPCC (Maximum marks 50)

Internal Assessment Test (IAT):

 IPCC means practical portion integrated with the theory of the course.
 CIE marks for the theory component are 25 marks and that for the practical component is 25 marks.
 25 marks for the theory component are split into 15 marks for two Internal Assessment Tests
(Two Tests, each of 50 Marks with 01-hour 30 minutes’ duration, are to be conducted and average of
two tests to be reduced to 15 marks) and 10 marks for Two Continuous Comprehensive
Assessment(CCA) methods.
 The first Internal test at the end of 40-50% coverage of the syllabus
 The second Internal test after covering 85-90% of the syllabus.
 Scaled-down marks of the sum of two tests and other assessment methods will be CIE marks for the
theory component of IPCC (that is for 25 marks).
 The student has to secure 40% of 25 marks to qualify in the CIE of the theory component of IPCC.
The IA test questions are to be framed to map the Course Outcomes (COs), Program Outcomes (POs)
and the Revised Blooms Taxonomy (RBT) Levels. Emphasis to be given for Higher order Thinking
Skills(HOTS).

Continuous Internal Evaluation (CIE) for the practical component of the IPCC
 On completion of every experiment/program in the laboratory, the students shall be evaluated and Marks
shall be awarded on the same day.
 The CIE marks awarded in the case of the Practical component shall be based on the continuous
evaluation of the laboratory report, 05 Marks are for conducting the experiment, 05 Marks for
preparation of the laboratory record, 5 Marks for conducting Open Ended Experiments Each experiment.
Marks of all experiments’ write-ups are added to 15 marks.
 The Practical laboratory test (duration 03 hours) at the end of the 15th week of the semester/after
completion of all the experiments (whichever is early) shall be conducted for 50 Marks and scaled down
to 5 Marks.
 The open-ended experiment after completion of all the experiments shall be conducted for 20 marks with
a split-up for 5 Marks for writeup, 10 Marks for Execution, and 5 Marks for Viva-Voce.
Marks for writeup, Execution and Viva-Voce is added and scaled down to 05 marks.
 Scaled-down marks of write-up evaluations and tests added will be CIE marks for the laboratory
component of IPCC for 25 marks.
 The student has to secure 40% of 25 marks to qualify in the CIE of the practical component of the IPCC.

Semester End Examination (SEE) for IPCC Theory

SEE will be conducted as per the scheduled timetable, with common question papers for the course (duration
03 hours)
 The question paper will have ten questions. Each question is set for 20 marks.
 The question paper shall be set for 100 Marks. The medium of the question paper shall be English. The
duration of SEE is 03 hours.
 There will be 2 questions from each module. Each of the two questions under a module (with a maximum
of 3 sub-questions), should have a mix of topics under that module. The two questions shall be of same
course outcome, program outcome and Blooms RBT level. Emphasis to be given for higher order RBT
levels.
 The students have to answer 5 full questions, selecting one full question from each module.
 Marks scored by the student shall be proportionally scaled down to 50 Marks.
 The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical portion will have a
CIE component only.
 Questions mentioned in the SEE paper may include questions from the practical component.

Continuous and Comprehensive Assessment (CCA):

Two of continuous and comprehensive assessment (CCA) to be conducted to attain COs and POs, evaluated
each for 50 Marks. Total Marks scored will be (CCA1+CCA2)/2 and scaled down to 10 Marks.
 CCA1 after 4th week and CCA2 after 9th week. The Assessment will be through rubrics.
 CCA as project-based learning,
o CCA is evaluated for 50 Marks with review 1 of 20 Marks after and review 2 of 30 Marks includes
project demonstration/competition and report submission.
o The evaluation of review 1 after 6th weeks of semester and review 2 after 12th week of semester
with project demonstration and submission of the report

Total score for CCA is 10 Marks

Total Marks scored for theory component of CIE (IAT+ CCA) is 25 Marks

Possible Continuous and Comprehensive Assessment (CCA):

 Project based, Problem Based, Building Models, Lab-to-Land, Mobile Studio, Design and Programming
Contest, Certification, Concept Map (Collage presentation/poster presentation), Case studies, Think-
Pair-Share, Flipped classroom,
 The assessment of these techniques shall be in rubrics.
 The faculty can adopt any other CCA method of implementation and its assessment with prior approval
of Program Assessment Committee (PAC).
4 Credits Courses – Integrated Professional Core Course (IPCC)

Assessment Component Type of Assessments Syllabus Coverage Maximu Average Reduced Minimum Evaluation Details
Method m Marks Marks Passing
Marks
50 ---- ---- 20
Total CIE Theory + Practical
Internal Assessment Test Module – 1 to 2.5 50 Average of Two
(IAT) – I 15 6 Internal test each
Theory (50+50) / 2 of 50 Marks scale
Internal Assessment Test Module – 2.5 to 5 50 down the marks to
(IAT) – II 15 Marks

Two CCA methods

CCA-1- Pedagogical 50 as per VTU Clause
Continuous Initiatives / Activity based 22OB4.2 of
regulations to be
Comprehensive learning Considering all the (50+50) / 2 10 4
CIE adopted. If CCA
Assessment Modules chosen is Project
(CCA) Based Learning,
CCA-2- Pedagogical
then one
Initiatives/ Activity based 50 assessment
learning method may be
adopted
25 10 Scale down Marks of
Total CIE Theory IAT and CCA to 25
 Performance- Performance of the
Continuous 05 Experiment (On
Evaluation of completion of every
each experiment/progra
m in the laboratory,
experiment 15 the students shall
Average of all be evaluated and
Conduction of Experiments Record 05 Experiments marks shall be
awarded on the
same day. 20
15 4 marks are for
Observation 05 conducting the
CIE book experiment and
calculations/observ
Practical ations/output)
Write up 15 One Internal
50 ---- 05 4 Practical Test after
Execution 25 conduction of all
Practical Test
Experiments for 50
Viva-voce 10
Marks
Write up 05 One experiment
Open Ended Experiment for 20 marks.
Execution 10 ---- 05 2
20 20 marks reduced
Viva-voce 05 to 05 marks

Scale down Marks of

Experiments,
Total CIE Practical 25 10 Record, Observation,
Practical Test and
Open-Ended
Experiment
 Entire theory SEE Exam is theory
syllabus including Exam conducted
SEE Theory exam questions from lab 100 ---- 50 20 for 100 Marks,
Component in scored Marks are
respective Modules scaled down to 50
Marks

CIE + SEE 100 ---- ---- 40

 The Minimum Marks to be secured in CIE to appear for SEE shall be 10 (40% of Maximum Marks – 25) in the Theory Component and 10 (40% of Maximum Marks
– 25) in the Practical component.
 The Laboratory Component for the IPCC shall be for CIE only.
 However, in SEE, the Questions from the Laboratory Component shall be included in the respective Modules only.
Note: If few of the 3 Credit Courses are Integrated course type, for such courses the method suggested for 4 Credit IPCC Course shall be followed
 Dayananda Sagar Academy of Technology & Management
(Autonomous Institute under VTU)

Semester : 3rd Semester

Course Title : Digital Electronic Circuits
Course Code : 23CECE33
Course Type
: Integrated
(Theory/ Practical/ Integrated)
Category : IPCC
Stream : ECE CIE : 50 Marks
Teaching hours/ week (L:T:P:S) : 3:0:2:0 SEE : 50 Marks
: 40 hours Theory + 20 :
Total Hours SEE
Hours of Practical Classes 3 hrs
Duration
Credits : 4

Course Learning Objectives: Students will be able to:

Sl. No Course Objectives
1 To understand the basic principles of combinational and sequential logic circuits.
To impart the concepts of simplifying Boolean expressions using K-map techniques and Quine
2
McCluskey minimization techniques.
3 To comprehend the basic elements of combinational and Sequential Circuits and its applications.
4 To provide the fundamental design concepts and analysis of sequential logic circuits using FSM.
5 To train on EDA tools used in simulating and debugging the combinational and sequential circuits.

Teaching-Learning Process
Pedagogical Initiatives:
Some sample strategies to accelerate the attainment of various course outcomes are listed below:
 Adopt different teaching methods to attain the course outcomes.
 Include videos to demonstrate various concepts in Digital Electronic Circuits.
 Encourage collaborative (Group) Learning to encourage team building.
 Ask at least three HOTS (Higher-order Thinking Skills) module-wise questions to promote critical thinking.
 Adopt Problem-Based Learning (PBL), which fosters students’ analytical skills, and develops thinking
skills such as evaluating, generalizing, and analyzing information rather than simply recalling it.
 Show different ways to solve a problem and encourage the students to come up with creative and optimal
solutions.
 Discuss various case studies to map with real-world scenarios and improve the understanding.
 Devise innovative pedagogy to improve Teaching-Learning Process (TLP).
 Scheme of Teaching and Examinations for BE Programme -2024-25
Outcome Based Education and Choice Based Credit System (CBCS)
(Effective from the Academic Year 2024-25)
DSATM

COURSE CURRICULUM
Module
Topics Hours
No.
Combinational Logic Circuit: Introduction to combinational logic, Design procedure,
Generation of switching equations from truth tables, Karnaugh maps-3, and 4 variables,
8 hrs
incompletely specified functions (Don’t Care terms), Simplifying Min term / Max term
1 equations, PI and EPI, Quine-McCluskey minimization technique, Quine-McCluskey using
don’t care terms.

Pedagogy Problem Solving

Design of Combinational Logic: Cascading full adders/subtractor, 4-bit Parallel
adder/subtractor, Carry Look ahead adder, Decoders, Encoders, Digital multiplexers,
2 8 hrs
Demultiplexer, Design of Boolean function using combinational circuits, Binary comparators.

Pedagogy Case Study

Sequential Circuits: Basic Bistable Element, Latches and its types, Flip-flops: SR, JK, D
3 and T, The Master-Slave JK Flip-Flop, (Pulse triggered Flip Flop), Characteristic Equations, 8 hrs
Shift Registers, Design of 4-bit Universal shift register, Application of shift registers.

Pedagogy Presentation / Mobile Studio

Counters: Binary Ripple Counters, Synchronous Binary counters, Design of a Synchronous
counters, Design of a Synchronous Mod-n Counter using clocked JK, SR, D and T Flip-Flops, 8 hrs
4
Counters based on Shift Registers.

Pedagogy Demonstration
Finite State Machine (FSM): Mealy and Moore Models, State Machine Notation, Synchronous
Sequential Circuit Analysis and Design, Guidelines and Construction of state graph.
8 hrs
FSM Design: Code Converter, Serial Adder with accumulator, Design of Binary Multiplier and Binary
5 Divider.

Pedagogy Think Pair and Share

 Pedagogical Initiatives (Not limited to):
 Think Pair and Share (Blended Learning): provides an opportunity for students to learn from
one another
 Problem Solving: encourages cognitive thinking and enables creative problem solving
 Poster Presentation: allows students to represent the concepts visually in order to
understand the topics easily.
 Case studies: maps different domains in real time applications
 Demonstration: exhibits the implementation process

List of Programs:
Sl. No. Experiments/Programs COs
1 Design and implement 2,3,4
(i) Half Adder & Full Adder using NAND gates.
(ii) Half subtractor & Full subtractor using NAND gates.
2 Design and implement 4-bit Parallel Adder/ Subtractor using IC 7483. 2,3,4
3 Design and implement BCD to excess-3 code conversion and vice-versa. 2,3,4
4 Design and Implementation of 2,3,4
(i) 1- bit comparator
(ii) 5-bit Magnitude Comparator using IC 7485.
5 . Realize 2,3,4
(i) Adder & Substractor using IC 74153.
(ii) 4-variable function using IC 74151(8:1MUX).
6 Realize 2,3,4
(i) Adder and Substractors using IC74139.
(ii) Binary to Gray code conversion & vice versa (74139)
7 Realize the following flip-flops using IC 7476: Master-Slave JK, D & T Flip-Flops. 2,3,4
8 Realize the following shift registers using IC 7495 2,3,4
(i) SISO (ii) SIPO (iii) PISO (iv) PIPO (v) Ring and (vi) Johnson counter.
9 Realize 2,3,4
 (i) Mod-N Asynchronous Counter using IC7490 and
(ii) Mod-N Synchronous counter using IC74192
10 Design Pseudo Random Sequence generator using 7495 2,3,4
Open ended Programs
1 Realize asynchronous and synchronous counter using Multisim tool. 2,3,4,5
2 Design Serial Adder with Accumulator and Simulate using Simulation tool. 2,3,4,5
3 Design Binary Multiplier and Simulate using Simulation tool. 2,3,4,5

Text Books :

Sl. No. Title of the Book/Name of the author/Name of the publisher/Edition and Year

1 Digital Logic Applications and Design by John M Yarbrough, Thomson Learning, 2001.

2 Digital Principles and Design by Donald. D. Givone, McGraw Hill, 2002.

3 Fundamentals of logic design, by Charles H Roth Jr., Cengage Learning

Reference Books :

1 Logic Design, by Sudhakar Samuel, Pearson/ Sanguine, 2007

2 SWITCHING THEORY AND LOGIC DESIGN, by Kumar A. Anand, 3rd Edition.

3 Digital Logic & Computer Design by M. Morris Mano, First Edition, ISBN- 978-9332542525

Course Outcomes: At the end of the course, the student will be able to:
 RBT RBT Level
Level Indicator
CO Course Outcomes
Describe the different combinational and sequential logic circuits using logic
CO1 L2 Understanding
gates.
Apply various minimization techniques for simplification of Boolean functions to
CO2 study different combinational and sequential logic circuits using logic gates and L3 Apply
Verilog model of programming.
Design the combinational and sequential circuits for given specifications using
CO3 L3 Apply
logic gates
Analyze the required combinational and sequential circuits for the given real time
CO4 L4 Analyse
examples.
Implement and evaluate real-time examples using combinational and sequential Evaluate
CO5 L5
circuit with suitable EDA tool.

Mapping of Course Outcomes to Program Outcomes:

CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
CO1 - - - - - - - - - - - - 2 - -
CO2 3 - - - - - - - - - - - 2 - -
CO3 - 3 - - - - - - - - - 2 - -
CO4 - 3 - - - - - - - - - 2 - -

CO5 - - - 2 2 - - - 2 2 - 1 2 - -

Weblinks and Video Lectures (e-Resources)

1 https://E-learning.vtu.ac.in

2 https://www.coursera.org/courses/digital-circuits

3 https://nptel.ac.in/courses/digital-electronic-circuits
4 http://en.wikipedia.org/wiki/digital system design

CIE- Continuous Internal Evaluation (50 Marks)

 Theory Practical
Bloom’s Continuous Assessment Tests Continuous Comprehensive Assessment
Category (CCA)
(IAT) Practical Test
IAT-1 IAT-2 CCA-1 CCA-2
50 Marks 50 Marks 50 Marks 50 Marks
Remember - - - -

Understand 10 10 - -

Apply 20 20 30

Analyse 20 20 25 25 20

Evaluate 25 25

Create

CIE Course Assessment Plan

Marks Distribution
Test-1 Test-2 Total Weightage
Marks
CO’s Module-1 Module-2 Module 2 to Module-2.5 Module-4 Module-5
2.5 to 3
CO1 5 5 5 5 20 20%
CO2 10 10 10 10 40 40%
CO3 10 10 10 10 40 40%
CO4
CO5
Total 15 25 10 10 25 15 100

SEE- Semester End Examination (50 Marks)

Bloom’s Category SEE Marks
(90% Theory+10% Practical Questions)
Remember -
Understand 33
Apply 35
Analyse 32
Evaluate -
Create -

SEE Course Plan

Marks Distribution
Total Weightage
Marks
CO’s
Module-1 Module-2 Module 3 Module-4 Module-5
CO1 7 6 10 10 33 33%
CO2 8 10 7 10 35 35%
CO3 5 10 7 10 32 32%
CO4
CO5
Total 20 20 20 20 20 100 100