ACS710-Datasheet Sensor corrente LG Piso teto

ACS710
120 kHz Bandwidth, High-Voltage Isolation

Current Sensor with Integrated Overcurrent Detection
FEATURES AND BENEFITS DESCRIPTION

▪ Industry-leading noise performance with greatly improved The Allegro™ ACS710 current sensor provides economical and
bandwidth through proprietary amplifier and filter design precise means for current sensing applications in industrial,
techniques commercial, and communications systems. The device is offered
▪ Small footprint package suitable for space-constrained in a small footprint surface-mount package that allows easy
applications implementation in customer applications.
▪ 1 mΩ primary conductor resistance for low power loss
The ACS710 consists of a precision linear Hall sensor integrated
▪ High isolation voltage, suitable for line-powered
circuit with a copper conduction path located near the surface
applications
of the silicon die. Applied current flows through the copper
▪ User-adjustable Overcurrent Fault level
conduction path, and the analog output voltage from the Hall
▪ Overcurrent Fault signal typically responds to an
sensor linearly tracks the magnetic field generated by the
overcurrent condition in < 2 μs
applied current. The accuracy of the ACS710 is maximized
▪ Integrated shield virtually eliminates capacitive coupling
with this patented packaging configuration because the Hall
from current conductor to die due to high dV/dt voltage
element is situated in extremely close proximity to the current
transients
to be measured.
▪ Filter pin capacitor improves resolution in low bandwidth
applications High-level immunity to current conductor dV/dt and stray
▪ 3 to 5.5 V single supply operation electric fields, offered by Allegro proprietary integrated shield
▪ Factory-trimmed sensitivity and quiescent output voltage technology, results in low ripple on the output and low offset
▪ Chopper stabilization results in extremely stable quiescent drift in high-side, high-voltage applications.
output voltage
The voltage on the Overcurrent Input (VOC pin) allows
▪ Ratiometric output from supply voltage
customers to define an overcurrent fault threshold for the device.
When the current flowing through the copper conduction path
CB Certificate Number:
US-23711-A2-UL (between the IP+ and IP– pins) exceeds this threshold, the open
drain Overcurrent Fault pin will transition to a logic low state.
PACKAGE: 16-Pin SOIC Hall-Effect IC Factory programming of the linear Hall sensor inside of the
Package (suffix LA) ACS710 results in exceptional accuracy in both analog and
digital output signals.
The internal resistance of the copper path used for current
sensing is typically 1 mΩ, for low power loss. Also, the current
conduction path is electrically isolated from the low-voltage
Not to scale Continued on the next page…
Typical Application Circuit

VCC
1 16 Fault_EN RH
IP+ FAULT_EN
2 15 RH, RL Sets resistor divider reference for VOC
IP+ VOC
3 ACS710 14 RL CF Noise and bandwidth limiting filter capacitor
IP+ VCC
4 13 RPU COC Fault delay setting capacitor, 22 nF maximum
IP IP+ FAULT
5 12 COC
B 0.1 µF A Use of capacitor required
IP– VIOUT
6 11 VIOUT
IP– FILTER Use of resistor optional, 330 kΩ recommended.
7 10 CF B If used, resistor must be connected between
IP– VZCR F̄¯ĀŪ¯L̄¯T̄¯ pin and VCC.
8 9 1 nF
IP– GND A
ACS710-DS, Rev. 16 January 30, 2020

MCO-0000196
ACS710 Current Sensor with Integrated Overcurrent Detection
DESCRIPTION (continued)
sensor inputs and outputs. This allows the ACS710 family of sensors Pb‑based solder balls, currently exempt from RoHS. The device is
to be used in applications requiring electrical isolation, without the fully calibrated prior to shipment from the factory.
use of opto-isolators or other costly isolation techniques.
The ACS710 is provided in a small, surface-mount SOIC16 package. Applications include:
The leadframe is plated with 100% matte tin, which is compatible • Motor control and protection
with standard lead (Pb) free printed circuit board assembly processes. • Load management and overcurrent detection
Internally, the device is Pb-free, except for flip-chip high-temperature • Power conversion and battery monitoring / UPS systems
SELECTION GUIDE
Sens (typ)
IP Latched TA
Part Number at VCC = 5 V Packing [1]
(A) Fault (°C)
(mV/A)
ACS710KLATR-6BB-T [2][3] ±6 151
ACS710KLATR-10BB-T [2] ±10 85
Yes –40 to 125 Tape and Reel, 1000 pieces per reel
ACS710KLATR-12CB-T [2] ±12.5 56
ACS710KLATR-25CB-T [2] ±25 28
ACS710KLATR-6BB-NL-T [2] ±6 151
ACS710KLATR-10BB-NL-T [2] ±10 85
No –40 to 125 Tape and Reel, 1000 pieces per reel
ACS710KLATR-12CB-NL-T [2] ±12.5 56
ACS710KLATR-25CB-NL-T [2] ±25 28
[1] Contact Allegro for packing options.

[2] Variant not intended for automotive applications.
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Unit
Supply Voltage VCC 8 V
Filter Pin VFILTER 8 V
Analog Output Pin VIOUT 32 V
Overcurrent Input Pin VOC 8 V
¯ĀŪ¯L̄¯T̄¯ Pin
Overcurrent F̄ V F̄¯ĀŪ¯L̄¯T̄¯ 8 V
Fault Enable (FAULT_EN) Pin VFAULTEN 8 V
Voltage Reference Output Pin VZCR 8 V
DC Reverse Voltage: VCC, FILTER, VIOUT, VOC,
¯ĀŪ¯L̄¯T̄¯, FAULT_EN, and VZCR Pins VRdcx –0.5 V
F̄
Excess to Supply Voltage: FILTER, VIOUT, VOC, Voltage by which pin voltage can exceed the VCC pin
¯ĀŪ¯L̄¯T̄¯, FAULT_EN, and VZCR Pins VEX 0.3 V
F̄ voltage
Output Current Source IIOUT(Source) 3 mA
Output Current Sink IIOUT(Sink) 1 mA
Operating Ambient Temperature TA Range K –40 to 125 °C
Junction Temperature TJ(max) 165 °C
Storage Temperature Tstg –65 to 170 °C
ISOLATION CHARACTERISTICS
Characteristic Symbol Notes Rating Unit
Tested ±5 pulses at 2/minute in compliance to IEC 61000-4-5
Dielectric Surge Strength Test Voltage VSURGE 6000 V
1.2 µs (rise) / 50 µs (width).
Agency type-tested for 60 seconds per IEC/UL 60950-1 (2nd Edition). 3600 VRMS
Dielectric Strength Test Voltage* VISO
Agency type-tested for 60 seconds per UL 1577. 3000 VRMS
Maximum approved working voltage for basic (single) isolation 870 VPK or VDC
Working Voltage for Basic Isolation VWVBI
according to IEC/UL 60950-1 (2nd Edition). 616 VRMS
Clearance DCL Minimum distance through air from IP leads to signal leads. 7.5 mm
Creepage DCR Minimum distance along package body from IP leads to signal leads. 7.5 mm
*Production tested for 1 second at 3600 VRMS in accordance with both UL 1577 and IEC/UL 60950-1 (edition 2).
THERMAL CHARACTERISTICS
Characteristic Symbol Test Conditions Value Unit
When mounted on Allegro demo board with 1332 mm2
(654 mm2
on com-
ponent side and 678 mm2 on opposite side) of 2 oz. copper connected to
Package Thermal Resistance RθJA the primary leadframe and with thermal vias connecting the copper layers. 17 °C/W
Performance is based on current flowing through the primary leadframe
and includes the power consumed by the PCB.
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Functional Block Diagram

Latching Version
VCC
D Q
CLK
R
Hall POR
POR Fault Latch
Bias
FAULT_EN FAULT Reset
Drain
– FAULT
VOC
+
2VREF
Control
OC Fault Logic
3 mA
Fault
Comparator
– VZCR
Sensitivity
Trim
+
IP+
Signal VIOUT
Recovery
RF(INT)
Hall
IP– Amplifier
VOUT(Q)
Trim
GND FILTER
Pinout Diagram Terminal List Table, Latching Version

Number Name Description
IP+ 1 16 FAULT_EN Sensed current copper conduction path pins. Terminals for current being sensed;
1,2,3,4 IP+
IP+ 2 15 VOC fused internally, loop to IP– pins; unidirectional or bidirectional current flow.
IP+ 3 14 VCC
Sensed current copper conduction path pins. Terminals for current being sensed;
13 FAULT 5,6,7,8 IP–
IP+ 4 fused internally, loop to IP+ pins; unidirectional or bidirectional current flow.
IP– 5 12 VIOUT
9 GND Device ground connection.
IP– 6 11 FILTER
IP– 7 10 VZCR Voltage Reference Output pin. Zero current (0 A) reference; output voltage on this
10 VZCR
IP– 8 9 GND pin scales with VCC . (Not a highly accurate reference.)
Filter pin. Terminal for an external capacitor connected from this pin to GND to set
11 FILTER
the device bandwidth.
Analog Output pin. Output voltage on this pin is proportional to current flowing
12 VIOUT
through the loop between the IP+ pins and IP– pins.
¯ĀŪ¯L̄¯T̄¯ Overcurrent Fault pin. When current flowing between IP+ pins and IP– pins
13 F̄
exceeds the overcurrent fault threshold, this pin transitions to a logic low state.
14 VCC Supply voltage.
Overcurrent Input pin. Analog input voltage on this pin sets the overcurrent fault
15 VOC
threshold.
16 FAULT_EN Enables overcurrent faulting when high. Resets F̄¯ĀŪ¯L̄¯T̄¯ when low.
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Functional Block Diagram

Non-Latching Version
VCC
Hall
POR
Bias
Drain
–
VOC FAULT
2VREF
+
FAULT_EN FAULT Reset

3 mA
OC Fault
Fault VZCR
Sensitivity Comparator
Trim
IP+
Signal VIOUT
Recovery
RF(INT)
Hall
IP– Amplifier
VOUT(Q)
Trim
GND FILTER
Pinout Diagram Terminal List Table, Non-Latching Version

Number Name Description
IP+ 1 16 FAULT_EN Sensed current copper conduction path pins. Terminals for current being sensed;
1,2,3,4 IP+
IP+ 2 15 VOC fused internally, loop to IP– pins; unidirectional or bidirectional current flow.
IP+ 3 14 VCC
Sensed current copper conduction path pins. Terminals for current being sensed;
IP+ 4 13 FAULT 5,6,7,8 IP–
fused internally, loop to IP+ pins; unidirectional or bidirectional current flow.
IP– 5 12 VIOUT
11 FILTER
9 GND Device ground connection.
IP– 6
IP– 7 10 VZCR Voltage Reference Output pin. Zero current (0 A) reference; output voltage on this
10 VZCR
IP– 8 9 GND pin scales with VCC . (Not a highly accurate reference.)
Filter pin. Terminal for an external capacitor connected from this pin to GND to set
11 FILTER
the device bandwidth.
Analog Output pin. Output voltage on this pin is proportional to current flowing
12 VIOUT
through the loop between the IP+ pins and IP– pins.
¯ĀŪ¯L̄¯T̄¯ Overcurrent Fault pin. When current flowing between IP+ pins and IP– pins
13 F̄
exceeds the overcurrent fault threshold, this pin transitions to a logic low state.
14 VCC Supply voltage.
Overcurrent Input pin. Analog input voltage on this pin sets the overcurrent fault
15 VOC
threshold.
16 FAULT_EN Enables overcurrent faulting when high.
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COMMON OPERATING CHARACTERISTICS: Valid at TA = –40°C to 125°C, VCC = 5 V, unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Units
ELECTRICAL CHARACTERISTICS
Supply Voltage [1] VCC 3 – 5.5 V
Nominal Supply Voltage VCCN – 5 – V
Supply Current ICC VIOUT open, F̄¯ĀŪ¯L̄¯T̄¯ pin high – 11 14.5 mA
Output Capacitance Load CLOAD VIOUT pin to GND – – 10 nF
Output Resistive Load RLOAD VIOUT pin to GND 10 – – kΩ
Magnetic Coupling from Device Conductor
MCHALL Current flowing from IP+ to IP– pins – 9.5 – G/A
to Hall Element
Internal Filter Resistance [2] RF(INT) – 1.7 – kΩ
Primary Conductor Resistance RPRIMARY TA = 25°C – 1 – mΩ
ANALOG OUTPUT SIGNAL CHARACTERISTICS
Full Range Linearity [3] ELIN IP = ±IP0A –0.75 ±0.25 0.75 %
Symmetry [4] ESYM IP = ±IP0A 99.1 100 100.9 %
Bidirectional Quiescent Output VOUT(QBI) IP = 0 A, TA = 25°C – VCC×0.5 – V
Input-referenced noise density; TA = 25°C, µA
Noise Density IND – 400 –
CL = 4.7 nF /√(Hz)
Input referenced noise at 120 kHz

Noise IN – 170 – mArms
Bandwidth; TA = 25°C,CL = 4.7 nF
TIMING PERFORMANCE CHARACTERISTICS
TA = 25°C, Swing IP from 0 A to IP0A,
VIOUT Signal Rise Time tr no capacitor on FILTER pin, 100 pF from – 3 – μs
VIOUT to GND
TA = 25°C, no capacitor on FILTER pin,
VIOUT Signal Propagation Time tPROP – 1 – μs
100 pF from VIOUT to GND
TA = 25°C, Swing IP from 0 A to IP0A,
VIOUT Signal Response Time tRESPONSE no capacitor on FILTER pin, 100 pF from – 4 – μs
VIOUT to GND
–3 dB, Apply IP such that VIOUT =
VIOUT Large Signal Bandwidth f3dB 1 Vpk-pk, no capacitor on FILTER pin, – 120 – kHz
100 pF from VIOUT to GND
Output reaches 90% of steady-state level,
Power-On Time tPO – 35 – μs
no capacitor on FILTER pin, TA = 25°C
OVERCURRENT CHARACTERISTICS
Setting Voltage for Overcurrent Switch Point [5] VOC VCC × 0.25 – VCC × 0.4 V
Signal Noise at Overcurrent Comparator Input INCOMP – ±1 – A
Switch point in VOC safe operating area;
Overcurrent Fault Switch Point Error [6][7] EOC – ±5 – %
assumes INCOMP = 0 A
Overcurrent F̄¯ĀŪ¯L̄
¯T̄¯ Pin Output Voltage V F̄¯ĀŪ¯L̄¯T̄¯ 1 mA sink current at F̄¯ĀŪ¯L̄¯T̄¯ pin – – 0.4 V
Fault Enable (FAULT_EN Pin) Input Low
VIL – – 0.1 × VCC V
Voltage Threshold
Fault Enable (FAULT_EN Pin) Input High
VIH 0.8 × VCC – – V
Voltage Threshold
Fault Enable (FAULT_EN Pin) Input
RFEI – 1 – MΩ
Resistance
Continued on the next page…
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COMMON OPERATING CHARACTERISTICS (continued): Valid at TA = –40°C to 125°C, VCC = 5 V, unless otherwise specified
OVERCURRENT CHARACTERISTICS (continued)
Set FAULT_EN to low, VOC = 0.25 × VCC ,
COC = 0 F; then run a DC IP exceeding the
corresponding overcurrent threshold; then
Fault Enable (FAULT_EN Pin) Delay [8] tFED – 15 – µs
reset FAULT_EN from low to high and
measure the delay from the rising edge of
FAULT_EN to the falling edge of F̄¯ĀŪ¯L̄¯T̄¯
Set FAULT_EN to low, VOC = 0.25 × VCC ,
COC = 0 F; then run a DC IP exceeding the
Fault Enable (FAULT_EN Pin) Delay corresponding overcurrent threshold; then
tFED(NL) – 150 – ns
(Non-Latching versions) [9] reset FAULT_EN from low to high and
measure the delay from the rising edge of
FAULT_EN to the falling edge of F̄¯ĀŪ¯L̄¯T̄¯
FAULT_EN set to high for a minimum
of 20 µs before the overcurrent event;
switch point set at VOC = 0.25 × VCC ;
Overcurrent Fault Response Time tOC – 1.9 – µs
delay from IP exceeding overcurrent
fault threshold to V F̄¯ĀŪ¯L̄¯T̄¯ < 0.4 V, without
external COC capacitor
FAULT_EN set to high for a minimum
of 20 µs before the undercurrent
event; switch point set at VOC = 0.25
Undercurrent Fault Response Time
tUC × VCC ; delay from IP falling below the – 3 – µs
(Non-Latching versions)
overcurrent fault threshold to
V F̄¯ĀŪ¯L̄¯T̄¯ > 0.8 × VCC , without external COC
capacitor, RPU = 330 kΩ
Time from VFAULTEN < VIL to
Overcurrent Fault Reset Delay tOCR – 500 – ns
V F̄¯ĀŪ¯L̄¯T̄¯ > 0.8 × VCC , RPU = 330 kΩ
Time from VFAULTEN <VIL to rising edge
Overcurrent Fault Reset Hold Time tOCH – 250 – ns
of V F̄¯ĀŪ¯L̄¯T̄¯
Overcurrent Input Pin Resistance ROC TA = 25°C, VOC pin to GND 2 – – MΩ
VOLTAGE REFERENCE CHARACTERISTICS
Voltage Reference Output VZCR TA = 25 °C (Not a highly accurate reference) 0.48 x VCC 0.5 × VCC 0.51 x VCC V
Source current 3 – – mA
Voltage Reference Output Load Current IZCR
Sink current 50 – – µA
Voltage Reference Output Drift ∆VZCR – ±10 – mV
[1] Devices are programmed for maximum accuracy at VCC = 5 V. The device contains ratiometry circuits that accurately alter the 0 A Output Voltage and
Sensitivity level of the device in proportion to the applied VCC level. However, as a result of minor nonlinearities in the ratiometry circuit, additional output
error will result when VCC varies from the VCC level at which the device was programmed. Customers that plan to operate the device at a VCC level other
than the VCC level at which the device was programmed should contact their local Allegro sales representative regarding expected device accuracy levels
under these bias conditions.
[2] R
F(INT) forms an RC circuit via the FILTER pin.
[3] This parameter can drift by as much as 0.8% over the lifetime of this product.
[4] This parameter can drift by as much as 1% over the lifetime of this product.
[5] See page 8 on how to set overcurrent fault switch point.
[6] Switch point can be lower at the expense of switch point accuracy.
[7] This error specification does not include the effect of noise. See the I
NCOMP specification in order to factor in the additional influence of noise on the
fault switch point.
[8] Fault Enable Delay is designed to avoid false tripping of an Overcurrent (OC) fault at power-up. A 15 µs (typical) delay will always be needed, every
time FAULT_EN is raised from low to high, before the device is ready for responding to any overcurrent event.
[9] During power-up, this delay is 15 µs in order to avoid false tripping of an Overcurrent (OC) fault.
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PERFORMANCE CHARACTERISTICS: TA Range K, valid at TA = – 40°C to 125°C, VCC = 5 V, unless otherwise specified
X6BB CHARACTERISTICS
Optimized Accuracy Range [1] IPOA –7.5 – 7.5 A
Linear Sensing Range IR –14 – 14 A
Noise [2] VNOISE(rms) TA = 25°C, Sens = 100 mV/A, Cf = 0, CLOAD = 4.7 nF, RLOAD open – 4.05 – mV
IP = 6.5 A, TA = 25°C – 151 – mV/A
Sensitivity [3] Sens IP = 6.5 A, TA = 25°C to 125°C – 151 – mV/A
IP = 6.5 A, TA = – 40°C to 25°C – 152 – mV/A
IP = 0 A, TA = 25°C – ±10 – mV
Electrical Offset Voltage
Variation Relative to VOE IP = 0 A, TA = 25°C to 125°C – ±11 – mV
VOUT(QBI) [4]
IP = 0 A, TA = – 40°C to 25°C – ±40 – mV
Over full scale of IPOA , IP applied for 5 ms, TA = 25°C to 125°C – ±1.6 – %
Total Output Error [5] ETOT
Over full scale of IPOA , IP applied for 5 ms, TA = – 40°C to 25°C – ±5.6 – %
X10BB CHARACTERISTICS
Optimized Accuracy Range [1] IPOA –10 – 10 A
IP = 10 A, TA = 25°C – 85 – mV/A
Sensitivity [3] Sens IP = 10 A, TA = 25°C to 125°C – 85 – mV/A
IP = 10 A, TA = – 40°C to 25°C – 85 – mV/A
IP = 0 A, TA = 25°C – ±5 – mV
VOUT(QBI) [4]
IP = 0 A, TA = – 40°C to 25°C – ±22 – mV
Over full scale of IPOA , IP applied for 5 ms, TA = – 40°C to 25°C – ±5 – %
X12CB CHARACTERISTICS
Optimized Accuracy Range [1] IPOA –12.5 – 12.5 A
Linear Sensing Range IR –37.5 – 37.5 A
IP = 12.5 A, TA = 25°C – 56 – mV/A
Sensitivity [3] Sens IP = 12.5 A, TA = 25°C to 125°C – 56 – mV/A
IP = 12.5 A, TA = – 40°C to 25°C – 57 – mV/A
IP = 0 A, TA = 25°C – ±4 – mV
VOUT(QBI) [4]
IP = 0 A, TA = – 40°C to 25°C – ±23 – mV
Over full scale of IPOA , IP applied for 5 ms, TA = – 40°C to 25°C – ±3.9 – %
Continued on the next page…
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PERFORMANCE CHARACTERISTICS (continued): TA Range K, valid at TA = – 40°C to 125°C, VCC = 5 V, unless otherwise specified
X25CB CHARACTERISTICS
Optimized Accuracy Range [1] IPOA –25 – 25 A
Noise [2] VNOISE(rms) TA = 25°C, Sens = 28 mV/A, Cf = 0, CLOAD = 4.7 nF, RLOAD open – 1 – mV
IP = 25 A, TA = 25°C – 28 – mV/A
Sensitivity [3] Sens IP = 25 A, TA = 25°C to 125°C – 27.9 – mV/A
IP = 25 A, TA = – 40°C to 25°C – 28.5 – mV/A
IP = 0 A, TA = 25°C – ±3 – mV
VOUT(QBI) [4]
IP = 0 A, TA = – 40°C to 25°C – ±18 – mV
Over full scale of IP OA, IP applied for 5 ms, TA = 25°C to 125°C – ±2.9 – %
Over full scale of IP OA, IP applied for 5 ms, TA = – 40°C to 25°C – ±5.2 – %
[1] Although the device is accurate over the entire linear range, the device is programmed for maximum accuracy over the range defined by IPOA . The
reason for this is that in many applications, such as motor control, the start-up current of the motor is approximately three times higher than the
running current.
[2] V
pk-pk noise (6 sigma noise) is equal to 6 × VNOISE(rms). Lower noise levels than this can be achieved by using Cf for applications requiring narrower
bandwidth. See Characteristic Performance page for graphs of noise versus Cf and bandwidth versus Cf.
[4] This parameter can drift by as much as 13 mV over the lifetime of this product.
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CHARACTERISTIC PERFORMANCE
ACS710 Bandwidth versus External Capacitor Value, CF
Capacitor connected between FILTER pin and GND
1000
100
Bandwidth (kHz)
10
0.1
0.01 0.1 1 10 100 1000
Capacitance (nF)
ACS710 Noise versus External Capacitor Value, CF

Capacitor connected between FILTER pin and GND
ACS710x-25C ACS710x-25C
V CC = 5 V V CC = 3.3 V
1000 900
900 800
RMS Noise (µV)
RMS Noise (µV)
800 700
700 600
600 500
500 400
400 300
0 10 20 30 40 50 0 10 20 30 40 50
Capacitance (nF) Capacitance (nF)
ACS710x-12C ACS710x-12C
V CC = 5 V V CC = 3.3 V
1600 1600
1400 1400
1200 1200
RMS Noise (µV)
RMS Noise (µV)
1000 1000
800 800
600 600
400 400
200 200
0 0
0 10 20 30 40 50 0 10 20 30 40 50
Capacitance (nF) Capacitance (nF)
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CHARACTERISTIC PERFORMANCE DATA

Data taken using the ACS710-6BB
Accuracy Data
Electrical Offset Voltage versus Ambient Temperature Sensitivity versus Ambient Temperature
50 160.0
40 157.5
30
155.0
20
Sens (mV/A)
152.5
VOE (mV)
10
0 150.0
-10 147.5
-20
145.0
-30
-40 142.5
-50 140.0
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
Nonlinearity versus Ambient Temperature Symmetry versus Ambient Temperature

0.4 101.00
0.3 100.75
0.2 100.50
0.1 100.25
ESYM (%)
ELIN (%)
0 100.00
-0.1 99.75
-0.2 99.50
-0.3 99.25
-0.4 99.00
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)
Total Output Error versus Ambient Temperature

6.0
4.5
3.0
1.5
ETOT (%)
0
-1.5
-3.0
-4.5
-6.0
–50 -25 0 25 50 75 100 125 150
TA (°C)
Typical Maximum Limit Mean Typical Minimum Limit
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Data taken using the ACS710-10BB
Accuracy Data
30 88.00
20 87.00
86.00
10
Sens (mV/A)
VOE (mV)
85.00
0
84.00
-10
83.00
-20
82.00
-30 81.00
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)

0.30 100.30
0.20 100.20
0.10 100.10
100.00
0
ESYM (%)
ELIN (%)
99.90
-0.10
99.80
-0.20
99.70
-0.30 99.60
-0.40 99.50
-0.50 99.40
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)

4.00
3.00
2.00
1.00
ETOT (%)
0
-1.00
-2.00
-3.00
-4.00
-5.00
–50 -25 0 25 50 75 100 125 150
TA (°C)
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Data taken using the ACS710-12CB
Accuracy Data
25 58.5
20
58.0
15
Sens (mV/A)
10 57.5
VOE (mV)
5 57.0
0
56.5
-5
-10 56.0
-15
55.5
-20
-25 55.0
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)

0.10 100.1
0.05
0 100.0
-0.05
-0.10 99.9
ESYM (%)
ELIN (%)
-0.15
99.8
-0.20
-0.25 99.7
-0.30
-0.35 99.6
-0.40
-0.45 99.5
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)

6
5
4
3
2
ETOT (%)
1
0
-1
-2
-3
–50 -25 0 25 50 75 100 125 150
TA (°C)
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Data taken using the ACS710-25CB
Accuracy Data
25 29.6
20 29.4
15 29.2
Sens (mV/A)
10 29.0
VOE (mV)
5 28.8
0 28.6
-5 28.4
-10 28.2
-15 28.0
-20 27.8
-25 27.6
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)

0.10 100.1
0.05
100.0
0
-0.05 99.9
ESYM (%)
ELIN (%)
-0.10
99.8
-0.15
-0.20 99.7
-0.25
99.6
-0.30
-0.35 99.5
–50 -25 0 25 50 75 100 125 150 –50 -25 0 25 50 75 100 125 150
TA (°C) TA (°C)

6
5
4
3
2
ETOT (%)
1
0
-1
-2
-3
–50 -25 0 25 50 75 100 125 150
TA (°C)
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SETTING OVERCURRENT FAULT SWITCH POINT
Setting 12CB and 25CB Versions

The VOC needed for setting the overcurrent fault switch point can | Ioc | is the overcurrent fault switch point for a bidirectional (AC)
be calculated as follows: current, which means a bidirectional sensor will have two sym-
metrical overcurrent fault switch points, +IOC and –IOC .
VOC = Sens × | IOC | ,
See the following graph for IOC and VOC ranges.
where VOC is in mV, Sens in mV/A, and IOC (overcurrent fault
switch point) in A.
IOC versus VOC

(12CB and 25CB Versions)
IOC
0.4 VCC / Sens

Not Valid Range
Valid Range
0.25 VCC / Sens
0
0. 25 VCC VOC
0. 4 VCC
– 0.25 VCC / Sens
– 0.4 VCC / Sens
Example: For ACS710KLATR-25CB-T, if required overcurrent fault switch point is 50 A, and VCC = 5 V, then the
required VOC can be calculated as follows:
VOC = Sens × IOC = 28 × 50 = 1400 (mV)
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Setting 6BB and 10BB Versions

The VOC needed for setting the overcurrent fault switch point can | Ioc | is the overcurrent fault switch point for a bidirectional (AC)
be calculated as follows: current, which means a bidirectional sensor will have two sym-
metrical overcurrent fault switch points, +IOC and –IOC .
VOC = 1.17 × Sens × | IOC | ,
See the following graph for IOC and VOC ranges.
where VOC is in mV, Sens in mV/A, and IOC (overcurrent fault
switch point) in A.
IOC versus VOC

(6BB and 10BB Versions)
IOC
0.4 VCC / (1.17 × Sens)

Not Valid Range
Valid Range
0.25 VCC / (1.17 × Sens)
0
0.25 VCC VOC
0.4 VCC
– 0.25 VCC / (1.17 × Sens)
– 0.4 VCC / (1.17 × Sens)
Example: For ACS710KLATR-6BB-T, if required overcurrent fault switch point is 10 A, and VCC = 5 V, then the
required VOC can be calculated as follows:
VOC = 1.17 × Sens × IOC = 1.17 × 151 × 10 = 1767 (mV)
16
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FUNCTIONAL DESCRIPTION (Latching Versions)

Overcurrent Fault Operation internal NMOS pull-down turns off and an internal PMOS pull-
The primary concern with high-speed fault detection is that noise up turns on (see [7] if the OC fault condition still exists).
may cause false tripping. Various applications have or need to 4. The slope, and thus the delay to latch the fault is controlled by
be able to ignore certain faults that are due to switching noise or the capacitor, COC, placed on the F̄¯Ā¯Ū
¯L̄¯T̄¯ pin to ground. Dur-
other parasitic phenomena, which are application dependant. The ing this portion of the fault (when the F̄¯Ā¯Ū¯L̄¯T̄¯ pin is between
problem with simply trying to filter out this noise in the main VCC and 2 V), there is a 3 mA constant current sink, which
signal path is that in high-speed applications, with asymmetric discharges COC. The length of the fault delay, t, is equal to:
noise, the act of filtering introduces an error into the measure-
ment. To get around this issue, and allow the user to prevent the COC ( VCC – 2 V )
t= (1)
fault signal from being latched by noise, a circuit was designed to 3 mA
slew the F̄¯Ā¯Ū¯L̄
¯T̄¯ pin voltage based on the value of the capacitor where VCC is the device power supply voltage in volts, t is in
from that pin to ground. Once the voltage on the pin falls below seconds and COC is in Farads. This formula is valid for RPU
2 V, as established by an internal reference, the fault output is equal to or greater than 330 kΩ. For lower-value resistors,
latched and pulled to ground quickly with an internal N-channel the current flowing through the RPU resistor during a fault
MOSFET. event, IPU , will be larger. Therefore, the current discharging
the capacitor would be 3 mA – IPU and equation 1 may not be
Fault Walkthrough
The following walkthrough references various sections and valid.
attributes in the figure below. This figure shows different 5. The F̄¯Ā
¯Ū
¯L̄¯T̄¯ pin did not reach the 2 V latch point before the
fault set/reset scenarios and how they relate to the voltages on OC fault condition cleared. Because of this, the fixed 3 mA
the F̄¯Ā¯Ū¯L̄¯T̄¯ pin, FAULT_EN pin, and the internal Overcurrent current sink turns off, and the internal PMOS pull-up turns on
(OC) Fault node, which is invisible to the customer. to recharge COC through the F̄¯Ā¯Ū ¯L̄¯T̄¯ pin.
1. Because the device is enabled (FAULT_EN is high for a 6. This curve shows VCC charging external capacitor COC
minimum period of time, the Fault Enable Delay, tFED , 15 µs through the internal PMOS pull-up. The slope is determined
typical) and there is an OC fault condition, the device F̄¯Ā¯Ū¯L̄¯T̄¯ by COC.
pin starts discharging. 7. When the FAULT_EN pin is brought low, if the fault condition
2. When the F̄¯Ā¯Ū¯L̄¯T̄¯ pin voltage reaches approximately 2 V, the ¯Ā¯Ū¯L̄
still exists, the latched F̄ ¯T̄¯ pin will be pulled low by the
fault is latched, and an internal NMOS device pulls the F̄¯Ā¯Ū¯L̄¯T̄¯ internal 3mA current source. When fault condition is removed
pin voltage to approximately 0 V. The rate at which the F̄¯Ā ¯Ū¯L̄¯T̄¯ then the Fault pin charges as shown in step 6.
pin slews downward (see [4] in the figure) is dependent on the 8. At this point there is a fault condition, and the part is enabled
external capacitor, COC, on the F̄¯Ā¯Ū¯L̄¯T̄¯ pin. before the F̄¯Ā¯Ū
¯L̄¯T̄¯ pin can charge to VCC. This shortens the
3. When the FAULT_EN pin is brought low, the F̄¯Ā¯Ū¯L̄¯T̄¯ user-set delay, so the fault is latched earlier. The new delay
pin starts resetting if no OC fault condition exists, and if time can be calculated by equation 1, after substituting the
FAULT_EN is low for a time period greater than tOCH . The voltage seen on the F̄¯Ā¯Ū ¯L̄¯T̄¯ pin for VCC.
1 1 1
VCC
4 6
tFED
4 4 8
FAULT
(Output) 6 5 4
2 2 6 2
2V
7
3
0V
Time
FAULT_EN
(Input)
OC Fault
Condition
(Active High)
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FUNCTIONAL DESCRIPTION (Non-Latching Versions)

Overcurrent Fault Operation than tOCH . The internal NMOS pull-down turns off and an
The primary concern with high-speed fault detection is that noise internal PMOS pull-up turns on.
may cause false tripping. Various applications have or need to 4. The slope, and thus the delay to pull the fault low is controlled
be able to ignore certain faults that are due to switching noise or by the capacitor, COC, placed on the F̄¯Ā¯Ū
¯L̄¯T̄¯ pin to ground.
other parasitic phenomena, which are application dependant. The During this portion of the fault (when the F̄ ¯Ā¯Ū¯L̄¯T̄
¯ pin is
problem with simply trying to filter out this noise in the main sig- between VCC and 2 V), there is a 3 mA constant current sink,
nal path is that in high-speed applications, with asymmetric noise,
which discharges COC. The length of the fault delay, t, is equal
the act of filtering introduces an error into the measurement.
to:
To get around this issue, and allow the user to prevent the fault
signal from going low due to noise, a circuit was designed to slew COC ( VCC – 2 V )
t= (2)
the F̄¯Ā¯Ū¯L̄¯T̄¯ pin voltage based on the value of the capacitor from 3 mA
that pin to ground. Once the voltage on the pin falls below 2 V, as where VCC is the device power supply voltage in volts, t is in
established by an internal reference, the fault output is pulled to seconds and COC is in Farads. This formula is valid for RPU
ground quickly with an internal N-channel MOSFET. equal to or greater than 330 kΩ. For lower-value resistors,
Fault Walkthrough the current flowing through the RPU resistor during a fault
The following walkthrough references various sections and event, IPU , will be larger. Therefore, the current discharging
attributes in the figure below. This figure shows different the capacitor would be 3 mA – IPU and equation 1 may not be
fault set/reset scenarios and how they relate to the voltages on valid.
¯Ā¯Ū¯L̄¯T̄¯ pin, FAULT_EN pin, and the internal Overcurrent
the F̄ 5. The F̄¯Ā
¯Ū
¯L̄¯T̄¯ pin did not reach the 2 V latch point before the
(OC) Fault node, which is invisible to the customer. OC fault condition cleared. Because of this, the fixed 3 mA
1. Because the device is enabled (FAULT_EN is high for a mini- current sink turns off, and the internal PMOS pull-up turns on
mum period of time, the Fault Enable Delay, tFED , and there is to recharge COC through the F̄¯Ā¯Ū ¯L̄¯T̄¯ pin.
an OC fault condition, the device F̄¯Ā¯Ū¯L̄ ¯T̄¯ pin starts discharging. 6. This curve shows VCC charging external capacitor COC
2. When the F̄¯Ā¯Ū¯L̄¯T̄¯ pin voltage reaches approximately 2 V, an through the internal PMOS pull-up. The slope is determined
internal NMOS device pulls the F̄ ¯Ā¯Ū¯L̄¯T̄¯ pin voltage to approx- by COC.
imately 0 V. The rate at which the F̄¯Ā¯Ū¯L̄¯T̄ ¯ pin slews downward 7. At this point there is a fault condition, and the part is enabled
(see [4] in the figure) is dependent on the external capacitor, before the F̄¯Ā¯Ū
¯L̄¯T̄¯ pin can charge to VCC. This shortens the
COC, on the F̄¯Ā¯Ū¯L̄¯T̄¯ pin. user-set delay, so the fault gets pulled low earlier. The new
3. When the FAULT_EN pin is brought low, the F̄¯Ā¯Ū¯L̄¯T̄¯ pin delay time can be calculated by equation 1, after substituting
starts resetting if FAULT_EN is low for a time period greater the voltage seen on the F̄¯Ā ¯Ū¯L̄¯T̄
¯ pin for VCC.
1 1 1
VCC
4 6
tFED
4 4 7
FAULT
(Output) 6 5 4
2 2 6 2
2V
3
0V
Time
FAULT_EN
(Input)
OC Fault
Condition
(Active High)
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955 Perimeter Road
Chopper Stabilization Technique

Chopper stabilization is an innovative circuit technique that is IC is desensitized to the effects of temperature and mechanical
used to minimize the offset voltage of a Hall element and an stress. This technique produces devices that have an extremely
associated on-chip amplifier. This chopper stabilization technique stable electrical offset voltage, are immune to thermal stress, and
nearly eliminates Hall IC output drift induced by temperature or have precise recoverability after temperature cycling.
package stress effects. This offset reduction technique is based on
This technique is made possible through the use of a BiCMOS
a signal modulation-demodulation process. Modulation is used
process that allows the use of low-offset and low-noise amplifiers
to separate the undesired DC offset signal from the magnetically
in combination with high-density logic integration and sample-
induced signal in the frequency domain. Then, using a low-pass
and-hold circuits.
filter, the modulated DC offset is suppressed while the magneti-
cally induced signal passes through the filter. As a result of this
chopper stabilization approach, the output voltage from the Hall
Regulator
Clock/Logic
Low-Pass
Hall Element
Filter
Sample and
Hold
Amp
Concept of Chopper Stabilization Technique
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955 Perimeter Road
DEFINITIONS OF ACCURACY CHARACTERISTICS

Sensitivity (Sens). The change in sensor output in response to a Accuracy is divided into four areas:
1 A change through the primary conductor. The sensitivity is the
• 0 A at 25°C. Accuracy of sensing zero current flow at 25°C,
product of the magnetic circuit sensitivity (G / A) and the linear
without the effects of temperature.
IC amplifier gain (mV/G). The linear IC amplifier gain is pro-
grammed at the factory to optimize the sensitivity (mV/A) for the • 0 A over Δ temperature. Accuracy of sensing zero current
full-scale current of the device. flow including temperature effects.
Noise (VNOISE). The product of the linear IC amplifier gain • Full-scale current at 25°C. Accuracy of sensing the full-scale
(mV/G) and the noise floor for the Allegro Hall-effect linear current at 25°C, without the effects of temperature.
IC. The noise floor is derived from the thermal and shot noise • Full-scale current over Δ temperature. Accuracy of sensing full-
observed in Hall elements. Dividing the noise (mV) by the sensi- scale current flow including temperature effects.
tivity (mV/A) provides the smallest current that the device is able
Ratiometry. The ratiometric feature means that its 0 A output,
to resolve.
VIOUT(Q), (nominally equal to VCC/2) and sensitivity, Sens, are
Linearity (ELIN). The degree to which the voltage output from proportional to its supply voltage, VCC . The following formula is
the sensor varies in direct proportion to the primary current
used to derive the ratiometric change in 0 A output voltage,
through its full-scale amplitude. Nonlinearity in the output can be
attributed to the saturation of the flux concentrator approaching ΔVIOUT(Q)RAT (%).
the full-scale current. The following equation is used to derive the

VIOUT(Q)VCC / VIOUT(Q)5V

linearity: 100
VCC / 5 V
{ [
100 1–
VIOUT_full-scale amperes – VIOUT(Q)
2 (VIOUT_1/2 full-scale amperes – VIOUT(Q) ) [{ The ratiometric change in sensitivity, ΔSensRAT (%), is defined as:
SensVCC / Sens5V
 
where VIOUT_full-scale amperes = the output voltage (V) when the
100
sensed current approximates full-scale ±IP . VCC / 5 V
Symmetry (ESYM). The degree to which the absolute voltage
output from the sensor varies in proportion to either a positive Output Voltage versus Sensed Current
Accuracy at 0 A and at Full-Scale Current
or negative full-scale primary current. The following formula is
used to derive symmetry: Increasing VIOUT(V)
Accuracy
VIOUT_+ full-scale amperes – VIOUT(Q)
 VIOUT(Q) – VIOUT_–full-scale amperes 

Over ∆Temp erature
100
Accuracy
25°C Only
Quiescent output voltage (VIOUT(Q)). The output of the sensor

Average
when the primary current is zero. For a unipolar supply voltage, VIOUT
it nominally remains at 0.5 × VCC. For example, in the case of a Accuracy
bidirectional output device, VCC = 5 V translates into VIOUT(Q) = Over ∆Temp erature
2.5 V. Variation in VIOUT(Q) can be attributed to the resolution of Accuracy

the Allegro linear IC quiescent voltage trim and thermal drift. IP(min)
25°C Only
Electrical offset voltage (VOE). The deviation of the device out- –IP (A) +IP (A)
put from its ideal quiescent voltage due to nonmagnetic causes. Full Scale
IP(max)
To convert this voltage to amperes, divide by the device sensitiv-
ity, Sens. 0A
Accuracy (ETOT). The accuracy represents the maximum devia-

tion of the actual output from its ideal value. This is also known
as the total ouput error. The accuracy is illustrated graphically in Accuracy
25°C Only
the output voltage versus current chart at right. Note that error is Accuracy
directly measured during final test at Allegro. Over ∆Temp erature
Decreasing VIOUT(V)
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955 Perimeter Road
DEFINITIONS OF DYNAMIC RESPONSE CHARACTERISTICS
I (%) Primary Current
Propagation delay (tPROP). The time required for the sensor

90
output to reflect a change in the primary current signal. Propaga-
tion delay is attributed to inductive loading within the linear IC
package, as well as in the inductive loop formed by the primary Transducer Output
conductor geometry. Propagation delay can be considered as a
fixed-time offset and may be compensated. 0
t
Propagation Time, tPROP
90
Response time (tRESPONSE). The time interval between a) when
the primary current signal reaches 90% of its final value, and b)
when the sensor reaches 90% of its output corresponding to the Transducer Output
applied current.
0
t
Response Time, tRESPONSE

Rise time (tr). The time interval between a) when the sensor
90
reaches 10% of its full-scale value, and b) when it reaches 90%
of its full-scale value. The rise time to a step response is used to
derive the bandwidth of the current sensor, in which ƒ(–3 dB) =
Transducer Output
0.35 / tr. Both tr and tRESPONSE are detrimentally affected by eddy
10
current losses observed in the conductive IC ground plane. 0
t
Rise Time, tr
21
955 Perimeter Road
Package LA, 16-Pin SOICW
10.30 ±0.20 8° 1.27

0° 16 0.65
16
0.33 2.25
0.20
7.50 ±0.10 10.30 ±0.33 9.50
1.40 REF
1 2
1.27
0.40 1 2
Branded Face 0.25 BSC

SEATING PLANE C PCB Layout Reference View
16X C GAUGE PLANE
SEATING
0.10 C PLANE
1.27 BSC 2.65 MAX
0.51
0.31 0.30
0.10 NNNNNNNNNNN
TTT-TTT
LLLLLLLLL
For Reference Only; not for tooling use (reference MS-013AA)

Dimensions in millimeters 1
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area B Standard Branding Reference View
B Branding scale and appearance at supplier discretion N = Device part number
C
T = Temperature range, package - amperage
Reference land pattern layout (reference IPC7351
L = Lot number
SOIC127P600X175-8M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances
22
955 Perimeter Road
REVISION HISTORY
Number Date Description
9 June 17, 2013 Add 10BB variant
10 August 19, 2015 Added certificate number under UL stamp on page 1; updated Isolation Characteristics table.
11 June 5, 2017 Updated product status
Added Dielectric Surge Strength Test Voltage to Isolation Characteristics table (p. 3), and Noise and
12 August 31, 2017
Noise Density characteristics to Common Operating Characteristics table (p. 6).
13 November 13, 2017 Corrected typo in Dielectric Surge Strength Test Voltage notes of Isolation Characteristics table (p. 3)
14 December 6, 2018 Updated UL certificate number and minor editorial updates
15 February 1, 2019 Updated product status to Pre-End-of-Life
16 January 30, 2020 Updated product status and minor editorial updates
The products described herein are protected by U.S. patents: 7,166,807; 7,425,821; 7,573,393; and 7,598,601.
Copyright 2020, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:

23
955 Perimeter Road

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ACS710

120 kHz Bandwidth, High-Voltage Isolation

FEATURES AND BENEFITS DESCRIPTION

Not to scale Continued on the next page…

Typical Application Circuit

ACS710-DS, Rev. 16 January 30, 2020

[1] Contact Allegro for packing options.

ABSOLUTE MAXIMUM RATINGS

Functional Block Diagram

Pinout Diagram Terminal List Table, Latching Version

Functional Block Diagram

FAULT_EN FAULT Reset

Pinout Diagram Terminal List Table, Non-Latching Version

Input referenced noise at 120 kHz

Continued on the next page…

Continued on the next page…

ACS710 Noise versus External Capacitor Value, CF

RMS Noise (µV)

Capacitance (nF) Capacitance (nF)

RMS Noise (µV)

Capacitance (nF) Capacitance (nF)

CHARACTERISTIC PERFORMANCE DATA

Nonlinearity versus Ambient Temperature Symmetry versus Ambient Temperature

Total Output Error versus Ambient Temperature

Typical Maximum Limit Mean Typical Minimum Limit

CHARACTERISTIC PERFORMANCE DATA

Nonlinearity versus Ambient Temperature Symmetry versus Ambient Temperature

Total Output Error versus Ambient Temperature

Typical Maximum Limit Mean Typical Minimum Limit

CHARACTERISTIC PERFORMANCE DATA

Nonlinearity versus Ambient Temperature Symmetry versus Ambient Temperature

Total Output Error versus Ambient Temperature

Typical Maximum Limit Mean Typical Minimum Limit

CHARACTERISTIC PERFORMANCE DATA

Nonlinearity versus Ambient Temperature Symmetry versus Ambient Temperature

Total Output Error versus Ambient Temperature

Typical Maximum Limit Mean Typical Minimum Limit

SETTING OVERCURRENT FAULT SWITCH POINT

Setting 12CB and 25CB Versions

IOC versus VOC

0.4 VCC / Sens

0.25 VCC / Sens

– 0.4 VCC / Sens

VOC = Sens × IOC = 28 × 50 = 1400 (mV)

Setting 6BB and 10BB Versions

IOC versus VOC

0.4 VCC / (1.17 × Sens)

0.25 VCC / (1.17 × Sens)

– 0.4 VCC / (1.17 × Sens)

VOC = 1.17 × Sens × IOC = 1.17 × 151 × 10 = 1767 (mV)

FUNCTIONAL DESCRIPTION (Latching Versions)

FUNCTIONAL DESCRIPTION (Non-Latching Versions)

Chopper Stabilization Technique

Concept of Chopper Stabilization Technique

DEFINITIONS OF ACCURACY CHARACTERISTICS

 VIOUT(Q) – VIOUT_–full-scale amperes 

Quiescent output voltage (VIOUT(Q)). The output of the sensor

it nominally remains at 0.5 × VCC. For example, in the case of a Accuracy

2.5 V. Variation in VIOUT(Q) can be attributed to the resolution of Accuracy

Accuracy (ETOT). The accuracy represents the maximum devia-