A C ircu it for All Seasons

Behzad Razavi

The Delay-Locked Loop

D
Delay-locked loops (DLLs) can be
considered as feedback circuits that
phase lock an output to an input
without the use of an oscillator. In
some applications, DLLs are neces-
to adjust the delay and force DT
toward zero. This conjecture leads
us to the arrangement depicted in
Fig u r e 2(c). He r e , a
phase detector mea-
of the phase/frequency detector (PFD),
charge pump (CP), and capacitor pro-
vides an infinite gain, thus driving the
skew toward zero. The
variable-delay stage is
sary or preferable over phase-locked sures the skew and The origins of realized as a voltage-
loops (PLLs), with their advantages adjusts t he delay of DLLs can be controlled delay line
including lower sensitivity to supply B 2 t o r e d u c e DT. A s traced to a paper (VCDL). Figure 2(e)
noise and lower phase noise. This with PLLs, the low-pass published shows an example of
article deals with fundamental DLL filter attenuates the in 1961. VCDL design emp­
design concepts. high-frequency compo- loying varactors for de-
The origins of DLLs can be traced nents generated by the lay control. While the
to a paper published in 1961 [1]. The PD. This circuit exemplifies a simple DLL does not require frequency
authors present the topology shown delay-locked loop. detection, the PFD provides a con-
in Figure 1 as a “delay-lock discrimi- The residual phase error in Fig- venient interface with the CP. As ex-
nator” operating on random signals. ure 2(c) depends on the loop gain, i.e., the plained next, no resistor is necessary
The feedback loop consists of a con- gain of the PD, K PD, and the gain of the in series with C 1 . This DLL archi-
trolled delay line, a multiplier acting variable-delay stage. The latter is de- tecture is commonly used in high-
as a phase detector (PD), and a low- fined as K DL = 2z/2Vcont, where z is speed systems.
pass filter. The use of DLLs in mod- the stage’s delay in ra­­d i­­­a ns. Rath- The DLL of Figure 2(d) is of first
ern CMOS design evidently began er than attempt to maximize order, facing no stability issues. More-
with the work by Bazes in 1985 [2] K PD K DL, we can add an integrator to over, it benefits from the lower phase
and Johnson and Hudson in 1988 [3]. the loop. Drawing upon our knowl- noise and supply sensitivity of delay
e d g e o f PLLs, we thus construct lines compared to oscillators.
Basic Idea the architecture shown in Figure 2(d), In contrast to PLLs, delay-locked
Suppose, as shown in Figure 2(a), an where the cascade consisting loops do not generate a frequency;
input clock travels on a long inter-
connect, experiencing a significant
skew, DT. How do we align CK out with
Received Waveform Multiplier
CK in ? Since the clock is periodic, As [t + T (t )] + n (t )
we surmise that an additional delay x (t ) Low-Pass Delay Estimate
can be introduced to make the total Filter F (p )
"

aT (t )
delay equal to one clock cycle [Fig-
ure 2(b)]. To set the delay properly, ks′ [t + T (t )]
we can view DT as an error that must
be suppressed by means of negative Delay Control
feedback. That is, if the phase of
CK out is compared to that of CK in, Reference Controlled Delay Line
the resulting er ror ca n be used Differentiate Gain gd = 1/α sec/Volt
ks (t )
ks′ (t )
Digital Object Identifier 10.1109/MSSC.2018.2844615
Date of publication: 13 August 2018 Figure 1: An early DLL reported in [1].

IEEE SOLID-STATE CIRCUITS MAGAZINE su m m e r 2 0 18 9

 TCK
CKin

Long Interconnect CKout

CKin B1 B2 CKout

t
∆T
(a)
Variable−Delay
Stage CKin

CKin B1 B2 CKout
CKout
Vcont

TCK t
(b)
VCDL

CKin B1 B2 CKout CKin B1 B2 CKout

R1 Vcont Vcont
PD PFD CP
C1 C1

(c) (d)

CKin CKout

Vcont
(e)

Figure 2: (a) An interconnect with skew, (b) the correction of skew by a delay stage, (c) a simple feedback system for controlling the delay
line, (d) a basic DLL, and (e) a VCDL implementation example.

rather, they simply delay the input. Loop Dynamics time constant, allowing the approxi-
As such, DLLs are less versatile than We wish to analyze the dynamic be­­ mation exp (- TCK s) . 1.
PLLs. For example, in practice, a DLL havior of the DLL shown in Figure 3(a). How about the path from Vcont
would not be able to generate a 5-GHz In the locked state, the phase differ- to CK out ? If we apply a step at Vcont
clock from a 20-MHz reference. ence between CK in and CK out is con- in Figure 2(e), how long does it take
Another drawback of DLLs is stant and, in principle, equal to zero. to affect the output phase? From the
that they allow the input duty cycle Thus, the VCDL provides a delay of waveforms shown in Figure 3(c), we
error to propagate to the output. one clock period, TCK . recognize that this path too has a
In fact, the delay line may further Before delving into the overall delay of at most one TCK . Based on
increase this error. Thus, the VCDL loop dynamics, let us understand these observations, we can construct
is typically preceded or followed those of the VCDL itself. The circuit an approximate, static model for the
by a duty cycle correction stage. A has a clock input and a control input. VCDL; as shown in Figure 3(d), it sim-
third drawback of DLLs is that they What happens if CK in in Figure 2(e) ply adds a phase equal to K DL Vcont
operate the PFD a nd the CP at incurs a phase step? This step propa- to the input phase. (The one-cycle
high speeds. gates through the chain and emerges delay is neglected here.)
The dynamic behavior of DLLs at the output TCK seconds later [Fig- It is instructive to first examine
determines how they respond to such ure 3(b)]. That is, the transfer func- the overall DLL’s response qualita-
effects as input phase noise, and sup- tion associated with this path can be tively. If the phase of CK in in Fig-
ply noise. We therefore study this expressed as exp (-TCK s) . In practice, ure 3(a) fluctuates slowly, the DLL
behavior in the next section. TCK is much less than the overall DLL maintains a high loop gain, keeping

10 su m m e r 2 0 18 IEEE SOLID-STATE CIRCUITS MAGAZINE

 TCK

Input Phase
CKin VCDL CKout Step
φ out
φ in CKin
Vcont
PFD CP
CKout
C1

t
(a) (b)

CKin

CKout φ in VCDL φ out = KDLVcont + φ in

Vcont
Vcont
t
(c) (d)

Figure 3: (a) A DLL with a VCDL, (b) the propagation of input phase step to output, (c) the propagation of step on Vcont to output, and
(d) a linear model of a VCDL.

CK out aligned with CK in . That is, the We should remark that some DLLs Effect of Supply Noise
closed-loop transfer function has apply an independent reference The principal effect of supply noise,
a unity magnitude for slow phase clock to the PFD and do not follow VDD (t), in DLLs is to modulate the
variations. Now suppose CK in expe- these dynamics [4]. delay of the VCDL. How does the DLL
riences very fast phase changes. The aforementioned study reveals of Figure 3(a) respond to VDD (t) ? If
Then, the DLL has little loop gain, two points: 1) DLLs do not generally the noise varies slowly, the loop has
Vcont d o e s n ot c h a n ge , a n d CK in face stability issues and can oper- enough “strength” to keep z out close to
simply propagates to CK out . In this ate with a wide range of values for z in, i.e., Vcont opposes VDD (t) and z out
case, too, the closed-loop response I p and C 1, and 2) the lack of filtering
is around unity because the input ability precludes the use of the fore-
phase changes appear at the output going DLLs in applications where the
VDD
with only a delay of TCK seconds. We input jitter must be removed. The
thus conclude that DLLs exhibit an latter issue is resolved by a different
KVDD
all-pass response, a point of contrast DLL architecture [4].
to the low-pass behavior of PLLs. φ out
φ in = 0
The all-pass nature of DLLs can also
be confirmed mathematically. For the
KDL
DLL of Figure 3(a), we draw the phase +
Ip
model as shown in Figure 4(a), noting that φ in φ out
– c1s Vcont
Vcont is given by (z in - z out) [I p / (C 1 s)],
where I p denotes the charge pump cur- KDL
+ (a)
rent, and hence Ip
φ out
c1s Vcont
Ip – VDD
z in + (z in - z out) K DL = z out .(1)
C1 s (a) KVDD
That is, φ out
φ in
K DL I p ω
- (z in - z out) = (z in - z out) , (2) IpKDL
C1 s
ω c1
(b) (b)
which implies z in = z out . In prac-
tice, the response exhibits a small Figure 4: (a) A linear model of DLL and Figure 5: (a) The supply noise in a DLL and
amount of peaking [Figure 4(b)] [4]. (b) the DLL phase response. (b) the DLL phase response.

IEEE SOLID-STATE CIRCUITS MAGAZINE su m m e r 2 0 18 11

is not affected. For high-frequency z out K VDD C 1 s where f0 is the oscillation frequency
(s) = . (4)
noise, on the other hand, the loop gain VDD C 1 s + I p K DL (Figure 6). We conclude that the ring
drops, and z out is directly modu- produces much higher phase noise.
lated by VDD . Plotted in Figure 5(b), the response One interpretation of this result is
Let us define for the VCDL a gain begins to flatten out beyond the pole that, in a ring, an edge continues
from VDD to z out as K VDD = 2z out /2VDD. frequency, ~ p = I p K DL /C 1 . We must to accumulate phase noise as it cir-
Shown in Figure 5(a) is the DLL model therefore choose a high value for ~ p culates, whereas, in a delay line, an
with supply noise and z in = 0. Be­­g in­­ so as to maximize the supply rejection. edge experiences the phase noise of
ning from the output, we can write the delay stages only once before it
Vcont as - z out [I p / (C 1 s)] and hence Effect of Phase Noise reaches the output [6].
DLLs are generally considered to gen- S econd, we model t he VCDL
Ip erate much less phase noise than phase noise as shown in Figure 7(a)
- z out K + VDD K VDD = z out .(3)
C 1 s DL PLLs, but the comparison must be and write
done carefully. We begin with the
Ip
It follows that input phase noise. As exemplified by - z out K + z n, DL = z out, (6)
C 1 s DL
the transfer function plotted in Fig-
ure 4(b), this noise experiences no obtaining
attenuation and simply propagates to
the output. z out C1 s
Sφ,ring (s) = .(7)
The case of the VCDL phase noise z n, DL C 1 s + I p K DL
Phase−Locked
is more interesting. We make two ob-
Oscillator
servations. First, as shown in [5], the Similar to the effect of supply
phase noise of a delay line, S z,DL, and noise, this result indicates a first-
Sφ,DL
that of a ring oscillator using such a order high-pass behavior [Figure 7(b)].
line, S z,ring, are related as follows: As expected, the loop rejects slow
f0 f0 + ∆f f phase fluctuations caused by the
VCDL. In general, the dominant source
Figure 6: The comparison of ring oscillator f0 2 of phase noise in VCDLs is the sup­­p­
S z, ring (f ) = S z, DL c m , (5)
phase noise and delay line phase noise. rDf ­ly noise.

Generation of Multiple Phases

φ n,DL In addition to the deskewing func-
tion illustrated in Figure 2(d), DLLs
φ out also find application in systems re­­
φ out φ n,DL quiring multiple clock phases. For
φ in = 0
example, some clock and data recov-
KDL 1.0 ery circuits demand 32 or 64 equal­
+ ­ly spaced clock phases, a difficult
Ip
situation for ring oscillators as their
– c1s Vcont
IpKDL ω operation frequency is inversely pro­­
c1 portional to the number of stages
(a) (b) that they employ.
Figure 8 depicts a DLL that deliv-
Figure 7: (a) A DLL model including delay line phase noise and (b) the DLL response. ers multiple clock phases. Incorpo-
rating N nominally identical delay
stages, the VCDL provides N phases
TD with a minimum spacing equal to the
V0 V1 V2 VN delay of one stage, TD . The key point
here is that TD = TCK /N because the
CKin V1 loop locks such that CK out and CK in
CKout
φ in φ out have a phase difference of TCK . In
V0 = VN other words, by virtue of the feed-
Vcont
PFD CP back around the loop, TD remains
C1 well defined and relatively precise
VN –1
even with process, voltage, and tem-
perature (PVT) variations. By compar-
Figure 8: A DLL generating multiple phases. ison, a “free-running” delay line can

12 s u m m e r 2 0 18 IEEE SOLID-STATE CIRCUITS MAGAZINE

 VCDL
InvN–1 InvN
V0
CKin CKout CKin CKout
VN–2 VN–1 VN V1 V2 V3 V4
Inva
Va
Vcont Vcont
PFD CP PFD CP
C1 C1
Vb
Invb
(a) (b)

Figure 9: (a) The DLL of Figure 8 with output inverters added and (b) uniform fanouts at all VCDL taps.

experience a nearly twofold change in it can do so if the phase difference this amount, thereby avoiding false
its delay as a function of PVT. between these two signals reaches lock. The filter preceding Vcoarse sup-
The multiphase DLL shown in Fig- 2TCK rather than TCK . As a result, presses the ripple and noise present
ure 8 faces several issues. First, due the phase spacings will be equal to in Vcont1 . This architecture approxi-
to unequal loading, the phase spac- 2TCK /N. mately doubles the area and power
ings at the boundaries of the VCDL Avoiding false lock generally consumption. Another method is
can be different from those in the re­­quires substantial added complex- described next.
middle. To understand this point, ity, especially if the DLL must oper-
consider the situation illustrated in ate across a wide frequency range.
Figure 9(a), where inverters Inv N - 1 Depicted in Figure 11 is a solution
and Inv N see different fanouts; the employ ing a PLL. A replica of the Start−Up Condition
former drives two inverters but the VCDL is configured as a ring oscil- 2TCK + ε
latter, an inverter and a PFD. As a lator and phase locked to the main VN
result, the phase difference between input, thus g ua ra nteeing that
VN - 2 and VN - 1 is not the same as that the delay from A to B is equal to After Lock
bet ween VN - 1 and VN . This issue TCK and hence Vcont1 reaches the 2TCK
is overcome as shown in Figure 9(b), desired value. Now, this voltage V0
with two inverters inserted at the serves as the coarse control for the
PF D inputs. A ssum ing a ll of t he main VCDL, allowing the DLL to pro- 2TCK
VN
inverters are identical, we observe vide only a fine adjustment through
that 1) the fanout at V4 is equal to Vfine . For example, if the two VCDLs t
that at V1, V2, and V3, and 2) the loop have a delay mismatch of 10%, then
drives the phase difference between Vfine must var y the delay by only Figure 10: The problem of false lock.
Va and Vb to zero, thus aligning V0
and V4 as well. One assumption here
is that the waveform arriving at V0
has approximately the same rise
and fall times as that at V4; other- CKin VCDL CKout
wise, the delays through Inv a and Vfine Vcoarse
Inv b are slightly different.
PFD CP
Another issue in the DLL of Fig- Replica VCDL
C1
ure 8 is the problem of “false lock.” A B
Assume the circuit is designed to
provide a total delay of TCK at the
PFD CP
typical-typical (TT), 27 c C corner. Vcont1
Now, suppose the DLL operates in
R1
the slow-slow (SS), high-temperature PLL
C1
corner, and, upon startup, the total
VCDL delay is slightly greater than
2TCK (Figure 10). Then, the DLL sim-
ply attempts to align V0 and VN , and Figure 11: The addition of a PLL to a DLL to avoid false lock.

IEEE SOLID-STATE CIRCUITS MAGAZINE su m m e r 2 0 18 13

 VX VY V1
V2
Va Vb Vc Vd Va
V3
V4
Vb
CKin CKout
V0 V1 V2 V3 V4 V5 V6 V7 V8 VX

(a) (b) t

Figure 12: (a) An edge-combining circuit for frequency multiplication and (b) its waveforms.

Recall that the DLL of Figure 8 pro-

V1 duces N equally spaced clock edges
V2 (= V6) with a resolution of TCK /N seconds.
If we combine these edges, we can
V1 . V2 V1
generate an output having a higher
V6
frequency. Shown in Figure 12(a) is
V3 . V4
V3 an eight-phase delay line, with its
V1 . V2 + V3 . V4 V8 outputs applied to XOR gates. Not-
Vout ing that the DLL aligns V8 and V0,
V1 . V2 + V3 . V4 V5
V1 we observe a phase difference of
45c between adjacent taps. As illus-
V1 . V2 + V3 . V4 + V9
trated in Figure 12(b), the XOR result
V1 . V2 + V3 . V4 V4
of V1 and V2 exhibits pulses every
t
TCK /2 seconds and so does the XOR
(a) (b)
result of V3 and V4 . Since Va and Vb
have a phase difference of 90c, their
Figure 13: (a) The use of AND and OR operations for frequency multiplication and (b) the
logical implementation. XOR result, VX , has a period of TCK /4
seconds. From another perspective,
the first rank of XOR gates doubles
the frequency, and the second rank
fmult False doubles again. The eight-stage DLL
Edge Combiner ÷N PFD Lock
Flag
thus multiplies the input frequency
by a factor of four. Note that the
CKin CKout fin
XORs introduce uniform loading
fin
along the delay line (if the XOR gates
Vcont are symmetric with respect to their
PFD CP two inputs). The XOR stages form an
C1
“edge combiner” here.
It is possible to design an edge
Figure 14: A false lock detector using a frequency multiplier. combiner using AND and OR gates.
The delay line shown in Figure 12(a)
provides delayed signals and their
The third issue in the multiphase DLL Frequency-Multiplying DLLs complements. For ex­­ample, V5 = V1,
of Figure 8 relates to the mismatches An important shortcoming of DLLs V6 = V2, etc. If we AND V1 and V2,
between the delay units, which trans- is their inability to perform fre­­ we obtain one pulse of width TCK /8
late to departures in the phase spacings quen­­­c y synthesis, i.e., generate ar­­ every TCK seconds [Figure 13(a)].
from TCK /N. Present in both the driv- bitrary output frequencies. In some Similarly, V3 · V4 exhibits the same
ing strength of the stages and their load applications, a DLL can multiply shape but shifted by TCK /4. It follows
capacitances, the mismatches must be the input frequency by an integer, that V1 · V2 + V3 · V4 yields two such
managed by proper sizing, careful lay- thereby acting as a “poor man’s” fre- pulses every TCK seconds. Noting that
out, and Monte Carlo simulations. quency synthesizer. V5 · V6 + V7 · V8 has the same behavior

14 su m m e r 2 0 18 IEEE SOLID-STATE CIRCUITS MAGAZINE

 RF
R2
R2
R1
A C1 C2
–
Vout
+ R1 R3
B +– + +–
Vin Vin Vx Vout
–+ – –+
R3 R4
R1 R3
IC 2 Req C1 C2

C2 R2
RF

Figure 15: A noninverting integrator. Figure 16: The Tow–Thomas biquad.

but shift­­ed by TCK /2, we conclude in Vcont . What is the effect of this 2) Suppose the Tow –Thomas bi-
that V1 · V2 + V3 · V4 + V5 · V6 + V7 · V8 ripple on the output waveform? quad of Figure 16 senses a large,
is a signal with four times the input narrowband undesired chan-
frequency. The implementation is Answers to Last Issue’s Questions nel at ~ = ~ -3dB . Which of the two
shown in Figure 13(b). In reality, the 1) Figure 15 shows a noninverting inte- integrators produces greater volt-
AND and OR gates are replaced grator. Derive the condition for the age swings and hence experiences
by NANDs. elements so that the circuit acts as more nonlinearity?
The multiplication factor in Fig- an ideal integrator. What is the prin- We have Vout /VX = - 1/ (R 3 C 2 s) .
ures 12 and 13 is difficult to change, cipal difficulty with this topology? The relative swings in the two
a point of contrast to PLLs. Moreover, W e h a v e VB . VA = Vout R 1 / integrator outputs depend on the
delay mismatches among the stages (R 1 +R 2). Also, (Vin -VB)/R 3 + (Vout - component values. For ex­­ample,
give rise to jitter and spurs. VB) /R 4 = VB C 2 s. Thus, i f C 1 = C 2, R 2 = R 3 = R F , a n d
The frequency multiplication Q = 1, t h e n ~ n = 1/ (R 3 C 2) a n d
Vin = V R1 C2 s
ability of DLLs can be exploited to R3 out
R1 + R2 ~ -3dB = 1.27~ n = 1.27/ (R 3 C 2) .
detect false locking. Consider the T h a t i s , | Vout /VX | = 1/1.27. I n
+ Vout c R 1
architecture shown in Figure 14, R1 + R2 this case, the first integrator com-
R + R4
where an edge combiner multiplies (8) $ 3 - 1 m. presses first. If the undesired
R3 R4 R4
the frequency by a factor of N. This channel occurs at 2~ -3dB, we have
result, fmult, is then divided by N and For ideal integration, the second | Vout /VX | = 1/2.54, observing even
compared to fin . With correct lock- term on the right-hand side must a greater swing disparity.
ing, fmult = N fin, leading to a low aver- vanish, yielding R 2 /R 1 = R 4 /R 3 .
age value for the PFD output. In the Another perspective provides References
[1] J. J. Spilker and D. T. Magill, “The delay-
presence of false lock, on the other additional insight. If Vout is pro- lock discriminator: An optimum tracking
hand, the total delay from CK in to portional to the integral of Vin, device,” Proc. IEEE, vol. 49, pp. 1403–1416,
Sept. 1961.
CK out is equa l to or g reater tha n t h e n s o a r e VA a n d VB . T h u s , [2] M. Bazes, “A novel precision MOS synchro-
2TCK, and fmult < N fin . As a result, the I C2 = C 2 dVB /dt is also proportion­ nous delay line,” IEEE J. Solid-State Cir-
cuits, vol. 20, pp. 1265–1271, Dec. 1985.
PFD output exhibits a higher aver- ­a l to Vin, a condition that is met [3] M. G. Johnson and E. I. Hudson, “A vari-
age. The false lock flag can then be only if the Norton equivalent of the able delay line PLL for CPU-coprocessor
synchronization,” IEEE J. Solid-State Cir-
used to adjust the tuning range of circuit in the dashed box reduces cuits, vol. 23, pp. 1218–1223, Oct. 1988.
the delay line so that the total delay to an ideal current source. Since [4] M. J. E. Lee, W. J. Dally, T. Greer, H. T. Ng,
R. Farjad-Rad, J. Poulton, and R. Senthi-
remains less than 2TCK. the Norton resistance is given by nathan, “Jitter transfer characteristics of
R 3 | | R eq, we set R eq to - R 3 and delay-locked loops: Theories and design
techniques,” IEEE J. Solid-State Circuits,
Questions for the Reader hence obtain R 2 /R 1 = R 4 /R 3 . vol. 38, pp. 614–621, Apr. 2003.
1) Suppose the up and down currents The pr i n c ip a l issue here is [5] A. Homayoun and B. Razavi, “Relation
between delay line phase noise and ring
in the charge pump of Figure 2(d) that the circuit relies on equal oscillator phase noise,” IEEE J. Solid-State
have a mismatch of DI.How does positive and negative feedback Circuits, vol. 49, pp. 384–391, Feb. 2014.
[6] J. Sonntag and R. Leonowich, “A monolithic
the DLL react to this mismatch? factors and is prone to latch up CMOS 10 MHz DPLL for burst-mode data reti-
2) The CP imperfections in Fig- in the presence of component ming,” in Proc. Int. Solid-State Circuits Conf.
Dig. Tech. Papers, Feb. 1990, pp. 194–195.
ure 2(d) create a periodic ripple mismatches.


IEEE SOLID-STATE CIRCUITS MAGAZINE su m m e r 2 0 18 15