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COA ClassSlidemodule 3

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3 views

COA ClassSlidemodule 3

Uploaded by

ssedits050
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Computer Organization

Course Topics
1. Chapter 1: Basic Structures of Computers: Functional Units, Operational concepts, Bus
structures, Software, Performance, Computer Architecture vs Computer Organization
2. Chapter 2: Machine Instructions and Programs: Memory location and addresses, Big-
Module I endian and Little-endian representation, Memory Operations, Instructions and
instruction sequencing, Addressing modes, Assembly Language, Basic Input / Output
operations, subroutine, additional instructions
3. Chapter 6: Arithmetic: Addition and subtraction of signed Numbers, Design of Fast
Module II Adders, Multiplication of positive Numbers, Signed-operand multiplication, Fast
multiplication, Integer Division, Floating-point Numbers (IEEE754 s. . .) and operations.

4. Chapter 5: The Memory System: Basic Concepts, cache Memory, Cache memory
mapping policies, Cache updating schemes, performance consideration, Virtual
Memories, Paging and Page replacement policies, Memory Management requirement,
Module III secondary storage.
5. Chapter 7: Basic Processing Units: Fundamental concepts, Execution of complete
Instructions, Multi bus organization, Hardwired control, Micro programmed control,
RISC vs CISC architecture
Addition and subtraction of signed numbers
• Suppose we want to add
two numbers X and Y.
• The following figure shows
the logic truth table for the
sum and carry-out functions
for adding xi and yi.
• Let ci represents the carry in
the ith stage which is the
carry out of (i1)th stage.
Addition and subtraction of signed numbers

• The logic expression of


si can be implemented
by a 3-input XOR gate.
• The carry-out function
ci+1 is implemented with
a two-level AND-OR
logic circuit.
• We can use a complete
circuit for a single stage
addition, called a full
adder (FA).
Addition and subtraction of signed numbers
• The first figure shows a cascaded
connection of n full adder blocks
which can be used to add two n-bit
numbers.
• Since the carry must propagate or
ripple, through this cascade, the
configuration is called an n-bit
ripple-carry adder.
• The second figure shows the
interconnection of k n-bit adders to
form an adder capable of handling
input number that is kn bit long.
Logic Circuit for Addition & Subtraction
• The logic circuit network perform either
addition or subtraction based on the
value applied to add / sub input control
line.
• This line is set to 0 for addition, making
the Y vector unchanged to one of the
adder input along with a carry in signal c0
of 0.
• When add / sub control is set to 1, the Y
vector is 1’s complemented by the XOR
gate, and c0 is set to 1 to compute the 2’s
complement of Y.
• An XOR gate can be added to detect the
overflow condition cncn1.
Addition and Subtraction Logic Unit
• The n-bit adder can be used to add 2’s complement numbers X and Y where
xn1 and yn1 are the sign bits.
• Overflow can only occurs when the signs of the two operands are the same. In
this case, overflow occurs if the sign of the result is different. To detect the
overflow a circuit can be added to the n-bit adder by implementing the logic
expression:
𝑶𝒗𝒆𝒓𝒇𝒍𝒐𝒘 = 𝒙𝒏−𝟏 𝒚𝒏−𝟏 𝒔𝒏−𝟏 + 𝒙𝒏−𝟏 𝒚𝒏−𝟏 𝒔𝒏−𝟏
• Also overflow occurs when the carry bits cn and cn1 are different. A simpler
alternative circuit for detecting overflow can be obtained by implementing the
expression cn cn1with an XOR gate.
• For the subtraction operation XY on 2’s complement of X and Y, we perform
2’s complement of Y and add it to X.
Design of Fast Adder
• Delay is calculated by adding up the number of logic-gate delays along
the longest signal propagation path through the network.
• In the n-bit ripple-carry adder:
• cn1 is available in 2(n1) gate delays. [For each pair of xi and yi one delay for 3
AND gates and one for OR gate]
• sn1 is available in = number of gate delays of cn1+ 1 [For XOR gate] = 2(n1)
+1 = 2n  1
• cn is available in 2n gate delays.
• Therefore to implement addition/subtraction unit using ripple-carry
adder:
• All sum bits are available in 2n gate delays. [2n 1 gate delays for availability
of sn1 + 1 gate delay for XOR gate on Y input]
• We need some approaches to reduce the delay.
Carry-Lookahead Addition
• The logic expression for sum (si) and carry (ci) of stage i are:
• 𝑠𝑖 = 𝑥𝑖 ⨁𝑦𝑖 ⨁𝑐𝑖
• 𝑐𝑖+1 = 𝑥𝑖 𝑦𝑖 + 𝑥𝑖 𝑐𝑖 + 𝑦𝑖 𝑐𝑖 = 𝑥𝑖 𝑦𝑖 + (𝑥𝑖 +𝑦𝑖 )𝑐𝑖 = 𝐺𝑖 + 𝑃𝑖 𝑐𝑖
where Gi= xi yi(Generate function)
andPi= xi + yi(Propagate function)
• If Gi = 1, then ci+1 = 1, independent of the input carry ci.
• The propagate function means that and input carry will
produce an output carry when either xi or yi is 1.
• All Gi and Pi functions can be formed independently and in
parallel in one logic gate delay after the X and Y vectors are
applied to the inputs of an n-bit adder.
Carry-Lookahead Addition
• Each bit stage contains:
• An AND gate to form Gi
• An OR gate to form Pi
• XOR gate to form Si
• We can write Pi = xi  yi instead of Pi = xi + yi
as it satisfies all cases except when xi = yi = 1.
However, in this case Gi =1 and it does not
matter whether Pi is 0 or 1.
• Therefore, we can use a cascade of two 2-
input XOR gates in place of one 3 input XOR
gate to get the desired outputs in each bit
stage.
Carry-Lookahead Addition
• Expanding ci in terms of i1 subscripted variables and
substituting into ci+1 expression we have:
𝑐𝑖+1 = 𝐺𝑖 + 𝑃𝑖 𝑐𝑖 = 𝐺𝑖 + 𝑃𝑖 𝐺𝑖−1 + 𝑃𝑖−1 𝑐𝑖−1
= 𝐺𝑖 + 𝑃𝑖 𝐺𝑖−1 + 𝑃𝑖 𝑃𝑖−1 𝑐𝑖−1 = . . . .
= 𝐺𝑖 + 𝑃𝑖 𝐺𝑖−1 + 𝑃𝑖 𝑃𝑖−1 𝐺𝑖−2 + . . . . + 𝑃𝑖 𝑃𝑖−1 . . . 𝑃𝑖 𝐺0 + 𝑃𝑖 𝑃𝑖−1 . . . 𝑃0 𝑐0
• So all carries can be obtained in three delays after the
input signals X, Y and c0 are applied because:
• One gate delay to produce all Pi and Gi signals.
• Two gate delays in AND-OR circuit for ci+1.
• All sum bits can be obtained after one XOR gate delay.
Example: Design of a 4-bit adder

• Using carry lookahead adder:


• Number of gate delays for
obtaining all carry bits = 3
• Number of gate delays for
obtaining all sum bits = 4
• Using 4-bit ripple-carry adder:
• Number of gate delays for
obtaining s3 = 7
• Number of gate delays for
obtaining c4 = 8
 Performing n-bit addition in 4 gate delays independent of n is good
only theoretically because of fan-in constraints.

 Last AND gate and OR gate require a fan-in of (n+1) for a n-bit adder.
 For a 4-bit adder (n=4) fan-in of 5 is required.
 Practical limit for most gates.
Problem
Find the number of delays for obtaining
c16 in the following 16-bit carry-lookahead
adder built from four 4-bit adders.
Ans:
• Number of gate delays for obtaining c4 =
3
• Number of gate delays for obtaining c8 =
3 + 2 (Since Gi and Pi are already
calculated)
• Number of gate delays for obtaining c16
=3+2+2+2=9
• Number of gate delays for obtaining all
sum bits = 9 + 1 = 10

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