Chapter4
Chapter4
Timebase
The timebase determines the duration of each timebase interval. For Fixed and SLC 5/01 processors, the
timebase is set at 0.01 second.
Definition
Count time base intervals when the instruction is true.
Bit 13: Done (DN) this bit is on when the Accumulation value >= Preset Value
Bit 14: Timer Timing (TT) this bit is on when the timer is timing
Bit 15: Enabled (EN), this bit is on when the timer is energized.
The programmer specifies this value. When the accumulated time reaches the preset value the controller sets
the done bit. When the accumulated value becomes equal to or greater than the preset value, the done bit is
set. Usually preset value is from 0 - 32,767
This is the time elapsed since the timer was last reset. When enabled the timer updates this continually.
Definition
Counts time base intervals when the instruction is false.
Definition
Counts time base intervals when the instruction is true and
retains the accumulated value when the instruction goes
false or when power cycle occurs.
The Retentive Timer instruction is a retentive instruction
that begins to count time base intervals when rung
conditions become true.
The Retentive Timer instruction retains its accumulated
value when any of the following occurs:
Rung conditions become false.
Changing Processor mode from REM run /Test / program mode.
The processor loses power (provided that battery back up is still
maintained).
A fault occurs.
When the RES instruction is enabled, it resets the Timer On Delay (TON), Retentive
Timer (RTO), Count Up (CTU), or Count Down (CTD) instruction having the same
address as the RES instruction.
Cascading Timers
If an event requires a longer time-delay than a timer is capable of providing then multiple
timers may be cascaded. That is, one timer completes a timing cycle and then activates
another timer.
The count value must remain in the range of -32768 to +32767. If the count value goes above +32767
or below -32768, the counter status overflow (OV) or underflow (UN) bit is set.
A counter can be reset to zero using the reset (RES) instruction
Definition
Increments the accumulated value at each false to true transition and retains the accumulated value when the
instruction goes false or when power cycle occurs.
The CTU is an instruction that counts false to true transition. When this transition happens the accumulated value
is incremented by one count.
A CTU accumulation is reset by the RES instruction.
If the accumulation value is over the maximum range then the overflow (OV) bit will be true.
Definition
Decrements the accumulate value at each false to true transition and retains the accumulated value when the
instruction goes false or when power cycle occurs.
The CTD is an instruction that counts false to true transition. When this transition happen the accumulated
value is decrements by one count.
A CTD accumulation is reset by the RES instruction.
If the accumulation value is below the minimum range then the underflow (UN) bit will be true.
Definition
Refer to Datasheet