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projects for systolic arrays

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14 views

projects for systolic arrays

pgorpkbrhkbgkgerkbekb f f d c

Uploaded by

harshithparitala4
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Projects for systolic arrays in VLSI:

Project 1: Matrix Mul plica on Using a Systolic Array in Python


Objec ve: Simulate a systolic array for matrix mul plica on using Python.
Steps:
1. Understand the Algorithm:
o Study how systolic arrays perform matrix mul plica on.
o Break down the opera on into processing element (PE) computa ons.
2. Design PEs:
o Write a Python func on represen ng a PE that takes inputs, performs
mul plica on, and accumulates results.
3. Create the Array:
o Implement a 2D grid of PEs and simulate the data flow (rows of one matrix
and columns of another).
4. Visualize Results:
o Use Matplotlib to visualize data flowing through the array and the final
output matrix.
Tools:
 Python (NumPy, Matplotlib).

Project 2: Implement Systolic Array in Verilog


Objec ve: Design a hardware implementa on of a simple systolic array for 2x2 matrix
mul plica on.
Steps:
1. Learn Verilog Basics:
o Study syntax and concepts like modules, registers, and always blocks.
2. Implement a PE:
o Create a Verilog module for a single PE that takes two inputs, mul plies them,
and accumulates the result.
3. Assemble the Array:
o Instan ate mul ple PEs in a grid-like structure.
o Route data inputs and outputs between PEs.
4. Simulate:
o Use ModelSim or another HDL simulator to test the design with sample
matrices.
Tools:
 Verilog, ModelSim or Xilinx Vivado.

Project 3: FPGA Implementa on of Systolic Array


Objec ve: Deploy a systolic array for matrix-vector mul plica on on an FPGA.
Steps:
1. Design for FPGA:
o Use your Verilog implementa on of a systolic array.
o Modify the design to accept data streams from external memory.
2. Simulate:

o Test the design with FPGA simula on tools (e.g., Vivado).


3. Deploy:
o Load the design onto an FPGA (e.g., Xilinx Zynq).
o Use input switches or a UART interface to feed data.
4. Visualize Output:
o Display the output on an LED array or send it to a connected computer.
Tools:
 FPGA board (e.g., Xilinx ZedBoard).
 Xilinx Vivado.

Project 4: Systolic Array for Convolu on (Python to HDL)


Objec ve: Implement a systolic array to perform 2D convolu on for image processing.
Steps:
1. Simulate in Python:
o Write a Python script for a systolic array that performs convolu on on a small
grayscale image.
2. Translate to Verilog:
o Implement the array in Verilog, with PEs performing mul ply-accumulate
opera ons.
3. Test and Op mize:
o Test the design on small input images.
o Op mize for speed and resource usage.
4. Deploy on FPGA:
o Integrate the systolic array with an external camera or image source.
o Display the processed image using an HDMI interface or send it to a PC.
Tools:
 Python, Verilog, FPGA tools.

Project 5: Design and Fabrica on of a Systolic Array ASIC


Objec ve: Take the systolic array through the VLSI design flow.

Steps:
1. Create RTL Design:
o Use your Verilog implementa on of a systolic array.
2. Synthesize the Design:
o Use Synopsys or Cadence tools for synthesis.
o Generate a gate-level netlist.
3. Perform Layout:
o Place and route the design using EDA tools.
o Op mize for area, power, and ming.
4. Simulate and Verify:

o Run simula ons to validate the physical design.


5. Fabricate (Op onal):
o Submit your design for fabrica on through a mul -project wafer (MPW)
program, such as MOSIS.
Tools:
 Cadence, Synopsys, or Mentor Graphics EDA tools.

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