MPQ7210_r1.0

MPQ7210
60V, 2A, Synchronous,

Dual-Buck LED Driver with SPI,
AEC-Q100 Qualified
DESCRIPTION FEATURES
The MPQ7210 is synchronous, dual-buck LED • Built for Automotive LED Applications
driver designed to operate as a constant current o Wide 4.5V to 60V Input Voltage (VIN)
source to drive 2 independent LED channels. Range
Each channel can support up to 2A of output o 2A Dual-Channel Buck
current (IOUT), and they can also be connected in o 4A Single-Channel Buck
parallel to support up to 4A of current. o ±3% LED Current Accuracy
The 4.5V to 60V input voltage (VIN) range allows o Operating Junction Temperature (TJ)
a string of up to 12 LEDs to be connected in from -40°C to +150°C
series per channel. When paired with a matrix o 8-Bit Analog Dimming
manager, such as the MPQ7241, the MPQ7210 o 12-Bit PWM Dimming
can achieve an ideal architecture to drive • Optimized for EMC/EMI
adaptive driving beams or matrix headlights. o Selectable 220kHz, 420kHz, 1.1MHz,
and 2.3MHz Switching Frequency (fSW)
The safety protection suite includes a fault (/FS) o Frequency Spread Spectrum (FSS)
pin used to report over-current protection (OCP), o CISPR25 Class 5 Compliant
under-voltage lockout (UVLO), early thermal o Safety
warning, and thermal shutdown. These features • Safety Protection Suites
can be used to assist the system in meeting o Analog-to-Digital Converter (ADC) to
functional safety requirements. Monitor the VIN, Output Voltage (VOUT),
An integrated 10-bit analog-to-digital converter VCC Voltage (VCC), and TJ
(ADC) monitors VIN, the output voltage (VOUT), o Failsafe (/FS) Pin and Registers
VCC voltage (VCC), and junction temperature o Output Under-Voltage Protection (UVP)
(TJ), and logs the data into the internal registers. o Over-Current Protection (OCP)
These diagnostics can be read back by a o Early Thermal Warning
microcontroller (MCU) through the serial o Thermal Shutdown
peripheral interface (SPI). The SPI can also be o Serial Peripheral Interface (SPI) with
used to preset dimming profiles within the Configurable Features
registers and mask undesired signals on the fault o Current Limit
(/FS) pin. • Additional Features
o Multi-Page One-Time Programmable
The MPQ7210 minimizes the need for a number (OTP) Memory
of external components and is available in a o Available in a QFN-26 (5mmx5mm)
QFN-26 (5mmx5mm) package. It is available in Package with Wettable Flanks
AEC-Q100 Grade 1. o Available in AEC-Q100 Grade 1
APPLICATIONS
• Adaptive Driving Beam Headlights
• Matrix Headlights
• Daytime Running Lights (DRLs)
• Side Markers
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
For MPS green status, please visit the MPS website under Quality
Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
trademarks of Monolithic Power Systems, Inc. or its subsidiaries.
MPQ7210 Rev. 1.0 MonolithicPower.com 1

10/18/2023 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2023 MPS. All Rights Reserved.
MPQ7210 – 60V, 2A, DUAL-BUCK LED DRIVER WITH SPI, AEC-Q100
TYPICAL APPLICATION
Efficiency vs. Input Voltage
VIN VIN1/ BST1
VIN2 Buck 1 and buck 2, 12 LEDs
(VLED = 38V), L = 68µH
MPQ7210 98 14
SW1
EN1 Efficiency
97 12
POWER LOSS (W)

EN2 ISP1
EFFICIENCY (%)
DIM1 96 10
ISN1 ILED=2.0A/CH
DIM2
ILED=1.5A/CH
BST2 95 ILED=1.0A/CH 8
ILED=0.5A/CH
/CS 94 6
SPI CK
SW2
SI 93 4
SO
ISP2
92 2
/FS ISN2
Power_Loss
VCC VCC 91 0
AGND PGND
42 45 48 51 54 57 60
INPUT VOLTAGE (V)

ORDERING INFORMATION
Part Number* Package Top Marking MSL Rating**
MPQ7210GUE-xxxx-AEC1***, **** QFN-26 (5mmx5mm) See Below 2
* For Tape & Reel, add suffix -Z (e.g. MPQ7210GUE-xxxx-AEC1-Z).
** Moisture Sensitivity Level Rating
*** “xxxx” is the configuration code identifier for the register settings stored in the OTP register. Each “x” can be a
hexadecimal value between 0 and F. The default code is “0000”. Contact an MPS FAE to create this unique
number.
**** Wettable flank
TOP MARKING
MPS: MPS prefix

YY: Year code
WW: Week code
MP7210: Part number
LLLLLLL: Lot number
E: Wettable Flank
PACKAGE REFERENCE
TOP VIEW
DIM1 EN1 N/C ISN1 ISP1 VIN1
26 25 24 23 22 21
20 PGND1
/FS 1
VCC 2 19 SW1
AGND 3 18 BST1
/CS 4 17 N/C
CK 5 16 BST2
SI 6 15 SW2
SO 7
14 PGND2
8 9 10 11 12 13
DIM2 EN2 N/C ISN2 ISP2 VIN2
QFN-26 (5mmx5mm)

PIN FUNCTIONS
Pin # Name Description
/FS indicator. The /FS pin is an open-drain output that is active low. Pull /FS to VCC through
a resistor. /FS pulls low when over-current protection (OCP), output under-voltage protection
(UVP), thermal warning (TW), or thermal shutdown (TSD) occur. If EN1 and EN2 pull low at
1 /FS
the same time, or VCC or VIN under-voltage lockout (UVLO) occurs, the /FS pin de-asserts
and returns to normal. The microcontroller (MCU) can write to register 0x0A to clear /FS error
flags.
Internal bias supply. The VCC pin supplies power to the internal circuit. Place a ≥4.7µF
2 VCC decoupling capacitor from VCC to ground, and close to VCC. There is no internal VCC
regulator from VIN. VCC can only be powered from an external 5V source.
3 AGND Analog ground. The AGND pin is the reference ground of the internal logic circuit.
4 /CS SPI chip selection input. Connect the /CS pin to the master CS.
5 CK SPI clock input. Connect the CK pin to the master CK.
6 SI SPI data input. Connect the SI pin to the master MOSI.
7 SO SPI data output. Connect the SO pin to the master MISO.
Dimming control. In PWM dimming mode 1, pull this pin high for X% dimming duty, and pull
this pin low for 0%, dimming duty (where X% can be set from 0% to 100% via the SPI with a
register change). In PWM dimming mode 2, the LED current follows the DIM pin. Apply a
DIM2,
8, 26 100Hz to 2kHz external clock to the DIM pin for PWM dimming. In dimming mode 3, pull this
DIM1
pin high for a 100% dimming duty cycle, and pull this pin low for X% dimming duty (where
X% can be set from 0% to 100% by the internal register). For more details, see the Pulse-
Width Modulation (PWM) Dimming section on page 27.
EN2, Enable control. Pull the EN1 and EN2 pin high to enable the part; pull EN1 and EN2 low to
9, 25
EN1 shut down the part.
10, 17,
N/C No connection.
24
ISN2,Negative current-sense input. Connect the ISN2 and ISN1 pin to the negative terminals of
11, 23
ISN1the current feedback resistors.
Positive current-sense input. Connect the ISP2 and ISP1 pin to the positive terminals of
ISP2,
12, 22 the current feedback resistors. This pin is also used as the sensing signal for the output
ISP1
voltage (VOUT).
Input supply. The MPQ7210 operates from a 4.5V to 60V input rail. Use an input capacitor
VIN2,
13, 21 (CIN) to decouple the input rail. VIN1 and VIN2 are independent. Make the VINx connections
VIN1
with a wide PCB trace.
PGND2, Power ground. The PGND pin is the reference ground of the power device and requires
14, 20
PGND1 careful consideration during PCB layout. It is typically used to dissipate the thermal heat.
Switch node. The SW2 and SW1 pin is the middle point of the high-side and low-side
SW2,
15, 19 MOSFET (HS-FET and LS-FET, respectively). To reduce the noise coupling and improve
SW1
EMI, it is recommended to make a wide SW trace and minimize the SW node’s size.
Bootstrap. The BST2 and BST1 pin typically requires a 0.1µF capacitor connected between
BST2, the SWx and BSTx pins to form a floating supply across the HS-FET driver. A resistor can
16, 18
BST1 be placed between SWx and BSTx to reduce the SW voltage spike and improve EMI
performance.
Exposure thermal pad. The exposed pad has no internal electrical connection to GND.
- EP Connect the exposed pad to the external GND plane on the board for optimal thermal
performance.

ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance θJA θJC

VINX - VPGND/AGND ............................-0.3V to +65V QFN-26 (5mmx5mm)
VSWX - VPGND/AGND…………………………………... JESD51-7 ........................ 35.5.....4.8......°C/W (5)
…………………..-0.3V to VIN - VPGND/AGND + 0.3V EVQ7210-U-00A .. ............27.9.....2.7......°C/W (6)
VBSTX ................................................. VSW + 5.5V
VISPX - VPGND/AGND ...........................-0.3V to +60V Notes:
1) Absolute maximum ratings are rated under room temperature,
VISNX - VPGND/AGND ...........................-0.3V to +60V unless otherwise noted. Exceeding these ratings may damage
VISPX - VISNX ..................................-0.3V to +0.3V the device.
All other pins - VPGND/AGND .............-0.3V to +5.5V 2) The maximum allowable power dissipation is a function of the
maximum junction temperature, TJ (MAX), the junction-to-
Continuous power dissipation (TA = 25°C) (2) (6) ambient thermal resistance, θJA, and the ambient temperature,
QFN-26 (5mmx5mm) ............................... 4.48W TA. The maximum allowable continuous power dissipation at
Junction temperature (TJ) .........................150°C any ambient temperature is calculated by PD (MAX) = (TJ
(MAX) - TA) / θJA. Exceeding the maximum allowable power
Lead temperature .....................................260°C dissipation can produce an excessive die temperature, and the
Storage temperature ................ -65°C to +150°C regulator may go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
ESD Ratings damage.
3) Per AEC-Q100-002.
Human body model (HBM) ................ Class 2 (3) 4) Per AEC-Q100-011.
Charged-device model (CDM) .......Class C2b (4) 5) Measured on a JESD51-5/7, 4-layer PCB, where there is a
thermal via array under the exposed pad. The values given in
this table are only valid for comparison with other packages and
Recommended Operating Conditions cannot be used for design purposes. These values were
Supply voltage (VIN - VPGND) ............. 4.5V to 60V calculated in accordance with JESD51-5/7, and simulated on a
specified JEDEC board. They do not represent the
Supply voltage (VCC - VPGND) ........... 4.5V to 5.5V performance obtained in an actual application. The value of θJC
LED current (ILED) (dual-channel) .......... Up to 2A shows the thermal resistance from the junction-to-case bottom.
ILED (single-channel) .............................. Up to 4A 6) Measured on a standard EVB for the MPQ7210,
83.5mmx83.5mm, 4-layer PCB, 2oz. The value of θJC shows
Operating junction temp (TJ) .... -40°C to +150°C the thermal resistance from junction-to-case top.

ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 3.3V, TJ = -40°C to +150°C, typical values are at TJ = 25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Input Supply
VIN supply current
ISD VENx = 0V, VDIMx = 0V, VCC = 5V 1 8.5 μA
(shutdown)
VENx = 3.3V, VDIMx = 0V,
VIN supply current (standby) ISTD 32 80 μA
VCC = 5V
Input voltage (VIN) under-
voltage lockout (UVLO) rising VINUVLO_R VIN - VPGND 3.8 4.2 4.6 V
threshold
VIN UVLO falling threshold VINUVLO_F VIN - VPGND 3.6 4 4.4 V
VIN UVLO threshold
VINUVLO_H VIN - VPGND 0.2 V
hysteresis
VCC Supply
VCC supply current
IVCC(SD) VENx = 0V, VDIMx = 0V, VCC = 5V 3.2 50 μA
(shutdown)
VENx = 3.3V, VDIMx = 0V,
VCC supply current (standby) IVCC(STD) 2 3.5 mA
VCC = 5V
VCC supply current VENx = VDIMx = 3.3V, VCC = 5V,
(switching)
IVCC(SW) fSW = 420kHz
3.5 mA
VCC voltage (VCC) UVLO

VCCUVLO_R VCC - VAGND 3.8 4.2 4.6 V
rising threshold
VCC UVLO falling threshold VCCUVLO_F VCC - VAGND 3.6 4 4.4 V
VCC UVLO threshold
VCCUVLO_H VCC - VAGND 0.2 V
hysteresis
Switch and Frequency
High-side (HS) switch on
RDS(ON)-HS VBST-SW = 5V, ILED = 1A 235 445 mΩ
resistance
Low-side (LS) switch on
RDS(ON)-LS VCC = 5V, ILED = 1A 235 445 mΩ
resistance
Switch leakage SWLKG VENx = 0V, VSW = 12V 5 μA
Peak current limit (7) ILIMIT_PEAK Register setting = 3.5A 2.5 3.5 4.5 A
Zero-current detection (ZCD)
(7) IZCD Zero-current detection 0 mA
Register setting = 220kHz 180 220 320 kHz

Register setting = 420kHz 360 420 470 kHz
Switching frequency fSW
Register setting = 1.1MHz 0.8 1.1 1.35 MHz
Register setting = 2.3MHz 2.0 2.3 2.6 MHz
Maximum duty cycle (7) 93% 95%
Spread spectrum frequency (7) 10 kHz
Spread spectrum frequency
±10% fSW
range (7)
Minimum on time (7) tON_MIN 125 ns
Minimum off time (7) tOFF_MIN 120 ns

ELECTRICAL CHARACTERISTICS (continued)

VIN = 12V, VEN = 3.3V, TJ = -40°C to +150°C, typical values are at TJ = 25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
EN
EN1/EN2 rising threshold VEN_R VEN - VAGND 0.8 1.0 1.2 V
EN1/EN2 falling threshold VEN_F VEN - VAGND 0.65 0.85 1.05 V
EN1/EN2 threshold
VEN_H VEN - VAGND 150 mV
hysteresis
VEN - VAGND = 2V 2 5 μA
EN1/EN2 input current IEN
VEN - VAGND = 0V 0 0.2 μA
DIM
DIM1/DIM2 high threshold VDIM_R
VDIM - VAGND 1.25 2 V
DIM1/DIM2 low threshold VDIM_F
VDIM - VAGND 0.8 1.15 V
VDIM - VAGND = 2V 0 0.2 μA
DIM1/DIM2 input current IDIM
VDIM - VAGND = 0V 0 0.2 μA
Current-Sense and Analog-to-Digital Converter (ADC)
VISP1 = 48V, VISN1 = 47.8V,
194 200 206 mV
ANA_DIMx = 2’b11001000
Current-sense accuracy VSEN
VISP1 = 5V, VISN1 = 4.8V,
194 200 206 mV
ANA_DIMx = 2’b11001000
ADC full scale 2 2.048 2.095 V
ADC resolution (10 bits) (7) 2 mV
Register = 100% 1.188 1.203 1.217 V
Analog dimming reference
VREF Register = 50% 0.592 0.6 0.608 V
voltage
Register = 5% 56.7 60 63.3 mV
Output under-voltage
VUV_TH 2.1 2.3 2.5 V
threshold
/FS Indicator
/FS assertion deglitch time
tFS_TD 10 μs
after start-up
/FS pull-down resistor 10 20 Ω
Thermal warning flag
TWARN 105 125 145 °C
threshold (7)
Thermal warning flag
TWARN_HYS 20 °C
hysteresis (7)
Thermal shutdown threshold
(7) TSD 155 170 185 °C
Thermal shutdown
TSD_HYS 20 °C
hysteresis (7)

SPI CHARACTERISTICS
VIN = 12V, VEN = 2V, TJ = -40°C to +150°C, typical values are at TJ = 25°C, unless otherwise noted.
Parameters Symbol Condition Min Typ Max Units
Serial Peripheral Interface (SPI) Timing Requirements
CK period (7) tSPI 250 ns
CK low time (7) tCKL 125 ns
CK high time (7) tCKH 125 ns
Time between the falling
edge of /CS and SO output tFSIV Falling: SO < 0.4V, rising: SO > 2V 125 ns
valid (7)
Time between falling edge Falling: SO < 0.4V, rising: SO > 2V,
tSOV 60
of CK and SO data valid (7) open drain
Set-up time of SI before the
tSIS 30 ns
rising edge of CK(7)
Hold time for SI after the
tSIH 30 ns
rising edge of CK (7)
Hold time of /CS after the
tHCS 62.5 ns
last rising edge of CK (7)
Delay between the rising
edge of /CS and SO tri- tSOTRI 120 ns
state (7)
Minimum time between two
tMIN2SPI 2 µs
SPI commands (7)
High level input voltage VI_HIGH CS, CK, SI; VIO = 3.3V, 5V 2 V
Low level input voltage VI_LOW CS, CK, SI; VIO = 3.3V, 5V 0.8 V
Input voltage hysteresis VI_HYS CS, CK, SI; VIO = 3.3V, 5V 130 mV
SO output high voltage VO_HIGH VCC = 5V 1.8 V
SO output low voltage VO_LOW VCC = 5V, ISO = 10mA 0.6 V
SO capacitance (7) CSO Pull-up resistor = 250Ω 50 pF
(7)
Deglitch time for CK tCK_FILTER 50 85 ns
Notes:
7) Not tested in production. Guaranteed by design and characterization.
tSPI tCKH
tHCS
/CS
CK
tSIS tSIH
tCKL
SI X Bit[6] Bit[5] P X
tFSIV tSOV tSOTRI
SO Z
Bit[6] Bit[5] FSI
Figure 1: SPI Model 3

TYPICAL CHARACTERISTICS
VIN = 12V, TJ = -40°C to +150°C, unless otherwise noted.
VIN Shutdown Current vs. VIN Standby Current vs.

Temperature Temperature
1.3 37
1.2 35
IVIN(SHDN) (µA)
IVIN(STD) (µA)
1.1 33
1.0 31
0.9 29
0.8 27
0.7 25
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TEMPERATURE ( C) TEMPERATURE ( C)
VIN UVLO Threshold vs. VCC Shutdown Current vs.

4.4 8.5
4.3 7.5
VINUVLO (V)
IVCC(SHDN) (µA)
4.2 6.5
4.1 5.5
4.0 4.5
3.9 Rising 3.5
Falling
3.8 2.5
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
VCC Standby Current vs. VCC UVLO Threshold vs.

2.2 4.4
2.1 4.3
VCCUVLO (V)
IVCC(STD) (mA)
2.0 4.2
1.9 4.1
1.8 4.0
1.7 3.9 Rising

Falling
1.6 3.8
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150

TYPICAL CHARACTERISTICS (continued)

HS Switch On Resistance vs. LS Switch On Resistance vs.

390 390
350 350
RDS(ON)-HS (mΩ)
RDS(ON)-LS (mΩ)
310 310
270 270
230 230
190 190
150 150
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Peak Current Limt vs.

Temperature
Register setting = 3.5A ZCD Current vs. Temperature
3.8 50
3.7 30
ILIMIT_PEAK (A)
IZCD (mA)
3.6 10
3.5 -10
3.4 -30
3.3 -50
3.2 -70
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Switching Frequency vs. Switching Frequency vs.

Register setting = 220kHz Register setting = 420kHz
235 425
230 423
fSW (kHz)
fSW (kHz)
225 421
220 419
215 417
210 415
205 413
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150


Switching Frequency vs.

Temperature Minimum On Time vs.
Register setting = 1100kHz Temperature
1,130 141
1,120 137
tON_MIN (ns)
fSW (kHz)
1,110 133
1,100 129
1,090 125
1,080 121
1,070 117
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Minimum Off Time vs.

Temperature EN Threshold vs. Temperature
126 1.2
124 1.1
tOFF_MIN (ns)
VEN (V)
122 1.0
120 0.9
118 0.8
116 Rising
0.7
Falling
114 0.6
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TEMPERATURE ( C)
TEMPERATURE ( C)
Current-Sense Voltage vs.

Temperature
DIM Threshold vs. Temperature ADIM[7:0] = 0xC8
1.4 203
1.3 202
VDIM (V)
VSEN (mV)
1.2 201
1.1 200
1.0 199
0.9 Rising 198
Falling
0.8 197
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150


Output UV Threshold vs.

Temperature
2.6
2.5
VUV_TH (V)
2.4
2.3
2.2
2.1
2.0
-50 -25 0 25 50 75 100 125 150
TEMPERATURE ( C)

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 48V, 12 LEDs in series (VLED = 38V), fSW = 420kHz, L = 68µH, TA = 25°C, unless otherwise noted.
Efficiency vs. Input Voltage Efficiency vs. Input Voltage

Buck 1 only, 12 LEDs (VLED = 38V), Buck 1 and buck 2, 12 LEDs
L = 68µH (VLED = 38V), L = 68µH
98 7 98 14
Efficiency Efficiency
97 6 97 12
POWER LOSS (W)
POWER LOSS (W)

EFFICIENCY (%)
EFFICIENCY (%)
96 ILED1=2.0A 5 96 10
ILED=2.0A/CH
ILED1=1.5A ILED=1.5A/CH
95 ILED1=1.0A 4 95 ILED=1.0A/CH 8
94 3 94 6
93 2 93 4
92 1 92 2
Power_Loss Power_Loss
91 0 91 0
42 45 48 51 54 57 60 42 45 48 51 54 57 60
INPUT VOLTAGE (V) INPUT VOLTAGE (V)

L = 68µH (VLED = 31V), L = 68µH
98 7 98 14
97 6 97 12
POWER LOSS (W)
POWER LOSS (W)

EFFICIENCY (%)
EFFICIENCY (%)
96 5 96 10
95 ILED1=1.5A 4 95 ILED=1.5A/CH 8
94 ILED1=0.5A 3 94 ILED=0.5A/CH 6
93 2 93 4
92 1 92 2
91 0 91 0
36 40 44 48 52 56 60 36 40 44 48 52 56 60

L = 68µH (VLED = 25V), L = 68µH
97 7 97 14
96 6 96 12
POWER LOSS (W)
POWER LOSS (W)

EFFICIENCY (%)
EFFICIENCY (%)
95 5 95 10
94 ILED1=1.5A 4 94 ILED=1.5A/CH 8
93 ILED1=0.5A 3 93 ILED=0.5A/CH 6
92 2 92 4
91 1 91 2
90 0 90 0
30 35 40 45 50 55 60 30 35 40 45 50 55 60

TYPICAL PERFORMANCE CHARACTERISTICS (continued)


Buck 1 only, 6 LEDs (VLED = 19V), Buck 1 and buck2, 6 LEDs
L = 68µH (VLED = 19V), L = 68µH
97 7 97 14
96 6 96 12
POWER LOSS (W)

POWER LOSS (W)
EFFICIENCY (%)
95 95
EFFICIENCY (%)
5 10
94 94 ILED=2.0A/CH
ILED1=2.0A
93 ILED1=1.5A 4 93 ILED=1.5A/CH 8
92 ILED1=1.0A 92 ILED=1.0A/CH
ILED1=0.5A 3 ILED=0.5A/CH
6
91 91
2 4
90 90
89 1 89 2
88 0 88 0
24 30 36 42 48 54 60 24 30 36 42 48 54 60
Case Temperature Rising vs. Case Temperature Rising vs.

Input Voltage Input Voltage
CASE TEMPERATURE RISING ( C)
CASE TEMPERATURE RISING ( C)
L= 68µH (VLED = 36V), L= 68µH

56 90
48 ILED1=1.5A
80 ILED=1.5A/CH
ILED1=1.0A 70 ILED=1.0A/CH
40 ILED1=0.5A ILED=0.5A/CH
60
32 50
24 40
30
16
20
8
10
0 0
42 44 46 48 50 52 54 56 58 60 42 44 46 48 50 52 54 56 58 60
Note:
8) The efficiency and thermal curves are based on Figure 12 on page 48 when RBST = 0Ω, and the output and input filters have been removed.
L = 68µH (e.g. Wurth: 7447709680).


VIN = 48V, 12 LEDs in series (VLED = 38V), fSW = 2.3MHz, L = 68µH, TA = 25°C, unless otherwise noted.

Dual-phase, 12 LEDs (VLED = 36V), Dual-phase, 8 LEDs (VLED = 25V),
L = 15µH L = 15µH
99 15 98 14
97 13 96 12
POWER LOSS (W)
POWER LOSS (W)

EFFICIENCY (%)
EFFICIENCY (%)
95 11 94 10
93 ILED1=1.5A 9 92 ILED=1.5A 8
ILED1=1.2A ILED=1.2A
91 ILED1=1.0A 7 ILED=1.0A
ILED1=0.5A
90 6
ILED=0.5A
89 5 88 4
87 3 86 2
85 1 84 0
42 45 48 51 54 57 60 30 33 36 39 42 45 48 51 54 57 60
Case Temperature Rise vs. Case Temperature Rise vs.

Input Voltage Input Voltage
Dual-phase, 12 LEDs (VLED = 36V), Dual-phase, 8 LEDs (VLED = 25V),
CASE TEMPERATURE RISE (°C)
CASE TEMPERATURE RISE ( C)
L= 15µH L = 15µH
120 120
ILED1=1.5A ILED=1.5A
ILED1=1.2A 105 ILED=1.2A
105 ILED=1.0A
ILED1=1.0A
ILED1=0.5A 90 ILED=0.5A
90
75 75
60
60
45
45
30
30
15
15 30 35 40 45 50 55 60
42 44 46 48 50 52 54 56 58 60
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Note:
9) The efficiency and thermal curves are based on Figure 15 on page 49 when RBST = 0Ω, and the output and input filters have been removed.
L = 15µH (e.g. XAL4040-153MEB).


Steady State (Buck 1) Steady State (Buck 2)

ILED1 = ILED2 = 2A ILED1 = ILED2 = 2A
CH2: VLED1 CH2: VLED2
CH1: VSW1 CH1: VSW2
CH3: IL1 CH3: IL2

CH4: ILED1 CH4: ILED2
Steady State Start-Up through VIN (Buck 1)

CH4: IL2 CH2: VIN

CH3: IL1 CH1: VSW1
CH1: VSW1
CH3: IL1
CH2: VSW2 CH4: ILED1
Start-Up through VIN (Buck 2) Shutdown through VIN (Buck 1)

CH2: VIN CH2: VIN

CH1: VSW2 CH1: VSW1
CH3: IL2 CH3: IL1


Shutdown through VIN (Buck 2) Start-Up through EN1 (Buck 1)

CH2: VEN1
CH2: VIN
CH1: VSW2 CH1: VSW1
CH3: IL2 CH3: IL1
Start-Up through EN2 (Buck 2) Shutdown through EN1 (Buck 1)

CH2: VEN2 CH2: VEN1
CH1: VSW2 CH1: VSW1
CH3: IL2 CH3: IL1
PWM Dimming Mode 1 Steady State

Shutdown through EN2 (Buck 2) (Buck 1)
ILED1 = ILED2 = 2A PWM dimming: 500Hz/50% duty cycle
CH2: VEN2 CH2: VDIM1
CH1: VSW1
CH1: VSW2
CH3: IL1
CH3: IL2
CH4: ILED1
CH4: ILED2


PWM Dimming Mode 1 Steady State PWM Dimming Mode 2 Steady State
(Buck 2) (Buck 1)
PWM dimming: 500Hz/50% duty cycle PWM dimming: 500Hz/50% duty cycle
CH2: VDIM2 CH2: VDIM1
CH1: VSW2 CH1: VSW1
CH3: IL2 CH3: IL1
PWM Dimming Mode 2 Steady State

(Buck 2) PWM Dimming Mode 3 (Buck 1)
PWM dimming: 500Hz/50% duty cycle PWM dimming: 500Hz/50% duty cycle
CH2: VDIM2 CH2: VDIM1
CH1: VSW2 CH1: VSW1
CH3: IL2 CH3: IL1
PWM Dimming Mode 3 (Buck 2) PWM Dimming Mode 2 (Buck 1)

PWM dimming: 500Hz/50% duty cycle Start-up through VIN
CH2: VDIM2
CH2: VIN
CH1: VSW1
CH1: VSW2
CH3: IL1
CH3: IL2



Start-up through VIN Shutdown through VIN
CH2: VIN CH2: VIN

CH1: VSW2 CH1: VSW1
CH3: IL2 CH3: IL1

Shutdown through VIN Start-up through EN1
CH2: VEN1
CH2: VIN
CH1: VSW2 CH1: VSW1
CH3: IL1
CH3: IL2
CH4: ILED1
CH4: ILED2

Start-up through EN2 Shutdown through EN1
CH2: VEN2 CH2: VEN1
CH1: VSW2 CH1: VSW1
CH3: IL2 CH3: IL1
CH4: ILED1
CH4: ILED2


PWM Dimming Mode 2 (Buck 2) Analog Dimming

Shutdown through EN2 ANA_DIM1 = 0x64 (VREF = 100mV)
CH2: VEN2
CH1: VSW2 CH1: VSW1
CH3: IL2
CH3: IL1
Analog Dimming OCP Entry

ANA_DIM2 = 0x64 Latch-off mode, OCP mask disabled
CH2: V/FS
CH3: IL
CH1: VSW2 CH3: ILED
CH3: IL2
CH1: VSW
CH4: ILED2
OCP Entry OCP Recovery

Hiccup mode, OCP mask disabled Hiccup mode, OCP mask disabled
CH2: V/FS
CH2: V/FS
CH3: IL CH3: IL
CH3: ILED CH3: ILED
CH1: VSW CH1: VSW


OCP Entry OCP Recovery

No action mode, OCP mask disabled No action mode, OCP mask disabled
CH2: V/FS
CH2: V/FS
CH3: IL CH3: IL
CH3: ILED CH3: ILED
CH1: VSW CH1: VSW
OCP Entry OCP Entry

Latch-off mode, OCP mask enabled Hiccup mode, OCP mask enabled
CH2: V/FS CH2: V/FS
CH1: VSW CH1: VSW
CH3: IL CH3: IL
CH3: ILED CH3: ILED
OCP Recovery OCP Entry

Hiccup mode, OCP mask enabled No action mode, OCP mask enabled
CH2: V/FS CH2: V/FS
CH1: VSW CH1: VSW
CH3: IL CH3: IL
CH3: ILED CH3: ILED


OCP Recovery UVP Entry

No action mode, OCP mask enabled Latch-off mode, UVP mask disabled
CH2: V/FS CH2: V/FS
CH1: VSW CH1: VSW
CH3: IL CH3: IL
CH3: ILED CH3: ILED
UVP Entry UVP Recovery

Hiccup mode, UVP mask disabled Hiccup mode, UVP mask disabled
CH2: V/FS CH2: V/FS
CH3: IL CH3: IL
CH3: ILED CH3: ILED
CH1: VSW CH1: VSW
UVP Entry UVP Recovery

No action mode, UVP mask disabled No action mode, UVP mask disabled
CH2: V/FS CH2: V/FS
CH3: IL CH3: IL
CH3: ILED CH3: ILED
CH1: VSW CH1: VSW


UVP Entry UVP Entry

Latch-off mode, UVP mask enabled Hiccup mode, UVP mask enabled
CH2: V/FS CH2: V/FS
CH1: VSW CH1: VSW
CH3: IL CH3: IL
CH3: ILED CH3: ILED
UVP Recovery UVP Entry

Hiccup mode, UVP mask enabled No action mode or UVP mask enabled
CH2: V/FS CH2: V/FS
CH1: VSW CH1: VSW
CH3: IL CH3: IL
CH3: ILED CH3: ILED
UVP Recovery
No action mode or UVP mask enabled
Shunt Dimming (UVP Disabled)
CH2: V/FS CH2: VOUT
CH1: VSW CH3: IL

CH3: ILED
CH3: IL
CH3: ILED CH1: VSW


Shunt Dimming On (UVP Disabled) Shunt Dimming Off (UVP Disabled)

LED off to on: 0V to 36V LED on to off: 36V to 0V
CH2: VOUT CH2: VOUT
CH3: IL CH3: IL
CH3: ILED CH3: ILED
CH1: VSW CH1: VSW

FUNCTIONAL BLOCK DIAGRAM

/FS ISN1 ISP1 VIN1
VIN1
Fault BST1
VIN1 UVLO Detect. Current
Charge Pump
VIN2 Sense
Detection
Boot-Low
BST-SW
VIN2 UVLO Level
Shift
VREF1 VREF1
DAC
BG SW1
VCC BG
Buffer VREF2 PVCC1
VREF2 VSNS_AVG1
DAC Average
Current HS On
AGND VCC UVLO Error
Amp. Hysteresis LS On
VREF1 Control
PGND1
Oscillator
ADC_SEL VIN2
4MHz Clock
VIN1 BST2
Digital Logic VIN2 VREF2
VOUT1
Charge Pump
Detection
Boot-Low
BST-SW
VOUT2 VSNS_AVG2
Average Level
ADC VCC Error Shift
Temp
Amp.
ADC_OUT
/CS
SPI SW2
PVCC2
CK Interface
OTP
SI and Current Current
HS On
Registers Sense Hysteresis LS On
SO Control
PGND2
EN1 EN2 DIM1 DIM2 ISN2 ISP2
Figure 2: Functional Block Diagram

OPERATION
The MPQ7210 is a high-frequency, D is the required duty cycle. Typically, tON_MIN is
synchronous, rectified, switch-mode buck LED 125ns, and tOFF_MIN is 120ns.
driver with built-in power MOSFETs. It offers a
The MPQ7210 is compatible with shunt
very compact solution to achieve 2A of
MOSFET dimming and LED matrix manager
continuous output current (IOUT) with a dual-buck
devices. The fast dynamic response ensures
converter. The MPQ7210 provides excellent
near ideal current source behavior with minimal
load and line regulation across a 4.5V to 60V
IL overshoot or undershoot.
input voltage (VIN) supply range.
The device’s behavior is impacted by the ISN1
The MPQ7210’s two output channels can work
and ISN2 node’s falling slew rate. A faster falling
alone. If a channel is not used, pull its ENx and
slew rate and greater output capacitance pose
DIMx pin low, and float the following pins: SWx,
risks to the shut MOSFET. In these scenarios, a
ISPx, ISNx, and BSTx.
larger inductance and lower output capacitance
The two output channels can operate in parallel is strongly recommended. In theory, even
as one phase to support high-current without the output capacitor, the MPQ7210’s
applications via the one-time programmable loop should be stable, which makes it well-suited
(OTP) memory. A single- or dual-inductor can be for applications with a faster falling slew rate.
used for thermal consideration. In a single-phase
LED Current (ILED) Sense
configuration, float the EN2, DIM2, ISP2, and
ISN2 pins; meanwhile, the internal buck 1 and The external resistor (RSEN) connected between
buck 2 MOSFETs operate in parallel. the ISPx and ISNx pins sets the LED current
(ILED). ILED can be calculated with Equation (1):
For higher power, two (or more) MPQ7210
devices can operate in parallel. 0.2
ILED (A) = (1)
Fixed-Frequency Band-to-Band Control RSEN (Ω)
The MPQ7210 uses fixed-frequency band-to- If the MPQ7210 is configured for single-phase
band control. Compared to fixed-frequency operation, ILED can only set by the resistor
pulse-width modulation (PWM) control, band-to- between ISP1 and ISN1, and it can still be
band control offers the advantages of a simpler calculated with Equation (1).
control loop and faster transient response. Even
without the output capacitor, the loop is stable. Analog-to-Digital Converter (ADC)
The MPQ7210 incorporates a 10-bit successive
Band-to-band control compares the inductor approximation register (SAR) analog-to-digital
current (IL) to the internal thresholds: the peak
converter (ADC). The single ADC can be
(IBAND_PEAK) and the valley (IBAND_VALLEY). When IL
multiplexed to sample certain signals (see Table
exceeds IBAND_PEAK, the high-side MOSFET (HS-
1). The ADC can only sample one signal each
FET) turns off. When IL is below IBAND_VALLEY, the time. The ADC_INMUX bit value in Table 1
HS-FET turns on. (IBAND_PEAK + IBAND_VALLEY) / 2 is selects which signal is sampled.
controlled by a PID loop to regulate the LED
current (ILED) to the set value. Table 1: ADC Sample Information (Register 0x12)
IBAND_PEAK - IBAND_VALLEY is controlled by a phase- Selection Description

locked loop (PLL) to regulate the switching 000 CH1: buck 1 input = VIN1
frequency (fSW) to 420kHz or another frequency, 001 CH2: buck 1 output = VOUT1
as set by the relevant OTP register. 010 CH3: buck 2 input = VIN2
If the minimum on time (tON_MIN) or minimum off 011 CH4: buck 2 output = VOUT2
time (tOFF_MIN) are triggered, fSW is extended and 100 CH5: VCC voltage = VCC
the real fSW is (D / tON_MIN) or (D / tOFF_MIN), where 101 Part temperature: TJ
110/111 Not used

Register 0x12, bit D[4] can control when the ADC When IBAND_VALLEY = 0A, the MPQ7210 enters
starts sampling the data. To obtain the discontinuous current mode (DCM). The low-
information regarding VIN, VOUT, VCC, and TJ, side MOSFET (LS-FET) turns off once zero-
follow the steps below: current detection (ZCD) is triggered, then the LS-
FET acts as an ideal diode. At light loads, fSW
1. Write to register 0x12, bits D[2:0] to select
decreases, and the SWx pin may skip a pulse if
which signal to monitor.
the device enters DCM. This may make the
2. Read 0x12. If bits D[7:5] = bits D[2:0] and bit current ripple too high and make the current
D[4] = 1, then proceed to step 3; if not, return precision too low. Select a larger-value inductor
to step 1. so that the device can operate in CCM under any
3. Write register 0x12, bit D[3] = 1. condition.
4. Read register 0x13, bits D[9:0]. Enable (EN) Control

EN is a control pin that turns the regulator on and
When the sensed signal is VIN1, VIN2, VOUT1, or off. Drive EN above 1V to turn the regulator on;
VOUT2, the voltage is first divided by 32.125. (For drive EN below 0.85V to turn it off. EN can be
example, if VIN is 40V, it will become 1.245V.) connected to VCC through a resistor, but it
The new value is sent to the ADC input. The ADC cannot be connected directly to VIN through a
is 10 bits, and 1 LSB is 2mV (0b1001101111). resistor. In a dual-channel configuration, EN1 or
Register 0x13, bits D[7:0] (0b10011011 = 0h155) EN2 going low can only reset buck 1 or buck 2,
is updated based on the 8MSB of the ADC respectively. The analog circuit and register
conversion. The final 2LSB are ignored. The value cannot be reset. If both EN1 and EN2 pull
relationship between the sensed voltage and the low, the IC resets completely. In a single-channel
ADC_DATA[7:0] can be estimated with Equation configuration, only EN1 can reset the part.
(2): The MPQ7210 can be enabled or disabled by
VIN (V)=ADC_DATA[7:0]×0.257 (2) setting the BUCK_EN bit when ENx is high:
When the sensed signal is VCC, the voltage is • If the BUCK1/2_EN bit = 0, enable buck 1/2
divided by 4. (For example, if VCC is 5V, then it
• If the BUCK1/2_EN bit = 1, disable buck 1/2
becomes 1.25V.) The relationship between
VCC and ACC_DATA can be calculated with Only the EN pin can enable or disable the
Equation (3): MPQ7210. It is not recommended to use the DIM
pin to enable or disable the device, as the error
VCC (V)=ADC_DATA[7:0]×0.032 (3) amplifier’s output voltage (VCOMP) may be
When the sensed signal is TJ, the temperature discharged by the leakage if the dimming off time
information can be transferred to a voltage (VT), is too long.
estimated with Equation (4): Pulse-Width Modulation (PWM) Dimming
VT =1.05+0.004  TJ (4) The MPQ7210 can be configured to PWM
dimming mode with three different selections.
The relationship between TJ and ADC_DATA The PWM dimming on time should be longer
can be calculated with Equation (5): than 60µs, and the PWM dimming frequency
TJ =2  (ADC_DATA 7:0 -131.25) (5) should be between 100Hz and 2kHz. Ensure that
the dimming off time is no longer than 10ms.
Continuous Conduction Mode (CCM) and
1. PWM dimming mode 1: When pulling the
Discontinuous Conduction Mode (DCM)
DIM pin high, the device dims with a certain
The MPQ7210 uses continuous conduction PWM dimming frequency and duty cycle.
mode (CCM) to ensure that the part works with a The frequency and duty cycle can be
fixed frequency from a minimum load to a full- configured via the SPI. When the DIM pin
load range. The advantages of CCM are its pulls low, the MPQ7210 stops switching.
controllable frequency and lower output voltage Figure 3 on page 28 shows PWM dimming
ripple under light loads. mode 1.

DIM 200mV. The default analog dimming register

value is 0x00C8, which corresponds to a 200mV
VREF. VREF can be estimated with Equation (6):
tPWM_ON
ILED
VREF = 0x06, bits D[7:0] / 200 x 200mV (6)
tPWM
The minimum VREF is 10mV, and the maximum
VREF is 255mV.
Figure 3: PWM Dimming Mode 1
Under-Voltage Lockout (UVLO)
2. PWM dimming mode 2: When applying an
external 100Hz to 2kHz PWM signal to the Under-voltage lockout (UVLO) protects the chip
DIM pin, the MPQ7210 stops switching when from operating at an insufficient supply voltage.
the DIM voltage is below 1.15V and ILED is Both VIN and VCC have UVLO. VIN and VCC both
zero. The device resumes normal operation have a rising UVLO threshold of 4.2V with a 0.2V
with the nominal ILED when the DIM pin’s hysteresis. VIN and VCC UVLO do not trigger the
voltage exceeds 1.25V. The average ILED is /FS pin. There is no internal VCC regulator for
proportional to the PWM duty cycle. Figure 4 the MPQ7210, so it requires an additional 5V DC
shows PWM dimming mode 2. source to power VCC. Add a 1µF to 10µF
decoupling ceramic capacitor at the VCC pin.
DIM When the device starts up, VCC should turn on
tPWM_ON
first. Once VCC exceeds its UVLO threshold, the
ILED
internal logic builds up. Then power on VIN.
When shutting down, turn VIN off first, then
tPWM disable VCC to shut down the internal circuit.
Figure 4: PWM Dimming Mode 2 Faults Detection and Diagnostics
3. PWM dimming mode 3: The DIM pin is used The MPQ7210 has a fault indicator pin (/FS). /FS
as the input pin to select the LED current with is high at normal operation, but interruptions pull
a full current or a certain dimming duty cycle. this pin low to indicate a fault status for the
When the DIM pin’s voltage is high, the following: output under-voltage protection (UVP),
device works at a 100% dimming duty cycle; over-current protection (OCP), BST UV condition,
when this voltage is low, the works at X% TJ thermal warning (TW), and thermal shutdown
dimming duty cycle, where X is determined (TSD).
by the register setting. Figure 5 shows PWM
When the false interruption register mask is
dimming mode 3.
enabled, the /FS pin does not pull low, even if an
interruption occurs. The MPQ7210 has multiple
DIM
registers to indicate if an interruption occurs (see
tPWM_ON Figure 6).
ILED Register Bank
(User Read FAULT
Status)
tPWM INT_RAW_STATUS
(0x0B)
AD_INT (0x0E)
Figure 5: PWM Dimming Mode 3 EN_INT (0x0C)
D Q
INT_STATUS
(0x0A) /FS_STATUS
INT_STATUS1 /FS
CP (0x08)
INT_STATUS2
For PWM dimming mode 1 and PWM dimming
mode 3, the dimming frequency is determined by INT_MASK_EN
(0x0D)
INT_STATUSn
DEV_CFG, bits D[3:0] (125Hz, 250Hz, 500Hz,

DC/DC
and 1kHz) in register 0x03. The duty cycle is FAULT_ACT
(0x09)
determined by the dimming duty cycle on

Figure 6: Interruption Diagram
register 0x04 and 0x05, bits D[11:0].
AD_INT (UVP, OCP, TSD) indicates whether an
Analog Dimming
interrupt has actually occurred (see Figure 6).
ILED can also be set by the analog dimming
register through the SPI. The reference voltage
(VREF) can be adjusted to a maximum 125% of

Only when EN_INT (interruption enable) is The /FS pin can be cleared by writing 0xFFFF to
enabled, the INT_RAW_STATUS and analog register 0x0A when the interruption is removed.
circuit (DC/DC) react to the interruption. The user can read the INT_STATUS (0x0A)
INT_RAW_STATUS can be also masked by the register to check whether an interruption has
INT_MASK_EN register (mask is enable); then occurred. Table 2 shows the device’s behavior
INT_STATUS does not flag 1, and the /FS does under different fault conditions.
not pull low (see Figure 6 on page 28).
Table 2: Device Behavior under Fault Conditions
Protection Feature Protection Behavior
Once the below interruption is triggered, the related fault is flagged in register 0x0A.
Trigger condition: IL triggers the OC value in registers 0x10 and 0x11.
OCP prevents IL runaway, and it can also be used to limit ILED. Typically, the wrong
ILED setting, or the sensing resistor shifting low, can trigger OCP. When the OC
Inductor current over- condition is triggered, the related fault is flagged. If set to hiccup mode, the device
current protection (OCP) tries to recover every 16ms. If the OC condition remains, the inductor’s peak value
is limited to an OC value. If the OC condition is removed, the device recovers. OCP
can be set to latch-off or no action mode. See the Over-Current Protection (OCP)
section on page 30 for more details.
Trigger condition: VOUT drops below the UV threshold (typically 2.3V).
Output UVP monitors if there is an LED+ short to GND. The UV threshold is typically
2.3V. If the output is connected to a dimming switch, this feature should be disabled.
Output under-voltage If set to hiccup mode, the device tries to recover every 16ms. If the UV condition
protection (UVP) remains, the part works for 1ms to check if the UV condition is removed. If the UV
condition is removed, the part recovers. The protection can be set to latch-off or no
action mode. For more details, see the Under-Voltage Protection (UVP) section on
page 30.
Trigger condition: TJ exceeds the TW threshold (typically 125°C).
Thermal warning (TW) When the IC’s TJ exceeds 125°C. The related fault is flagged, and the device takes
no action. After TJ drops below 105°C, the fault flag can be cleared.
Trigger condition: TJ exceeds the TSD threshold (typically 170°C).
Thermal shutdown (TSD) If TJ exceeds 170°C, TSD is triggered. All output channels turn off for this protection.
When TJ drops to 150°C, the device recovers in hiccup mode. In latch-off mode, the
device must be reset by EN, VCC, or VIN UVLO.
Trigger condition: The BST-to-SW voltage drops below the UV threshold (typically
2.5V).
BST voltage under- This protection monitors the BST-to-SW voltage. If the BST voltage is below the
voltage lockout (UVLO) UVLO threshold (2.2V), UVLO is triggered. The device shuts down (no switching,
VOUT drops to 0V). The device recovers switching when the BST voltage exceeds
the 2.5V rising threshold.
One-time programmable
Each time the device starts up, the part will self-check if there is an OTP error. If
(OTP) memory indicator
there is an OTP error, the part stays in an idle status.
failure protection
OTP program failure Checks if the OTP program is successful when the device undergoes OTP in the
protection factory. This bit can be covered by OTP indicator protection.
After the OTP indicator check finishes, the device checks the OTP data’s CRC. If
OTP cyclic redundancy
there is any wrong data, the CRC value is different, the CRC error is flagged, and
check (CRC) failure
the device maintains an idle status. Both OTP indicator and OTP CRC failures force
protection
the device to an idle state with no switching.
Once the below interruption is triggered, no fault register is flagged.
VIN UVLO The device shuts down and stops switching.
VCC UVLO The device shuts down and stops switching.
Minimum off time is The device enters dropout mode, and the frequency folds back to low gradually
triggered while VIN drops. ILED cannot stay at the set value in deep dropout mode.

Over-Current Protection (OCP) is triggered, the device can be set to no action,

The MPQ7210 has cycle-by-cycle peak current- hiccup, or latch-off mode:
limit protection. IL is monitored while the HS-FET • No action: The device continues switching
is on. If IL exceeds the current-limit value, the and the inductor’s average current stays at
HS-FET turns off immediately. Then the LS-FET the set current. If the minimum on time is
turns on to discharge the energy, and IL triggered, the frequency drops.
decreases. The HS-FET remains off unless IL
drops to zero, and then another HS-FET on cycle • Hiccup mode: The device tries to recover
starts. OCP can disabled or enabled with three every 16ms; if the UV condition is removed,
choices when an OC condition is triggered. If the device recovers.
OCP is enabled and an OC condition is triggered, • Latch-off mode: The device latches off and
the device can be set to no action, latch-off, or stops switching the UV condition is triggered;
hiccup mode: the device does not recover even if the UV
• No action: The device continues switching, interruption is removed and the /FS register
but the current is limited to the set OC value. is cleared.
• Hiccup mode: The device tries to recover UVP protects from LED+ short to LED-, but if the
every 16ms; if the OC condition remains, the MPQ7210 is used to power shunt FET dimming
inductor’s peak value is limited to the set OC and LED matrix manager devices, all the
value. If the OC condition is removed, the dimming switches may turn on at the same time.
device recovers. In this scenario, VOUT may be discharged to 0V,
which triggers UVP. UVP should be disabled for
• Latch-off mode: The device latches off and these applications.
stops switching, even the OC condition is
removed. The device does not recover even If the dimming duty cycle is set to 0% for a long
if the OC condition is removed. time during normal PWM dimming conditions,
VOUT is discharged to 0V. This may also trigger
The OC value can be set via the OTP or adjusted UVP. Disable UVP before setting the PWM
through the SPI via register 0x11, bits[5:4] (for dimming duty cycle to 0%. For these applications,
buck 1) and 0x11, bits[2:0] (for buck 2). Select the LED+ short to LED- condition can be
the OC behavior and OC limit based on the monitored by reading VOUT through the ADC.
specifications. The OC limit should be 50%
greater than the maximum ILED. Thermal Warning (TW)
If TJ exceeds 125°C, the STATUS_TWN bit
Table 3: OC Value Selection
asserts and the /FS pin pulls low, while the IC
Register Register continues working. When the thermal warning
OC Limit OC Limit
Selection Selection condition is removed (20°C hysteresis), /FS
000 500mA 100 2.5A stays low and the /FS bit remains flagged at
001 1A 101 3A 1until it has been cleared by the MCU.
010 1.5A 110 3.5A
The thermal warning interrupt can be individually
011 2A 111 4A masked via TWN_INT_MASK_EN to prevent the
Set the OC response based on the application /FS open-drain output from pulling low. Even if
requirements. If OCP is disabled or the device is the thermal warning condition is masked, the
set to no action, conduct a thorough validation at thermal warning status can still be read via the
the system level. /FS_REAL_TIME_STATUS register.
Under-Voltage Protection (UVP) Thermal Shutdown (TSD)
The MPQ7210 provides output UVP by If TJ continues to rise, thermal shutdown
monitoring the ISNx pin’s voltage. If the ISNx prevents the chip from operating at exceedingly
pin’s voltage drops below the UVP threshold high temperatures.
(typically 2.3V), UVP is detected. UVP can be
enabled or disabled with three potential
responses. If UVP is enabled and a UV condition

When the die temperature exceeds 170°C, all Serial Peripheral Interface (SPI)
output channels turn off for protection, the The MPQ7210 features a four-wire SPI with a
STATUS_TSD bit is set, and the /FS pin asserts. clock speed up to 4MHz. Ensure that the MCU
When the IC recovers from thermal shutdown, and the MPQ7210 are on the same board, with
the /FS pin stays low and the /FS bit is flagged a line that is as short as possible.
to 1 until it is cleared by the MCU.
The interface is a four-wire SPI with SPI mode 3
Thermal protection can be configured to latch-off (CPOL = CPHA = 1, the clock is idle high, sample
or hiccup mode. If set to hiccup mode, the device data at the clock’s first rising edge).
recovers and turns on the channels when the
temperature drops by at least 20°C. The For standard SPI configurations, the /CS (chip
channels return to their previous settings without select, active low), CK (sync clock), SI (MOSI,
needing to be reinitialized. If set to latch-off mode, serial data input), and SO (MISO, serial data
the device latches off when the die temperature output) pins are used. The communication starts
exceeds 170°C. Only VCC, EN, or VIN UVLO can when /CS is pulled low by the SPI master and
reset the latch. stops when the /CS pin pulls high. CK is also
controlled by the SPI master. SI and SO are
Floating Driver and Bootstrap Charging driven at the falling edge of CK and should be
An external bootstrap capacitor powers the captured at the rising edge of CK. The /CS pin
floating power MOSFET driver. The bootstrap stays low while sending data.
capacitor voltage is charged to 5V from VCC
The clock must be within the specified frequency
through a pass transistor when the LS-FET is on.
range (≤4MHz).
This floating driver has its own UVLO protection,
with a rising threshold of 2.5V and a hysteresis Command and data are shifted with the least
of 700mV. significant bit (LSB) first, and the most significant
bit (MSB) last.
When the BST-to-SW voltage drops to 2.2V, the
LS-FET is forced on to refresh the BST voltage. The SPI does not support back-to-back frame
The recommended bootstrap capacitor is a operation. After each SPI transfer, the /CS pin
ceramic capacitor between 47nF and 220nF. must go from low to high to low before the next
The actual capacitor's capacitance has a SPI frame transfer starts. The minimum time
derating that changes at different DC voltages between two SPI commands is one SPI clock
and temperatures. Take this derating into cycle during which the /CS pin must remain high.
account when choosing the capacitor to ensure Bit Encoding of the Command Byte
that the actual capacitance is between 47nF and
200nF. A maximum 22Ω resistor can be placed The first byte (command byte) transmitted at SI
in series with the bootstrap capacitor to reduce after /CS goes low contains address and
the SW pin’s spike voltage. command information. Table 2 shows the
command byte arrangement. Bits[7:0] are the
If BST UVP is triggered, the target register address, while bit[0] is command
BSTOK_INT_STATUS bit asserts and the /FS mode (two supported modes, where 0 is a single
pin pulls low if BST protection is enabled. write and 1 is a single read).
Figure 7 on page 32 shows the SPI signal frame
write/read.
Table 2: Command Byte

D7 D6 D5 D4 D3 D2 D1 D0
ADDR CMD

/CS
CK
SI ADDR CMD Write DATA to ADDR [LSB, MSB]
SI Bit 6 5 4 3 2 1 0 0 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
SO IDLE Read DATA from ADDR [LSB, MSB]
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
SO bit
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Figure 7: SPI Signal Frame Write/Read
Figure 8 shows the SPI frame signal write/read. The read frame description is below:
The write frame description is below:
• SI: Received master [CMD (ADDR+CMD)].
• SI: Received master {CMD (ADDR+CMD), • SO: Transmit slave {R_data [L], R_data
W_data [L], W_data [H]}. [H]}.
• SO: Stay idle.
/CS
SPI Write CK
SI Addr[n]+W New BL[n] New BH[n]
SO IDLE IDLE IDLE
/CS
CK
SPI Read
SI Addr[n]+R IDLE IDLE
SO IDLE BL[n] BH[n]
Figure 8: SPI Frame Signal Write/Read

REGISTER MAP
Register
R/W Addr. Def D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name
SIL_INF R/W 0x01 0000 OTP RSV SIL_INF
DEV_CFG R/W 0x03 005A RSV PHASE DIM1_MODE DIM2_MODE DIM1_FREQ DIM2_FREQ
PWM_DIM
R/W 0x04 0000 RSV PWM_DIM1_DUTY
1
PWM_DIM
R/W 0x05 0000 RSV PWM_DIM2_DUTY
2
ANA_DIM1 R/W 0x06 00C8 RSV ANA_DIM1
ANA_DIM2 R/W 0x07 00C8 RSV ANA_DIM2
INT
_ST
INT_ALL R 0x08 0000 RSV
ATU
S
BUCK1_OCP_ BUCK2_OCP_ BUCK1_UVP_A BUCK2_UVP_A
/FS_CFG R/W 0x09 5551 RSV RSV RSV TSD_ACT
ACT ACT CT CT
OTP OTP
BUC BUC BUC BUC OTP_
PHA BST1 BST2 _IND _PR
K1_ K1_U K2_ K2_U TWN TSD_ CRC_
SE_I _UV_ _UV_ _FAI OG_
/FS_INT_S R/W OCP VP_I OCP VP_I _INT INT_ FAIL_
0x0A 0000 RSV RSV NT_ INT_ INT_ L_IN FAIL RSV
TATUS 1C _INT NT_ _INT NT_ _STA STAT INT_
STA STA STA T_ST _INT
_STA STA _STA STA TUS US STAT
TUS TUS TUS ATU _STA
TUS TUS TUS TUS US
S TUS
OTP
BUC BUC OTP
BUC BUC _PR OTP_
K1_ K2_ PHA TWN BST1 BST2 _IND
K1_U K2_U TSD_ OG_ CRC_
OCP OCP SE_I _INT _UV_ _UV_ _FAI
/FS_INT_R VP_I VP_I INT_ FAIL FAIL_
_INT _INT NT_ _RA INT_ INT_ L_IN
AW_STAT R 0x0B 0000 RSV NT_ RSV NT_ RAW _INT INT_ RSV
_RA _RA RAW W_S RAW RAW T_RA
US RAW RAW _STA _RA RAW
W_S W_S _STA TAT _STA _STA W_S
_STA _STA TUS W_S _STA
TAT TAT TUS US TUS TUS TAT
TUS TUS TAT TUS
US US US
US
OTP
BUC BUC BUC BUC PHA BST1 BST2 OTP OTP_
TWN _PR
/FS_INT_E K1_ K1_U K2_ K2_U SE_I TSD_ _UV_ _UV_ _IND CRC_
R/W 0x0C 93FC RSV RSV _INT OG_ RSV
N OCP VP_ OCP VP_ NT_ EN INT_ INT_ _FAI FAIL_
_EN FAIL
_EN EN _EN EN EN EN EN L_EN EN
_EN
OTP
BUC BUC BUC BUC OTP
PHA BST1 BST2 _PR OTP_
K1_ K1_U K2_ K2_U TWN TSD_ _IND
SE_I _UV_ _UV_ OG_ CRC_
OCP VP_I OCP VP_I _INT INT_ _FAI
/FS_INT_ NT_ INT_ INT_ FAIL FAIL_
R/W 0x0D 0000 _INT RSV NT_ _INT RSV NT_ _MA MAS L_IN RSV
MASK_EN MAS MAS MAS _INT INT_
_MA MAS _MA MAS SK_ K_E T_M
K_E K_E K_E _MA MAS
SK_ K_E SK_ K_E EN N ASK_
N N N SK_ K_EN
EN N EN N EN
EN
/FS_INT__ STA STA STA STA STA STA
REAL_TIM TUS TUS TUS TUS TUS TUS
R 0x0E 0000 RSV RSV RSV
E_STATU _OC _UV _OC _UV _TW _TS
S P1 P1 P2 P2 N D
BUC
BUCK1_C BUCK1_FREQ_ K1_F
R 0x10 001E RSV BUCK1_OCP_SEL
FG SEL SS_
EN
BUC
BUCK2_C BUCK2_FREQ_ K2_F
R 0x11 001E RSV BUCK2_OCP_SEL
FG SEL SS_
EN
TRIG
ADC GER
ADC_CTR
R/W 0x12 0000 RSV CUR_STORED_CH _RE _AD ADC_INMUX
L
ADY C_R
EAD
ADC_OUT R 0x13 0000 RSV ADC_DATA
USE
TRIM
OTP R_P
_PA
DA_ _CR AGE
GE_
BUCK_ST OTP C_E _CR
R 0x15 0000 RSV CRC RSV
ATUS _RD RR_ C_E
_ER
Y FLA RR_
R_FL
G FLA
AG
G
BUC BUC
BUCK_EN R/W 0x20 0x00 RSV K1_E K1_E
N N

REGISTER DESCRIPTION
SIL_REV (0x01)
Default: 0x0000
POR: N/A
The SIL_REV command indicates whether OTP is complete, provides readout data, and returns the
silicon information.
Bits Access Bit Name Default Description
D15 R OTP 0 When the device finishes OTP, this bit is set to 1.
D[14:8] R RESERVED 0 Reserved. Always read as 0.
D[7:0] R SIL_INF 0 Returns the silicon revision information.
DEV_CFG (0x03)
Default: 0x005A
POR: Load from the OTP
The DEV_CFG command configures the part phase, PWM dimming mode, PWM dimming frequency.
Selects the phase (dual-phase or single-phase). Read-only after
loading the OTP. If the part is set to 01 or 10 via the OTP, the part
does not operate.
D[9:8] R PHASE 0
00: Dual-phase
01, 10: Error
11: Single-phase
Configures buck 1’s dimming mode. See the Pulse-Width
Modulation (PWM) Dimming section on page 27 for more details.
D[7:6] R/W DIM1_MODE 01 00: PWM dimming mode 1
01: PWM dimming mode 3
10, 11: PWM dimming mode 2, follow the DIM pin
Configures buck 2’s dimming mode. See the Pulse-Width
Modulation (PWM) Dimming section on page 27 for more details.
D[5:4] R/W DIM2_MODE 01 00: PWM dimming mode 1
01: PWM dimming mode 3
10, 11: PWM dimming mode 2, follow the DIM pin
Configures buck 1’s dimming frequency.
00: 125Hz
D[3:2] R/W DIM1_FREQ 10 01: 250Hz
10: 500Hz
11: 1kHz
Configures buck 2’s dimming frequency.
00: 125Hz
D[1:0] R/W DIM2_FREQ 10 01: 250Hz
10: 500Hz
11: 1kHz

PWM_DIM1 (0x04)
Default: 0x0000
The PWM_DIM command configures buck 1’s PWM dimming duty cycle.
Configures buck 1’s PWM dimming duty cycle. The duty cycle is
(x / 4095), where x is the register value, which can be set between
D[11:0] R/W DIM1_DUTY 0
0 and 0xFFF via the OTP in the factory, or it can be changed on
the fly via the SPI.
PWM_DIM2 (0x05)
Default: 0x0000
The PWM_DIM1 command configures buck 2’s PWM dimming duty cycle.
Configures buck 2’s PWM dimming duty cycle. The duty cycle is
(x / 4095), where x is is the register value, which can be set
D[11:0] R/W DIM2_DUTY 0
between 0 and 0xFFF via the OTP in the factory, or it can be
changed on the fly via the SPI.
ANA_DIM1 (0x06)
Default: 0x00C8
The ANA_DIM1 command configures buck 1’s analog dimming reference voltage.
Configures buck 1’s analog dimming setting. When the 0x06
register is set to 0xC8, the reference voltage is 0.2V. The voltage
on the sensing resistor is (N / 200 x 200mV), where N is the
D[7:0] R/W ANA_DIM1 0xC8
register value, which can be set between 0 and 255 via the OTP
in the factory, or changed on the fly via the SPI. The minimum
voltage is 10mV.
ANA_DIM2 (0x07)
Default: 0x00C8
The ANA_DIM2 command configures the part buck 2 analog dimming reference voltage.
Configures buck 2’s analog dimming setting. When the 0x07
register is set to 0xC8, the reference voltage is 0.2V. The voltage
on the sensing resistor is (N / 200 x 200mV), where N is the
D[7:0] R/W ANA_DIM2 0xC8
register value, which can be set between 0 and 255 via the OTP
in the factory, or changed on the fly via the SPI. The minimum
voltage is 10mV.

INT_ALL (0x08)
Default: 0x0000
POR: N/A
The INT_ALL command indicates the device’s interruption status. If any interruption is triggered, bit[0]
flags 1.
Indicates the /FS interruption status.
D0 R INT_STATUS 0 0: No interruption events; /FS is high
1: There are interruption events; /FS is low
INT_CFG (0x09)
Default: 0x5551
POR: N/A
The INT_CFG command configures the device’s action for IL over-current protection (OCP), VOUT under-
voltage protection (UVP), and thermal shutdown (TSD). Typically, the device can be configured for no
action, hiccup, and latch-off mode.
Sets buck 1’s OCP response.
D[15:14] R/W BUCK1_OCP_ACT 01 00: Latch-off mode

01: Hiccup mode
10, 11: No action
Sets buck 2’s OCP response.
D[13:12] R/W BUCK2_OCP_ACT 01 00: Latch-off mode

01: Hiccup mode
10, 11: No action
Sets buck 1’s VOUT UVP response.
D[11:10] R/W BUCK1_UVP_ACT 01 00: Latch-off mode

01: Hiccup mode
10, 11: No action
Sets buck 2’s VOUT UVP response.
D[9:8] R/W BUCK2_UVP_ACT 01 00: Latch-off mode

01: Hiccup mode
10, 11: No action
D[7:6] R/W RESERVED 01 Reserved. Always read as 01.
D[5:4] R/W RESERVED 01 Reserved. Always read as 01.
Sets the thermal shutdown response.
D[1:0] R/W TSD 01 00: Latch-off mode

01: Hiccup mode
10, 11: No action

/FS_INT_STATUS (0x0A)
Default: 0x0000
POR: N/A
The /FS_INT_STATUS command indicates if the following occur: over-current protection (OCP), under-
voltage protection (UVP), thermal warning (TW), thermal shutdown (TSD), BST UV, and one-time
programmable (OTP) error interruption. If any interruption occurs, an /FS interruption status register flag
is set to 1 and the /FS pin pulls low if the interruption mask is disabled. When writing 1 to this register,
the interruption flag is cleared after the interruption condition is removed. The user can read this register
to obtain the information if there is an interruption.
BUCK1_OCP_INT_
D[15] R/W1C 0 Indicates buck 1’s OCP interruption status.
STATUS
D[14] R RESERVED 0 Reserved. Always read as 0.
BUCK1_UVP_INT_
D[13] R/W1C 0 Indicates buck 1’s output UVP interruption status.
STATUS
BUCK2_OCP_INT_
D[12] R/W1C 0 Indicates buck 2’s OCP interruption status.
STATUS
BUCK2_UVP_INT_
D[10] R/W1C 0 Indicates buck 2’s output UVP interruption status.
STATUS
D[9] R/W1C PHASE_INT_STATUS 0 Indicates the phase control’s safety error interruption status.
D[8] R/W1C TWN_INT_STATUS 0 Indicates the TW interruption status.
D[7] R/W1C TSD_INT_STATUS 0 Indicates the TSD interruption status.
BST1_UV_INT_ Indicates the interrupt status for whether buck 1’s boot voltage
D[6] R/W1C 0
STATUS is okay.
BST2_UV_INT_ Indicates the interrupt status for whether buck 2’s boot voltage
D[5] R/W1C 0
STATUS is okay.
OTP_IND_FAIL_INT_
D[4] R/W1C 0 Indicates an OTP failure interruption status.
STATUS
OTP_PROG_FAIL_
D[3] R/W1C 0 Indicates an OTP failure after the OTP is programmed.
INT_STATUS
OTP_CRC_FAIL_
D[2] R/W1C 0 Indicates the OTP CRC failure interruption status.
INT_STATUS
D[1:0] RSV RESERVED 0 Reserved. Always read as 0.
/FS_INT_RAW_STATUS (0x0B)
Default: 0x0000
POR: N/A
The /FS_INT_RAW_STATUS command indicates if an error interruption occurs if any of the following
interrupts are enabled: over-current protection (OCP), under-voltage protection (UVP), thermal warning
(TW), thermal shutdown (TSD), BST UV, and one-time programmable (OTP) error. If any interruption
occurs, the related register bit is flagged as 1. The related interruption bit is flagged only if the related
interruption is enabled.
BUCK1_OCP_INT_
D[15] R 0 Indicates buck 1’s OCP interruption raw status.
RAW_STATUS
BUCK1_UVP_INT_
D[13] R 0 Indicates buck 1’s output UVP interruption raw status.
RAW_STATUS

BUCK2_OCP_INT_
D[12] R 0 Indicates buck 2’s OCP interruption raw status.
RAW_STATUS
BUCK2_UVP_INT_
D[10] R 0 Indicates buck 2’s output UVP interruption raw status.
RAW_STATUS
PHASE_INT_RAW_
D[9] R 0 Indicates the phase control’s safety error interruption raw status.
STATUS
TWN_INT_RAW_
D[8] R 0 Indicates the TW interruption raw status.
STATUS
TSD_INT_RAW_
D[7] R 0 Indicates the TSD interruption raw status.
STATUS
BST1_UV_INT_RAW_
D[6] R 0 Indicates buck 1’s BST UV interruption raw status.
STATUS
BST2_UV_INT_RAW_
D[5] R 0 Indicates buck 2’s BST UV interruption raw status.
STATUS
OTP_IND_FAIL_INT_
D[4] R 0 Indicates an OTP failure interruption raw status.
RAW_STATUS
OTP_PROG_FAIL_
D[3] R 0 Indicates an OTP failure after the OTP is programmed.
INT_RAW_STATUS
OTP_CRC_FAIL_
D[2] R 0 Indicates the OTP CRC failure interruption raw status.
INT_RAW_STATUS
/FS_INT_EN (0x0C)
Default: 0x93FC
The /FS_INT_EN command enables the following interruptions: over-current protection (OCP), under-
voltage protection (UVP), thermal warning (TW), thermal shutdown (TSD), BST UV, and one-time
programmable (OTP) error. If the related protection is enable, the part will act as the INT_CFG
configuration.
0: Disable buck 1 OCP
D[15] R/W BUCK1_OCP_EN 1
1: Enable buck 1 OCP
0: Disable buck 1 output UVP
D[13] R/W BUCK1_UVP_EN 0
1: Enable buck 1 output UVP
0: Disable buck 2 OCP
D[12] R/W BUCK2_OCP_EN 1
1: Enable buck 2 OCP
D[11] R/W RESERVED 0 Reserved. Always read as 0.
0: Disable buck 2 output UVP
D[10] R/W BUCK2_UVP_EN 0
1: Enable buck 2 output UVP
0: Disable the phase control safety error
D[9] R/W PHASE_EN 1
1: Enable the phase control safety error
0: Disable the TW interruption
D[8] R/W TWN_EN 1
1: Enable the TW interruption
0: Disable TSD interruption
D[7] R/W TSD_EN 1
1: Enable TSD interruption
0: Disable buck 1’s BST UV interruption
D[6] R/W BST1_UV_EN 1
1: Enable buck 1’s BST UV interruption
0: Disable buck 2’s BST UV interruption
D[5] R/W BST2_UV_EN 1
1: Enable buck 2’s BST UV interruption

0: Turn off the OTP indicator interruption status

D[4] R/W OTP_IND_FAIL_EN 1
1: Turn on the OTP indicator interruption status
0: Turn off the OTP program failure interruption status
D[3] R/W OTP_PROG_FAIL_EN 1
1: Turn off the OTP program failure interruption status
0: Turn off the OTP CRC failure interruption status
D[2] R/W OTP_CRC_FAIL_EN 1
1: Turn on the OTP CRC failure interruption status
/FS_INT_MASK_EN (0x0D)
Default: 0x0000
The /FS_INT_MASK_EN command masks the following interruptions: over-current protection (OCP),
under-voltage protection (UVP), thermal warning (TW), thermal shutdown (TSD), BST UV, and one-time
programmable (OTP) error. If the related interruption fault flag mask is enabled, the fault register flag is
not set to 1, even if the interruption is triggered. This register can only be configured via the SPI on the fly; it
cannot be configured via the OTP.
BUCK1_OCP_INT_ 0: Disable buck 1’s OCP interruption mask
D[15] R/W 0
MASK_EN 1: Enable buck 1’s OCP interruption mask
BUCK1_UVP_INT_ 0: Disable buck 1’s UV interruption mask

D[13] R/W 0
MASK_EN 1: Enable buck 1’s UV interruption mask
BUCK2_OCP_INT_ 0: Disable buck 2’s OCP interruption mask
D[12] R/W 0
MASK_EN 1: Enable buck 2’s OCP interruption mask
D[11] R/W RESERVED 0 Reserved. Always read as 0.
BUCK2_UVP_INT_ 0: Disable buck 2’s UV interruption mask
D[10] R/W 0
MASK_EN 1: Enable buck 2’s UV interruption mask
PHASE_INT_MASK_E 0: Disable the phase control safety error interruption mask
D[9] R/W 0
N 1: Enable the phase control safety error interruption mask
0: Disable the TW interruption mask
D[8] R/W TW_INT_MASK_EN 0
1: Enable the TW interruption mask
0: Disable the TSD interruption mask
D[7] R/W TSD_INT_MASK_EN 0
1: Enable the TSD interruption mask
BST1_UV_INT_ 0: Disable buck 1’s BST UV interruption mask
D[6] R/W 0
MASK_EN 1: Enable buck 1’s BST UV interruption mask
BST2_UV_INT_ 0: Disable buck 2’s BST UV interruption mask
D[5] R/W 0
MASK_EN 1: Enable buck 2’s BST UV interruption mask
0: Disable the OTP indicator interruption mask
D[4] R/W OTP_IND_FAIL_EN 0
1: Enable the OTP indicator interruption mask
OTP_PROG_FAIL_ 0: Disable the OTP program failure interruption mask
D[3] R/W 0
INT_MASK_EN 1: Enable the OTP program failure interruption mask
OTP_CRC_FAIL_INT_ 0: Disable the OTP CRC failure interruption mask
D[2] R/W 0
MASK_EN 1: Enable the OTP CRC failure interruption mask

/FS_INT_REAL_TIME_STATUS (0x0E)
Default: 0x0000
POR: N/A
The /FS_REAL_TIME_STATUS command indicates the real-time status of the following interrupts: over-
current protection (OCP), under-voltage protection (UVP), thermal warning (TW), and thermal shutdown
(TSD). If the interrupt condition is removed, the related bit returns to 0.
BUCK1_OCP_
D[15] R 0 Indicates buck 1’s live OCP status.
STATUS
BUCK1_UVP_
D[13] R 0 Indicates buck 1’s live output UV status.
STATUS
BUCK2_OCP_
D[12] R 0 Indicates buck 2’s live OCP status.
STATUS
BUCK2_UVP_
D[10] R 0 Indicates buck 2’s live output UV status.
STATUS
D[9] R TW_STATUS 0 Indicates the real-time TW status.
D[8] R TSD_STATUS 0 Indicates the real-time TSD status.
BUCK1_CFG (0x10)
Default: 0x001E
The BUCK1_CFG command configures buck 1’s switching frequency, frequency spread spectrum (FSS),
and high-side (HS) current limit. The switching frequency and FSS can only be configured via the OTP.
The current limit can be configured via the OTP in the factory or via the SPI on the fly. The current limit
prevents current runaway, and it can limit the current through the LED.
Sets buck 1’s switching frequency selection. Read-only after the
OTP finishes loading.
D[5:4] R BUCK1_FREQ_SEL 01 00: 220kHz

01: 420kHz
10: 1.1MHz
11: 2.3MHz
Enables FSS. Read-only after the OTP finishes loading.
D[3] R BUCK1_FSS_EN 1 0: Disabled
1: Enabled
Sets the HS current limit.
000: 500mA
001: 1A
010: 1.5A
D[2:0] R BUCK1_OCP_SEL 110 011: 2A
100: 2.5A
101: 3A
110: 3.5A
111: 4A

BUCK2_CFG (0x11)
Default: 0x001E
The BUCK2_CFG command configures the buck 2 switching frequency, frequency spread spectrum
(FSS), and high-side (HS) current limit. The switching frequency and FSS can only be configured via the
OTP. The current limit can be configured via the OTP in the factory or via the SPI on the fly. The current
limit prevents current runaway, and it can limit the current through the LED.
Sets buck 2’s switching frequency selection. Read-only after the
OTP finishes loading.
D[5:4] R BUCK2_FREQ_SEL 01 00: 220kHz

01: 420kHz
10: 1.1MHz
11: 2.3MHz
Enables FSS. Read-only after the OTP finishes loading.
D[3] R BUCK2_FSS_EN 1 0: Disabled
1: Enabled
Sets the HS current limit.
000:500mA
001: 1A
010: 1.5A
D[2:0] R BUCK2_OCP_SEL 110 011: 2A
100: 2.5A
101: 3A
110: 3.5A
111: 4A
ADC_CTRL (0x12)
Default: 0x0000
The ADC_CTRL command configures the ADC-related information. CUR_STORED_CH records the
current-sensing channel information and ADC_READY indicates whether the ADC is idle.
TRIG_ADC_READ triggers the ADC reading signal. ADC_INMUX selects which signal the ADC will read.
The ADC can read one channel at a time and the reading process is triggered by writing 1 to
TRIG_ADC_READ.
Bit Access Bit Name Default Description
Records the current stored in the ADC-sensing channel to check
what software is set for the ADC-sensing channel. ADC_INMUX
selects which signal the ADC reads.
000: CH1, buck 1 input :VIN1
D[7:5] R CUR_STORED_CH 0 001: CH2, buck 1 output: VOUT1
011: CH4, buck 2 output: VOUT2
100: CH5, VCC voltage: VCC
101: Part temperature: TJ
110, 111: Not used

Returns the ADC ready signal.
D[4] R ADC_READY 0 1: The ADC is ready to be triggered to read new values, or the
readout value from the ADC is available
0: The ADC is busy
Triggers the ADC to start reading. This bit automatically returns
D[3] R/W TRIG_ADC_READ 0 to 0 when reading is finished. Write 1 to this bit to start ADC
reading.
Selects which signal the ADC reads.
D[2:0] R/W ADC_INMUX 000 010: CH3, buck 2 input :VIN2
100: CH5, VCC voltage: VCC
101: Part temperature: TJ
110, 111: Not used
ADC_DATA (0x13)
Default: 0x0000
POR: N/A
The ADC_DATA command stores the ADC readout data. The ADC_DATA is refreshed once another
command from register 0x12, bit D[3] (TRIG_ADC_READ) write 1 is finished.
D[9:0] R ADC_DATA 0 Returns the 10-bit ADC data.
OTP_STATUS (0x15)
Default: 0x0000
POR: N/A
The OTP_STATUS command stores the device’s OTP information.
D[15] RSV RESERVED 0 Reserved. Always read as 0.
1: OTP reading to digital is complete
D[14] R DA_OTP_RDY 0
0: OTP reading to digital is not complete
Indicates the OTP CRC result.
OTP_CRC_ERR_
D[13] R 0 1: OTP CRC error
FLAG
0: No OTP CRC error
Indicates the OTP CRC result of a trimmed page.
TRIM_PAGE_CRC_
D[12] R 0 1: There is a trimmed page OTP CRC error
ERR_FLAG
0: There is no trimmed page OTP CRC error
Indicates the user page OTP CRC result.
USER_PAGE_CRC_
D[11] R 0 1: OTP CRC error
ERR_FLAG
0: No OTP CRC error

BUCK_EN (0x20)
Default: 0x0000
The BUCK_EN command controls buck 1 and buck 2’s on/off information.
Enables buck 1.
D[7] R/W BUCK1_EN 0 0: Enabled
1: Disabled
Enables buck 2.
D[3] R/W BUCK2_EN 0 0: Enabled
1: Disabled

APPLICATION INFORMATION
Setting the LED Current Choose the inductor ripple current to be 10% to
The external resistor connected between the 30% of the LED current. The inductor peak
ISPx and ISNx pins sets ILED. Select the sensing current can be calculated with Equation (8):
resistor package based on the power dissipation. ΔIL
ILED can be estimated with Equation (6): IL_PEAK = IL_AVG + (8)
2
0.2 Where IL_AVG is the average current through the
ILED (A) = (6)
RSEN (Ω) inductor. IL_AVG is equal to the output load current
(ILED) for buck applications. Under low-ILED
VREF (0.2V) can also be adjusted via the SPI by conditions, use a larger-value inductor to prevent
changing the analog dimming register 0x06, the part from entering DCM.
bits[7:0], which means VREF can be adjusted from
10mV to 255mV. Selecting the Input Capacitor
The step-down converter has a discontinuous
Dimming Mode Selection
input current in buck or buck-boost mode, and
The dimming mode can be configured via requires a capacitor to supply AC current to the
register 0x03. There are three dimming modes; converter while maintaining the DC input voltage.
for more details, see the Pulse-Width Modulation For the best performance, use low-ESR
(PWM) Dimming section on page 27. The capacitors. Ceramic capacitors with X7R
dimming mode should work with DIM pin to dielectrics are highly recommended because of
initialize the IC. their low ESR and small temperature
For example, if the PWM dimming mode is set to coefficients.
PWM dimming mode 3, pull the DIM pin low and For most applications, use a 4.7µF to 22µF
set the internal PWM dimming duty cycle to 0%. capacitor. The input capacitor can be electrolytic,
After VIN, VCC, and EN pull high, the initial tantalum, or ceramic. When using electrolytic or
current is 0A; the current can be changed via the tantalum capacitors, it is strongly recommended
SPI’s analog dimming and PWM dimming to use another lower-value capacitor (e.g. 0.1µF)
registers. with a small package size (0603) to absorb high-
Selecting the Switching Frequency (fSW) frequency switching noise. Place the smaller
capacitor as close as possible to VIN and GND.
fSW can be set to 220kHz, 420kHz, 1.1MHz, or
2.3MHz via the OTP. A higher fSW can reduce the In buck mode, since the input capacitor (CIN)
inductance and capacitance, but it increases absorbs the input switching current, it requires
power loss and may result in thermal issues. an adequate ripple current rating. The RMS
High-frequency operation is recommended for current in the input capacitor can be estimated
applications with a low LED current. The thermal with Equation (9):
and cooling conditions should be validated on a
VOUT V
system level. ICIN = ILOAD   (1 − OUT ) (9)
VIN VIN
Selecting the Inductor
For most applications, use an inductor with an The worst-case condition occurs at VIN = 2 x
inductance between 2.2µH and 330µH and a DC VOUT, calculated with Equation (10):
current rating higher than the maximum inductor ILOAD
ICIN = (10)
current. Include the inductor’s DC resistance 2
when estimating the output current and the
inductor’s power consumption. For simplification, choose an input capacitor with
an RMS current rating greater than half of the
For buck converter designs, calculate the maximum load current.
required inductance with Equation (7):
VOUT  (VIN − VOUT )
L= (7)
VIN  IL  fSW

The input voltage ripple caused by the falling threshold (typically 4V). The bypass
capacitance can be estimated with Equation capacitor from VCC to GND must have a
(11): capacitance 10 times greater than the bootstrap
capacitance (CBST) to support proper operation
ILOAD V V
VIN =  OUT  (1 − OUT ) (11) during PWM dimming. When choosing the VCC
fSW  CIN VIN VIN capacitor, select a capacitor between 1µF and
10µF. For most applications, use a 4.7µF/10V,
Selecting the Output Capacitor
X7R capacitor. A low-dropout (LDO) regulator
The output capacitor maintains the DC output with >10mA current ability is required to power
voltage. Ceramic, tantalum, or low-ESR VCC.
electrolytic capacitors are recommended. For
the best results, use low-ESR capacitors to keep Selecting the BST Resistor and Capacitor
the output voltage ripple low. It is recommended to place a resistor in series
with CBST to reduce the SW spike voltage. A
In buck mode, the output voltage ripple can be
higher resistance improves SW spike reduction,
calculated with Equation (12):
but it compromises efficiency. The
VOUT V 1 (12) recommended external CBST is a ceramic
ΔVOUT =  (1 - OUT )  (RESR + )
fSW  L VIN 8  fsw  COUT capacitor between 22nF and 220nF with a 10V
Where L is the inductance, and RESR is the or 16V DC derating. A maximum 20Ω resistor
equivalent series resistance (ESR) of the output with a 0603/0402 package is recommend for
capacitor. For ceramic capacitors, the efficiency and EMI performance.
capacitance dominates the impedance at the Output Short Circuits
switching frequency, and causes the majority of The voltage transient on the ISPx and ISNx
the output voltage ripple. For simplification, the inputs during a short circuit is dependent on the
output voltage ripple can be estimated with output capacitance and the cable harness
Equation (13): impedance. The inductance associated with a
VOUT V long cable harness resonates with the charge
VOUT =  (1 − OUT ) (13) stored on the output capacitor, which forces the
8  fSW  L  COUT
2
VIN
ISPx and ISNx voltages to ring below ground.
For tantalum or electrolytic capacitors, the ESR The negative voltage and current are dependent
dominates the impedance at the switching on the parasitic cable harness’s inductance and
frequency. For simplification, the output ripple resistance.
can be calculated with Equation (14): When using a long cable harness, a diode is
VOUT V recommended to clamp the negative voltage
VOUT =  (1 − OUT )  RESR (14)
across the ISPx and ISNx inputs (see Figure 9).
fSW  L VIN
To meet the shunt FET dimming and LED matrix ILED = 4A

L2
manager device application requirements, VOUT SW1 LED+
must have a fast transient speed. A large output ISP1 COUT

capacitance means it will take too long to charge
VOUT up to high. When the output is shorted, ISN1
the output capacitor’s energy bypasses through LED-

PGND1
the shunt FET. The FET may be damaged if the
capacitance is too high and the slew rate is too Figure 9: Transient Protection Using an External
Diode
fast. For these scenarios, a 100nF to 1µF
capacitor is recommended. Place the diode close to the output capacitor and
Selecting the VCC Capacitor ensure that the current flowing through the ISPx
and ISNx nodes under negative transient
The device is powered by an external 5V supply conditions is below the absolute maximum rating
connected to the VCC pin. Operation is enabled of the device.
when VCC exceeds its rising threshold (typically
4.2V) and is disabled when VCC drops below the

It is recommended to use a low forward voltage

Schottky diode or a fast recovery silicon diode VIN
VOUT
with a reverse blocking voltage rating greater

than the maximum output voltage. IL
If an output short occurs, a UV condition is

detected, and the device responds based on the Without the VOUT-to-VIN Diode t
selected UVP action.
LED Open Load VIN + 0.7V
If an LED open condition occurs, the MPQ7210 VIN
switches with a maximum duty cycle close to VOUT
100%, which makes VOUT rise close to VIN. The IL
dynamic behavior of the buck converter’s VOUT

during an LED open is influenced by the IL,
With the VOUT-to-VIN diode t
output capacitance (COUT), and VIN.
Figure 10: LED Load Open Condition
The switching operation under open-load
conditions makes inductor and output capacitor Selecting the SW-to-PGND Node Diode
resonance, forcing VOUT to oscillate. This The SW-to-PGND node diode is necessary for
oscillation may result in output overshoot with a most cases. The forward voltage of the body
small COUT. At LED load hot-plug conditions, this diode drops at high temperatures; at heavy
overshoot may exceed the ISPx and ISNx loads, there is a sub-injection current that goes
breakdown voltages, so it is recommended to through the LS-FET’s body diode. In this
connect a larger-value capacitor or a diode scenario, a Schottky diode with a low forward
(IN4148) from VOUT to VIN (see Figure 10). voltage (e.g. B360) is required.

PCB Layout Guidelines 6. Place the VCC capacitor as close to VCC

Efficient PCB layout, especially for the input and GND as possible.
capacitor placement, is critical for stable 7. Place the SW-to-PGND diode close to the
operation. A 4-layer layout is strongly SW pin and the PGND pin.
recommended to improve thermal performance.
For the best results, refer to Figure 11 and follow 8. Route SW and BST away from sensitive
the guidelines below: analog areas, such as ISPx and ISNx traces.
1. Place the symmetric input capacitors as 9. Route the ISPx and ISNx sense lines close
close to VIN1, VIN2, and GND as possible. together with a Kelvin connection to reduce
the line drop error.
2. Use a large ground plane to connect directly
to PGND. 10. The top layer should include the power,
signal, and GND.
3. Add vias near PGND if the bottom layer is a
ground plane. 11. Cover GND in all areas on the top layer,
except for the signal and power path.
4. Ensure that the high-current paths at GND
and VINx have short, direct, and wide 12. The second layer should only include GND
traces. to shield noise interference on the top layer.
5. Place the ceramic input capacitor, especially 13. The third layer should include the power,
the small package size (0603) input bypass signal, and GND.
capacitor, as close to VIN and PGND as 14. Cover GND in all areas on the bottom layer,
possible to minimize high-frequency noise. except for the signal and power path.
Top Layer Mid-Layer 1
Mid-Layer 2 Bottom Layer

Figure 11: Recommended PCB Layout
Note:
10) The recommended PCB layout is based on Figure 12 on page 48.

TYPICAL APPLICATION CIRCUITS

CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 CA1 CB1 CA2 CB2
EMI Filter 22nF/ 22nF/ 22nF/ 22nF/ 10µF/10µF/ L2 47µF 4.7µF/ 4.7µF/0.1µF/0.1µF/
100V 100V 100V 100V L1 100V 100V 4.7µH 100V 100V 100V 100V 100V
0603 0603 0603 0603 1210 1210 1210 1210 0603 0603 18
VEMI VIN VIN1/ BST1
13, VIN2
RA3 VIN
21 D5
0Ω
RASE1 IN4148
GND CA3 L3 200m
GND 68µH
VCC 2 ILED=2A
VCC
C4
VCC 190.1µF 1206 LED+
SW1
4.7µF D3
The EMI filter is not RA1
16V MPQ7210 22 B260
CAO1
1µF/ D1
VCC ISP1 RASE2
necessary if VIN is not 100k GND 25 100V IN4148
EN1 EN1 23 GND 200m 1206
connected to the battery RA2 ISN1
VCC 100k 26 1206
CN1 DIM1 DIM1 LED-
VCC RB1 16
100k BST2
1 2 9
EN2 EN2 RB3 VIN GND
R5 VCC RB2
3 4 100k 8 0Ω D6
SI 1k DIM2 DIM2 RBSE1
5 VCC R4 1 CB4 L4 IN4148
6 /FS 200m
SO 68µH
GND 100k 15 0.1µF ILED = 2A
7 8 /CS 4 /CS 1210 LED+
CK SW2
D4
9 10 5 CBO1
/CS VCC CK CK 12 B260 1µF/ D2
MPQ2013AGQ ISP2 RBSE2
1 VCC = 5V 100V
GND 8 6 GND 200m IN4148
VIN2: 6V to 36V SI SI 11 1206
IN OUT ISN2
C4 R10 5 30.9k
1µF/ 2 C7 7 1210 LED-
EN FB R9 SO SO
50V 3 4.7µF/ N/C AGND PGND1 PGND2
100k NC1
4 16V GND
GND 6 R8 10, 17, 24 3 20 14
NC2
9 7 10k
PAD NC3
GND
Figure 12: Typical Application Circuit (OTP, Dual-Channel, fSW = 420kHz, ILED = 2A/Channel)
EMI Filter 22nF/ 22nF/ 22nF/ 22nF/ 10µF/10µF/ L1 47µF 10µF/ 10µF/ 0.1µF/ 0.1µF/
100V 100V 100V 100V FB1 100V 100V 4.7µH 100V 100V 100V 100V 100V
0603 0603 0603 0603 1210 1210 1210 1210 0603 0603 18
VEMI VIN VIN1/ BST1
13, VIN2 VIN
RA3
21
0Ω
RASE1 D1
GND GND CA3 200m
L2
VCC 2 0.1µF ILED = 2A
VCC VCC 19
C4 SW1 1210 LED+
4.7µF 68µH
The EMI filter is not
RA1
16V MPQ7210 22
B260
D2
CAO1
1µF/
necessary if VIN is not VCC ISP1 RASE2
100k GND 25 100V
connected to the battery. EN1 EN1 23 200m 1206
RA2 ISN1
VCC 100k 26 1210
CN1 DIM1 DIM1 LED-
VCC 16
BST2
GND
1 2 9
EN2 GND
R5
3 4 8
SI 1k DIM2
5 VCC R4 1
6 SO /FS
GND 100k
7 8 /CS 4 /CS 15
CK SW2
9 10 5
/CS CK CK
VCC 12
MPQ2013AGQ ISP2
1 VCC = 5V 6
GND 8 SI SI
IN OUT ISN2
11
VIN2: 6V to 36V C4 R10 2
5 30.9k 7
1µF/ C7 SO SO
EN FB R9
100k NC1
4 16V
GND 6 R8 10, 17, 24 3 20 14
NC2
9 7 10k
PAD NC3
GND
Figure 13: Typical Application Circuit (OTP, Dual-Channel When Using Only 1 Channel, fSW = 420kHz, ILED
= 2A/Channel)

TYPICAL APPLICATION CIRCUITS (continued)

CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 CA1 CA2 CA3 CA4
22nF/ 22nF/ 22nF/ 22nF/ 10µF/10µF/ L1 47µF 10µF/ 10µF/ 0.1µF/ 0.1µF/
EMI Filter 100V 100V 100V 100V FB1 100V 100V 100V 100V
100V 100V 4.7µH 100V
0603 0603 0603 0603 1210 1210 1210 1210 0603 0603 V 18
VEMI IN VIN1/ BST1
13, VIN2 VIN
21 R3
0Ω D1
RSE1
GND GND C3 100m
L2 IN4148 ILED = 4A
2
VCC VCC 190.1µF LED+
C4 SW1 2010
68µH
The EMI filter is not
4.7µF
16V
MPQ7210 22
D2
B260
CO1 CO2
0.47µF/
R1 RSE2 0.47µF/
necessary if VIN is not VCC 100k GND ISP1
25 100V 100V
connected to the battery. EN1 EN1 23 100m 1206 1206
R2 ISN1
VCC 100k 26
DIM1 DIM1 2010
CN1 LED-
1 2 9
EN2 GND
R5
3 4 8
SI 1k DIM2 16
5 VCC R4 BST2 BST1
6 SO 1
GND /FS
7 8 VCC 100k
CK
/CS 4 /CS SW2
15 SW1
9 10 CS
CK 5 CK
GND VCC ISP2 12
MPQ2013AGQ
1 VCC = 5V 6
8 SI SI
IN OUT 11
VIN2: 6V to 36V C4 5 30.9k ISN2
1µF/
R10 2 C7 SO 7 SO
EN FB R9
100k NC1
4 16V
GND 6 R8 10, 17, 24 3 20 14
NC2
9 7 10k
PAD NC3
GND
Figure 14: Typical Application Circuit (OTP, Single-Channel, fSW = 420kHz, ILED = 4A)
EMI Filter 22nF/ 22nF/ 22nF/ 22nF/ 10µF/10µF/ L1 47µF 10µF/10µF/ 0.1µF/ 0.1µF/
100V 100V 100V 100V FB1 100V 100V 4.7µH 100V 100V 100V 100V 100V
0603 0603 0603 0603 1210 1210 1210 1210 0603 0603 18
VEMI VIN VIN1/ BST1
13, VIN2
RA3 VIN
21
0Ω
GND CA3 L2 RASE1
GND 15µH
2 200m ILED = 1A
VCC
C4
VCC 190.1µF LED+
SW1
4.7µF 1210 CAO1
VCC RA1
16V MPQ7210ISP1 22
B160
1µF/
100k GND 25 100V
EN1 EN1 23 GND 1206
RA2 ISN1
CN1 VCC 100k 26
VCC DIM1 DIM1 LED-
1 2 VCC RB1 16
100k BST2
R5 EN2 9
EN2 RB3 VIN GND
3 4 RB2
SI 1k VCC 0Ω
100k 8
5 6 DIM2 DIM2
SO VCC R4 1 CB4 L3
GND /FS RBSE1
7 8 15µH
CK 100k
4 15 0.1µF 200m ILED = 1A
/CS /CS SW2 LED+
9 10 VCC
/CS MPQ2013AGQ 1210 CBO1
VCC = 5V 5 B160
1 CK CK 12 1µF/
8 ISP2
GND IN OUT 6 100V
VIN2: 6V to 36V C4 R10 5 SI SI GND 1206
2 R9 C7 11
1µF/ EN FB ISN2
50V 3 30.9k 4.7µF/ 7 LED-
100k NC1 SO SO
4 16V
GND 6 N/C AGND PGND1 PGND2
NC2 R8 GND
9 7 10k 10, 17, 24 3 20 14
PAD NC3
GND
Figure 15: Typical Application Circuit (OTP, Dual-Channel, fSW = 2.3MHz, ILED = 1A/Channel)

PACKAGE INFORMATION
QFN-26 (5mmx5mm)
Wettable Flank
PIN 1 ID
MARKING
PIN 1 ID
0.30X45° TYP.
PIN 1 ID
INDEX AREA
0.075X45°
TOP VIEW BOTTOM VIEW
SIDE VIEW SECTION A-A
NOTE:
1)THE LEAD SIDE IS WETTABLE.

2) ALL DIMENSIONS ARE IN MILLIMETERS.
3) EXPOSED PADDLE SIZE DOES NOT
INCLUDE MOLD FLASH.
4) LEAD COPLANARITY SHALL BE 0.08
MILLIMETERS MAX.
5) DRAWING CONFIRMS TO JEDEC MO-220.
6) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN

CARRIER INFORMATION
Pin1 1 1 1 1
ABCD ABCD ABCD ABCD
Feed Direction
Carrier Carrier
Package Quantity/ Quantity/ Quantity/ Reel
Part Number Tape Tape
Description Reel Tube Tray Diameter
Width Pitch
MPQ7210GUE- QFN-26
5000 N/A N/A 13in 12mm 8mm
xxxx-AEC1-Z (5mmx5mm)

REVISION HISTORY
Revision # Revision Date Description Pages Updated
1.0 10/18/2023 Initial Release -
Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.


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MPQ7210

60V, 2A, Synchronous,

MPQ7210 Rev. 1.0 MonolithicPower.com 1

POWER LOSS (W)

MPQ7210 Rev. 1.0 MonolithicPower.com 2

MPS: MPS prefix

DIM1 EN1 N/C ISN1 ISP1 VIN1

DIM2 EN2 N/C ISN2 ISP2 VIN2

MPQ7210 Rev. 1.0 MonolithicPower.com 3

MPQ7210 Rev. 1.0 MonolithicPower.com 4

ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance θJA θJC

MPQ7210 Rev. 1.0 MonolithicPower.com 5

VCC voltage (VCC) UVLO

Register setting = 220kHz 180 220 320 kHz

MPQ7210 Rev. 1.0 MonolithicPower.com 6

ELECTRICAL CHARACTERISTICS (continued)

MPQ7210 Rev. 1.0 MonolithicPower.com 7

tFSIV tSOV tSOTRI

Figure 1: SPI Model 3

MPQ7210 Rev. 1.0 MonolithicPower.com 8

VIN Shutdown Current vs. VIN Standby Current vs.

VIN UVLO Threshold vs. VCC Shutdown Current vs.

VCC Standby Current vs. VCC UVLO Threshold vs.

1.7 3.9 Rising

MPQ7210 Rev. 1.0 MonolithicPower.com 9

TYPICAL CHARACTERISTICS (continued)

HS Switch On Resistance vs. LS Switch On Resistance vs.

Peak Current Limt vs.

Switching Frequency vs. Switching Frequency vs.

MPQ7210 Rev. 1.0 MonolithicPower.com 10

TYPICAL CHARACTERISTICS (continued)

Switching Frequency vs.

Minimum Off Time vs.

Current-Sense Voltage vs.

MPQ7210 Rev. 1.0 MonolithicPower.com 11

TYPICAL CHARACTERISTICS (continued)

Output UV Threshold vs.

MPQ7210 Rev. 1.0 MonolithicPower.com 12

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency vs. Input Voltage Efficiency vs. Input Voltage

POWER LOSS (W)

POWER LOSS (W)

Efficiency vs. Input Voltage Efficiency vs. Input Voltage

POWER LOSS (W)

Efficiency vs. Input Voltage Efficiency vs. Input Voltage

POWER LOSS (W)

MPQ7210 Rev. 1.0 MonolithicPower.com 13

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Efficiency vs. Input Voltage Efficiency vs. Input Voltage

POWER LOSS (W)

Case Temperature Rising vs. Case Temperature Rising vs.

CASE TEMPERATURE RISING ( C)

L= 68µH (VLED = 36V), L= 68µH

MPQ7210 Rev. 1.0 MonolithicPower.com 14

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Efficiency vs. Input Voltage Efficiency vs. Input Voltage

POWER LOSS (W)

POWER LOSS (W)

Case Temperature Rise vs. Case Temperature Rise vs.

MPQ7210 Rev. 1.0 MonolithicPower.com 15